Integrated Circuit Systems, Inc. ICS9248-56 Frequency Timing Generator for Pentium II Systems General Description Features The ICS9248-56 is the Main clock solution for Notebook designs using the Intel 440BX style chipset. Along with an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system. • Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-56 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. • • • Block Diagram • • Generates the following system clocks: - 2CPU(2.5V) up to 100MHz. - 6 PCI(3.3V) @ 33.3MHz (Includes one free running). - 1 REF clks (3.3V) at 14.318MHz. - 1 Fixed clock at 48MHz - 1 Fixed clock at 48 or 24MHz Skew characteristics: - CPU – CPU<175ps - PCI – PCI < 500ps - CPU(early) – PCI = 1.5ns – 4ns. Supports Spread Spectrum modulation for CPU and PCI clocks, 0.5% down spread Efficient Power management scheme through stop clocks and power down modes. Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal. 28 pin 209mil SSOP and 173mil TSSOP Pin Configuration 28 pin SSOP and TSSOP Power Groups VDD, GND = PLL core VDDREF, GNDREF = REF(0:1), X1, X2 VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4) VDD48, GND48 = 48MHz, 48/24MHz Pentium is a trademark on Intel Corporation. 9248-56 Rev E 12/27/00 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-56 Pin Descriptions Pin number Pin name Type Description 1 2 3 4 5,6,9,10,11 7 8 12 13 GNDREF X1 X2 PCICLK_F PCICLK (1:5) GNDPCI VDDPCI VDD48 48 MHz Power Input Output Output Output Power Power Power Output 14 TS#/48/24MHz Output 15 GND48 Power 16 SEL 100/66# Input 17 PD# Input 18 CPU_STOP# Input 19 VDD Power 20 PCI-Stop# Input 21 22 23,24 25 GND GNDL CPUCLK(1:0) VDDL Power Power Output Power 26 SPREAD# Output 27 REF0/SEL48# Output 28 VDDREF Power Ground for 14.318 MHz reference clock outputs 14.318 MHz crystal input 14.318 MHz crystal output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP# 3.3 V PCI clock outputs, generating timing requirements for Pentium II Ground for PCI clock outputs 3.3 V power for the PCI clock outputs 3.3 V power for 48/24 MHz clocks 3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices 3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for testing, active high = normal operation Ground for 48/24 MHz clocks control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at least 3 CPU clocks. Isolated 3.3 V power for core Synchronous active low input used to stop the PCICLK in active low state. It will not effect PCICLK_F or any other outputs. Isolated ground for core Ground for CPU clock outputs 2.5 V CPU clock outputs 2.5 V power for CPU clock outputs Power-on spread spectrum enable option. Active low = spread spectrum clocking enable. Active high = spread spectrum clocking disable. 3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option. Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14. 3.3 V power for 14.318 MHz reference clock outputs. 2 ICS9248-56 Select Functions (Functionality determined by TS# and SEL100/66# pin, see below) Functionality PCI, PCI_F CPUCLK REF0 Tristate HI - Z HI - Z HI - Z Testmode TCLK/21 TCLK/61 TCLK1 Notes: 1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode. SEL 100/66# TS# Function 0 0 Tri-State 0 - (Reserved) 0 - (Reserved) 0 1 Active 66.6MHz CPU, 33.3 PCI 1 0 Test Mode 1 - (Reserved) 1 - (Reserved) 1 1 Active 100MHz CPU, 33.3 PCI Power Management Clock Enable Configuration C P U _ S TO P # P C I _ S TO P # X X 0 0 0 1 1 0 1 1 P W R _ DW N # 0 1 1 1 1 CPUCLK L ow Low Low 100/66.6MHz 100/66.6MHz PCICLK PCICLK_F L ow L ow Low 33.3MHz 33.3 MHz 33.3MHz Low 33.3MHz 33.3 MHz 33.3MHz REF Stopped Running Running Running Running Crystal O ff Running Running Running Running VCOs O ff Running Running Running Running Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also. ICS9248-56 Power Management Requirements SIGNAL SIGNAL STATE C P U _ S TO P # 0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1 1 (Normal Operation)3 0 (Power Down)4 P C I _ S TO P # PD# L a t e n cy No. of rising edges of free running PCICLK 1 1 1 1 3ms 2max Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF will be stopped independant of these. 3 ICS9248-56 CPU_STOP# Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-56. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-56. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9248-56. It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-56 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state. 4 ICS9248-56 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9248-56 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated. 5 ICS9248-56 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0 V; Inputs with pull-up resistors Input Low Current IIL2 Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND Power Down IDD3.3PD Supply Current VDD = 3.3 V; Input frequency Fi 1 Input Capacitance CIN Logic Inputs CINX X1 & X2 pins 1 Transition Time Ttrans To 1st crossing of target Freq. Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. Skew1 TCPU-PCI VT = 1.5 V; MIN 2 VSS-0.3 -5 -200 TYP 0.1 2.0 -100 60 66 70 11 14.318 27 36 1.5 2.4 MAX UNITS VDD+0.3 V 0.8 V 5 µA µA µA 180 mA 180 mA 600 µA 16 5 45 3 3 4 MHz pF pF ms ms ns 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Operating IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz Supply Current IDD2.5OP100 CL = 0 pF; Select @ 100 MHz Skew1 tCPU-PCI2 VT = 1.5 V; VTL = 1.25 V 1.5 1 Guaranteed by design, not 100% tested in production. 6 TYP 16 23 MAX 72 100 UNITS mA mA 3 4 ns ICS9248-56 Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH2B IOH = -12.0 mA 1.8 Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V 27 1 Rise Time tr2B VOL = 0.4 V, VOH = 2.0 V 0.4 1 VOH = 2.0 V, VOL = 0.4 V 0.4 Fall Time tf2B VT = 1.25 V 44 Duty Cycle dt2B1 1 VT = 1.25 V Skew tsk2B tjcyc-cyc2B1 VT = 1.25 V Jitter VT = 1.25 V tj1s2B1 1 tjabs2B VT = 1.25 V -250 TYP 2.3 0.31 MAX 1.15 1.4 48 134 186 52 150 1.6 1.6 55 175 250 150 +250 TYP 3.3 0.1 MAX 0.4 -22 57 UNITS V V mA mA 0.4 -27 UNITS V V mA mA ns ns % ps ps ps ps 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL IOH = -18 mA Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V Rise Time 1 MIN 2.1 16 tr1 VOL = 0.4 V, VOH = 2.4 V 1.6 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 1.8 2 ns dt1 VT = 1.5 V 50 55 % Skew tsk1 tjcyc-cyc1 VT = 1.5 V VT = 1.5 V 222 186 500 500 ps ps Jitter tj1s1 tjabs1 VT = 1.5 V VT = 1.5 V 52 200 150 500 ps ps Fall Time 1 1 Duty Cycle 1 1 CONDITIONS 45 Guaranteed by design, not 100% tested in production. 7 ICS9248-56 Electrical Characteristics - REF/48MHz/24MHz TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -12 mA Output Low Voltage VOL5 IOL = 9 mA VOH = 2.0 V Output High Current IOH5 VOL = 0.8 V Output Low Current IOL5 Rise Time Fall Time 1 1 Duty Cycle Jitter1 Jitter1 1 MIN 2.6 16 TYP 3.1 0.17 -44 42 MAX 0.4 -22 UNITS V V mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.4 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.1 4 ns 53 185 385 169 469 55 250 800 250 800 % ps ps ps ps dt5 tj1σ5 tjabs5 tj1σ5 tjabs5 VT = 1.5 V VT = 1.5 V, REF VT = 1.5 V, REF VT = 1.5 V, 48 MHz VT = 1.5 V, 48 MHz 45 8 ICS9248-56 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user All unmarked capacitors are 0.01 F ceramic 9 ICS9248-56 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A - A1 0.05 - .002 - A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 SEE VARIATIONS D 2.00 .079 .0035 .010 SEE VARIATIONS E 7.40 E1 5.00 5.60 0.65 BASIC .197 .220 0.0256 BASIC 0.55 0.95 SEE VARIATIONS .022 .037 SEE VARIATIONS e L N α 8.20 - 0° .291 .323 8° 0° 8° MIN MAX MIN 9.90 10.50 .390 .413 MO-150 JEDEC Doc.# 10-0033 6/1/00 Rev B VARIATIONS D mm. N 28 D (inch) MAX Ordering Information ICS9248F-56 Example: ICS XXXXy F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 10 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-56 SY MBOL In Millimeters COMMON DIMENSIONS MIN MA X In Inches COMMON DIMENSIONS MIN MA X A - 1.20 - .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 SEE V A RIA TIONS D .0035 .008 SEE V A RIA TIONS 6.40 BA SIC E E1 4.30 e 4.50 0.252 BA SIC .169 0.65 BA SIC L 0.45 0.75 SEE V A RIA TIONS N α aaa .177 0.0256 BA SIC .018 .030 SEE V A RIA TIONS 0° 8° 0° 8° - 0.10 - .004 MIN MA X MIN 9.60 9.80 V A RIA TIONS D mm. N 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 mil) (173 mil) 28 D (inch) MA X .378 .386 M O -1 53 J E D E C 7 / 6/ 00 R ev B D o c . # 1 0-0 0 3 8 Ordering Information ICS9248yG-56-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 11 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.