ICS ICS9248-61

Integrated
Circuit
Systems, Inc.
ICS9248-61
Frequency Timing Generator for Pentium II Systems
General Description
Features
The ICS9248-61 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
•
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-61 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
•
•
•
Block Diagram
•
•
Generates the following system clocks:
- 2CPU(2.5V) up to 100MHz.
- 7 PCI(3.3V) @ 33.3MHz (Includes one free running).
- 2 REF clks Fixed (3.3V) 48MHz at 14.318MHz.
Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 250ps
- PCI_E (early) – PCI = 2.1ns
- CPU(early) – PCI = 1.5ns – 4ns
Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
Efficient Power management scheme through stop clocks
and power down modes.
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
28 pin 209mil SSOP.
Pin Configuration
28 pin SSOP
Power Groups
GNDR/C = REFCLK, CORE, Crystal
VDDCOR = Core
GNDLCPU, VDDCPU = CPU
GND48, VDD48 = 48MHz
VDDPCI, GNDPCI - PCICLK, PCICLK_F, PCICLK_E
Pentium is a trademark on Intel Corporation.
9248-61 Rev B 1/8/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-61
Pin Descriptions
Pin number
Pin name
Type
Description
2
3
4
7
8
12
13
X1
X2
PCICLK_F
GNDPCI
VDDPCI
PCICLK_E
VDD48
Input
Output
Output
Power
Power
Output
Power
14
SEL 100_66#/
48MHz
Input
15
GND48
Power
16
DIV4#
Input
17
PD#
Input
18
CPU_STOP#
Input
19
VDDCOR
Input
20
PCI-STOP#
Input
21
22
25
GNDR/C
GNDLCPU
VDDLCPU
Input
Power
Power
26
SPREAD#
Output
28
1,27
23,24
5,6,9,10, 11
VDDR
REF(0:1)
CPUCLK (0:1)
PCICLK (1:4)
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
Ground for PCI clock outputs
3.3 V power for the PCI clock outputs
Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#
3.3 V power for 48 MHz clocks
on power-on control for the frequency of clocks at the CPU & PCICLK output pins. If
logic "0" is used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100
MHz frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
selects
Ground for 48 MHz clocks
Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular
frequecies
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
3.3 V power for the core
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
Ground for REFCLK, Crystal & Core
Ground for the CPU and Host clock outputs
2.5 V power for the CPU and Host clock outputs
power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
3.3 V power for the REFCLK and crystal clock outputs
3.3V, 14.318 MHz reference clock output.
2.5 V CPU and Host clock outputs
3.3 V PCI clock outputs, generating timing requirements
Input
Output
0utput
Output
2
ICS9248-61
Frequency Table
DIV4#
1
1
0
0
SEL
100/66#
1
0
1
0
CPU MHz
PCI MHz
100
66.69
25
16.65
33
33
8.32
8.32
Power Management
Clock Enable Configuration
C P U _ S TO P # P C I _ S TO P #
X
X
0
0
0
1
1
0
1
1
P W R _ DW N #
0
1
1
1
1
CPUCLK
L ow
Low
Low
100/66.6MHz
100/66.6MHz
PCICLK PCICLK_F
L ow
L ow
Low
33.3MHz
33.3 MHz 33.3MHz
Low
33.3MHz
33.3 MHz 33.3MHz
REF
Stopped
Running
Running
Running
Running
Crystal
O ff
Running
Running
Running
Running
VCOs
O ff
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry.
Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-61 Power Management Requirements
SIGNAL
SIGNAL STATE
C P U _ S TO P #
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1 (Enabled)1
1 (Normal Operation)3
0 (Power Down)4
P C I _ S TO P #
PD#
L a t e n cy
No. of rising edges of free running
PCICLK
1
1
1
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
3
ICS9248-61
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-61. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9248-61.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-61. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-61 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
4
ICS9248-61
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-61 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5
ICS9248-61
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
2
VIH
Input Low Voltage
VSS-0.3
VIL
Input High Current
VIN = VDD
IIH
Input Low Current
VIN = 0 V; Inputs with no pull-up resistors
-5
IIL1
Input Low Current
VIN = 0 V; Inputs with pull-up resistors
-200
IIL2
Operating
IDD3.3OP66 C L = 0 pF; Select @ 66MHz
Supply Current
IDD3.3OP100 C L = 0 pF; Select @ 100MHz
Power Down Supply
Current
Input frequency
Input Capacitance1
Transition Time
1
Clk Stabilization 1
Skew1
1
Fi
C IN
C INX
C L = 0 pF;
With input address to Vdd or GND
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
Ttrans
To 1st crossing of target Freq.
IDD3.3PD
TSTAB
TCPU-PCI1
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V;
TYP
0.1
2.0
-100
60
66
11
70
14.318
27
36
1.5
2.4
MAX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
180
mA
180
mA
600
16
5
45
µA
MHz
pF
pF
3
ms
3
ms
4
ns
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
Supply Current
1
Skew
1
SYMBOL
IDD2.5OP66
IDD2.5OP100
tCPU-PCI2
CONDITIONS
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
VT = 1.5 V; VTL = 1.25 V
Guaranteed by design, not 100% tested in production.
6
MIN
TYP
16
23
MAX
72
100
UNITS
mA
mA
1.5
3
4
ns
ICS9248-61
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
MIN
2
19
TYP
2.3
0.2
-41
37
MAX UNITS
V
0.4
V
-19
mA
mA
Rise Time
tr2B
1
VOL = 0.4 V, VOH = 2.0 V
1.25
1.6
ns
Fall Time
t f2B1
VOH = 2.0 V, VOL = 0.4 V
1
1.6
ns
Duty Cycle
d t2B1
VT = 1.25 V
48
55
%
1
VT = 1.25 V
30
175
ps
VT = 1.25 V
150
250
ps
VT = 1.25 V
VT = 1.25 V
40
150
ps
-250
140
+250
ps
MIN
2.4
TYP
3.1
0.1
-62
57
MAX UNITS
V
0.4
V
-22
mA
mA
Skew
tsk2B
Jitter, Cycle-to-cycle
tjcyc-cyc2B1
tj1s2B1
tjabs2B1
Jitter, One Sigma
Jitter, Absolute
1
CONDITIONS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew
Jitter, Cycle-to-cycle
Jitter, One Sigma
Jitter, Absolute
1
1
1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
16
tr1
VOL = 0.4 V, VOH = 2.4 V
1.5
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
1.1
2
ns
d t1
VT = 1.5 V
50
55
%
tsk1
VT = 1.5 V
VT = 1.25 V
140
250
500
500
ps
ps
17
150
ps
70
250
ps
t jcyc-cyc1
tj1s1
VT = 1.5 V
tjabs1
VT = 1.5 V
45
-250
Guaranteed by design, not 100% tested in production.
7
ICS9248-61
Electrical Characteristics - REF/48MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
Jitter, One Sigma
Jitter, Absolute
1
1
1
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.6
16
TYP
3.1
0.17
-44
42
MAX UNITS
V
0.4
V
-22
mA
mA
tr5
VOL = 0.4 V, VOH = 2.4 V
1.4
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V
1.1
4
ns
d t5
VT = 1.5 V
53
55
%
tj1s5
VT = 1.5 V
1
3
%
tjabs5
VT = 1.5 V
3
5
%
45
Guaranteed by design, not 100% tested in production.
8
ICS9248-61
COMMON
DIMENSIONS
SYMBOL
D
VARIATIONS
MIN.
NOM.
MAX.
N
MIN.
NOM.
MAX.
A
A1
A2
b
c
D
E
e
H
L
N
0.068
0.002
0.066
0.010
0.004
0.078
0.008
0.070
0.015
0.008
14
16
20
24
28
30
0.239
0.239
0.278
0.318
0.397
0.397
0.244
0.244
0.284
0.323
0.402
0.402
0.249
0.249
0.289
0.328
0.407
0.407
∝
0°
0.073
0.005
0.068
0.012
0.006
See Variations
0.209
0.0256 BSC
0.307
0.030
See Variations
4°
0.205
0.301
0.025
0.212
0.311
0.037
SSOP Package
Dimensions in inches
8°
Ordering Information
ICS9248F-61
Example:
ICS XXXX Y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
9
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.