Integrated Circuit Systems, Inc. ICS9148-46 Pentium/ProTM System Clock Chip General Description Features The ICS9148-46 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-03, and -12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), five PCI (3.3V), two REF (3.3V), one 48MHz, and one selectable 48_24MHz. Block Diagram Generates system clocks for CPU, PCI, 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SSOP Spread Sectrum operation optional for PLL1 CPU frequencies to 100MHz are supported. Pin Configuration 28 pin SSOP Power Groups VDD = Supply for PLL core VDD1 = REF(0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:3) VDD3 = 48MHz, 24/48MHz VDDL = CPUCLK (0:1) Ground Groups GND = Ground Source Core, CPUCLK (0:1) GND1 = REF(0:1), X1, X2 GND2 = PCICLK_F, PCICLK (0:5) GND3=48MHz, 24/48MHz Pentium is a trademark on Intel Corporation. 9148-46 Rev E 4/20/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-46 Pin Descriptions PIN NUMBER 1 PIN NAME GND1 TYPE PWR 2 X1 IN 3 4 5 6, 7, 9, 10 8 11 12 X2 GND2 PCICLK_F PCICLK (0:3) VDD2 VDD3 48MHz OUT PWR OUT OUT PWR PWR OUT 13 24_48MHz OUT 14 GND3 PWR 15 SEL100/66.6# IN 16 17 SCLK SDATA IN IN 18 PD# IN 19 CPU_STOP# IN 20 PCI_STOP# IN 21 22 23, 24 25 26 27 GN D VDD CPUCLK (1:0) VDDL REF1 VDD1 REF0 SEL 48# PWR PWR OUT PWR OUT PWR OUT IN 28 DESCRIPTION Ground for REF (0:1), X1, X2. XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output. Not affected by PCI_STOP# PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Poer for 48MHz Fixed CLK output @ 48MHz Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if pin 27=0 at power up. Ground for 48MHz Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2C input Data input for I2C input Asynchronous input when driven active (LOW) disables internal clocks, stops VCO early. All outputs are placed in a LOW state at the end of the curent cycle. Asynchronous input when driven active (LOW) stops CPUCLK(0:1) in a LOW state. Asynchronous input when driven active (LOW) stops PCICLK(0:3) in a LOW state. PCICLK_F is not affected. Ground for CPUCLK (0:1) and the core Power for PLL core CPU and Host clock outputs nominally 2.5V Power for CPU outputs, nominally 2.5V 14.318MHz Reference clock output Power for REF outputs. 14.318MHz clock output Latched input at power up. When low, pin 13 is 48MHz. 2 ICS9148-46 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ICS (Slave/Receiver) ACK Byte Count ACK Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 3 ICS9148-46 Serial Bitmap Byte 3: Functionality & Frequency Select & Spread Slect Register Bit Description 0: Center Spread ±0.255% 1: Down Spread 0 to -0.6% Bit CPU PCI 654 34.25 68.5 000 37.5 75.0 001 41.6 83.3 010 33.3 66.6 011 34.3 103 100 37.3 112 101 44.43 133.3 110 33.33 100 111 7 6:4 3 2 10 Byte 5: PW D 0 - Frequency is selected by hardware select SEL100/66.6# 1 - Frequency is selected by 6:4 above (Reserved) 00 - Normal operation 01 - Test mode 10 - Spread sprectrum ON 11 - Tristate all outputs 0 0 0 Bit Pin# Pin Name PWD 7 5 PCICLK_F 1 6 10 PCICLK3 1 5 9 PCICLK2 1 4 - - 0 3 7 PCICLK1 1 2 6 PCICLK0 1 1 0 - - 0 0 Description Bit Value = 0 Bit Value = 1 Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) (Reserved) (Reserved) Notes: 1 = Enabled; 0 = Disabled, outputs held low 00 Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 4: Byte 6: Bit Pin# Pin Name PWD 7 6 5 4 3 - - - 2 23 CPUCLK1 1 1 - - 0 0 24 CPUCLK0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Disabled) Enabled (low) Bit Notes: 1 = Enabled; 0 = Disabled, outputs held low Pin# Pin Name PWD 7 6 5 4 3 - - 0 0 0 0 0 2 26 REF1 1 1 - - 0 0 28 REF0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Disabled) Enabled (low) (Reserved) (Reserved) (Disabled) Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default 4 ICS9148-46 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0°C to +70°C 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL Input High Voltage VIH Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency VIL IIH IIL1 IIL2 Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization 1 Skew1 1 CONDITIONS MIN TYP 2 MAX UNITS VDD+0.3 V 0.8 5 V µA µA µA mA mA µA VSS-0.3 IDD3.3OP66 IDD3.3OP100 IDD3.3PD VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND Fi CIN CINX Ttrans Ts TSTAB TAGP-PCI1 VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; 0.1 2.0 -100 60 66 3 -5 -200 170 170 650 14.318 27 5 45 3 36 5 1 3 4 3.5 Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current 1 Skew 1 SYMBOL IDD2.5OP66 IDD2.5OP 100 IDD2.5PD tCPU-AGP tCPU-PCI2 CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; With input address to Vdd or GND VT = 1.5 V; VTL = 1.25 V Guaranteed by design, not 100% tested in production. 5 MIN 0 1 TYP 16 23 MAX 72 100 UNITS mA mA 10 100 µA 0.5 2.6 1 4 ns ns MHz pF pF ms ms ms ns ICS9148-46 Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc2B1 tj1s2B1 tjabs2B1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V MIN 2 19 45 -250 TYP 2.3 0.2 -41 37 1.25 1 48 30 150 40 140 MAX UNITS V 0.4 V -19 mA mA 1.6 ns 1.6 ns 55 % 175 ps 250 ps 150 ps +250 ps TYP 3.1 0.1 -62 57 MAX UNITS V 0.4 V -22 mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 1 tr1 VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns 1 tf1 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns dt1 VT = 1.5 V 50 55 % tsk1 VT = 1.5 V 140 500 ps tj1s1 VT = 1.5 V 17 150 ps tjabs1 VT = 1.5 V 70 500 ps Rise Time Fall Time Duty Cycle 1 1 Skew Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH1 VOL1 IOH1 IOL1 1 1 45 -500 Guaranteed by design, not 100% tested in production. 6 ICS9148-46 Electrical Characteristics - REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 29 TYP 3.1 0.17 -44 42 MAX UNITS V 0.4 V -22 mA mA 1 tr5 VOL = 0.4 V, VOH = 2.4 V 1.4 2 ns 1 tf5 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns dt5 VT = 1.5 V 54 57 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % Rise Time Fall Time Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH5 VOL5 IOH5 IOL5 1 1 47 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48, 24 MHz TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 16 TYP 3 0.14 -44 42 MAX UNITS V 0.4 V -22 mA mA 1 tr5 VOL = 0.4 V, VOH = 2.4 V 1.2 4 ns 1 tf5 VOH = 2.4 V, VOL = 0.4 V 1.2 4 ns dt5 VT = 1.5 V 52 55 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % Rise Time Fall Time Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH5 VOL5 IOH5 IOL5 1 1 45 Guaranteed by design, not 100% tested in production. 7 ICS9148-46 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user All unmarked capacitors are 0.01µF ceramic 8 ICS9148-46 COMMON DIMENSIONS SYMBOL D VARIATIONS MIN. NOM. MAX. N MIN. NOM. MAX. A A1 A2 b c D E e H L N 0.068 0.002 0.066 0.010 0.004 0.078 0.008 0.070 0.015 0.008 14 16 20 24 28 30 0.239 0.239 0.278 0.318 0.397 0.397 0.244 0.244 0.284 0.323 0.402 0.402 0.249 0.249 0.289 0.328 0.407 0.407 ∝ 0° 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4° 0.205 0.301 0.025 0.212 0.311 0.037 8° 28 Pin SSOP Package Ordering Information ICS9148yF-46 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.