ICS932S203 Integrated Circuit Systems, Inc. Frequency Generator with 133MHz Differential CPU Clocks Recommended Application: Servers based on Intel CK408 processors Output Features: • 4 Differential CPU Clock Pairs @ 3.3V • 7 PCI (3.3V) @ 33.3MHz • 3 PCI_F (3.3V) @ 33.3MHz • 1 USB (3.3V) @ 48MHz • 1 DOT (3.3V) @ 48MHz • 1 REF (3.3V) @ 14.318MHz • 1 3V66 (3.3V) @ 66.6MHz • 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz • 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz • 1 66MHz_IN/3V66 (3.3V) @ Input/66MHz Features: • Supports spread spectrum modulation, down spread 0 to -0.5%. • Efficient power management scheme through PD# and PCI_STOP#. • Uses external 14.318MHz crystal • Stop clocks and functional control available through SMBus interface. Key Specifications: • CPU Output Jitter <150ps • 3V66 Output Jitter <250ps • CPU Output Skew <150ps Block Diagram Pin Configuration 56-Pin 300mil SSOP/TSSOP * These inputs have 150K internal pull-up resistor to VDD. Functionality FS1 FS0 0601E—12/22/04 CPU (MHz) 3V66 (MHz) 66Buff[2:0] 3V66[4:2] (MHz) PCI_F PCI (MHz) 1 0 100 66.6 66.6 In path 66.6 in/2 1 1 133.3 66.6 66. In path 66.6 in/2 0 0 100 66.6 66.6 33.3 0 1 133.3 66.6 66.6 33.3 mid 0 Hi-Z Hi-Z Hi-Z Hi-Z mid 1 Tclk/2 Tclk/4 Tclk/4 Tclk/8 ICS932S203 Pin Configuration PIN NUMBER PIN NAME TYPE 1, 8, 14, 19, 26, 32, 37, 46, 50 VDD PWR 2 X1 X2 Cr ystal Input 3 X2 X1 Cr ystal Output DESCRIPTION 3.3V power supply 14.318MHz Cr ystal input 14.318MHz Cr ystal output 7, 6, 5 PCICLK_F (2:0) OUT Free running PCI clock not affected by PCI_STOP# for power management. 4, 9, 15, 20, 27, 31, 36, 41, 47 GND PWR Ground pins for 3.3V supply 18, 17, 16, 13, 12,11, 10 PCICLK (6:0) OUT PCI clock outputs 66MHz_OUT (2:0) OUT 66MHz buffered 66MHz_OUT from 66MHz_IN input. 3V66 (4:2) OUT 66MHz_IN IN 3V66_5 OUT PD# IN Invokes power-down mode. Active Low. 23, 22, 21 24 25 66MHz reference clocks, from internal VCO 66MHz input to buffered 66MHz_OUT and PCI clocks 66MHz reference clock, from internal VCO 28 Vtt_PWRGD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when FS[0:2] and MULTISEL0 inputs are valid and are ready to be sampled (active low) 29 SDATA I/O Data pin for SMBus circuitr y 5V tolerant 30 SCLK IN Clock pin of SMBus circuitr y 5V tolerant 33 3V66_0 OUT 66MHz reference clocks, from internal VCO Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running 34 PCI_STOP# IN 35 3V66_1/VCH_CLK OUT 38 48MHz_DOT OUT 48MHz output clock for DOT 39 48MHz_USB OUT 48MHz output clock for USB 40, 55 FS (1:0) IN 42 I REF OUT 43 MULTSEL0 IN MULTSEL0 input is sensed on power-up and then internally latched prior to the pin being used for output on 3V 14.318MHz clocks. 44, 48, 51, 53 CPUCLKC (3:0) OUT "Complementar y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 45, 49, 52, 54 CPUCLKT (3:0) OUT "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 56 REF OUT 14.318MHz reference clock. 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC) Special 3.3V input for Mode selection This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Power Groups (Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR (Digital) VDDPCI VDD3V66 VDDCPU 0601E—12/22/04 2 ICS932S203 Frequency Select Table FS2 FS1 CPU 3V66 (1:0) 66Buff (2:0) / 3V66 (4:2) 66 In / 3V66_5 PCI REF USB, DOT 1 0 100 66.6 66.6 In path 66.6 IN 66.6 in/2 14.318 48 1 1 133.3 66.6 66.6 In path 66.6 IN 66.6 in/2 14.318 48 0 0 0 1 100 133.3 66.6 66.6 66.6 66.6 66.6 66.6 33.3 33.3 14.318 14.318 48 48 mid 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z mid 1 Tclk/2 Tclk/4 Tclk/4 Tclk/4 Tclk/8 Tclk Tclk/2 note Buffer mode 66 Buffer mode 66 Driven 66 Driven 66 Tri-state outputs Tclk is at X1 input Host Swing Select Functions MULTISEL0 Board Target Trace/Term Z Reference R, Iref = VDD/(3*Rr) Output Current Voh @ Z 0 50 ohms Rr = 221 1%, Iref = 5.00mA Ioh = 4* I REF 1.0V @ 50 1 50 ohms Rr = 475 1%, Iref = 2.32mA Ioh = 6* I REF 0.7V @ 50 0601E—12/22/04 3 ICS932S203 Byte 0: Control Register Bit Bit 0 Bit 1 Bit 2 Pin# 55 40 Name B it 3 34 Bit 4 - Bit 5 35 Bit 6 - B it 7 - Type FS0 FS1 PW D 1 X X PCI_STOP#3 X R R R 1 3V66_1/VCH 0 RW 0 Spread Enabled Description (Reserved) Reflects the value of FS0 pin sampled on power up Reflects the value of FS1 pin sampled on power up Hardware mode: Reflects the value of PCI_STOP# pin sampled on PWD (Reserved) VCH Select 66MHz/48MHz 0=66MHz, 1=48MHz (Reserved) 0 RW 0=Spread Off, 1=Spread On PWD Type 1 RW 0=Disabled 1=Enabled 1 RW 0=Disabled 1=Enabled 1 RW 0=Disabled 1=Enabled 0 0 0 - 1 RW X R Byte 1: Control Register Bit Pin# Bit 0 52, 51 Bit 1 49, 48 Bit 2 45, 44 B it 3 B it 4 B it 5 5 2, 51 49, 48 45, 44 Bit 6 53, 54 Bit 7 43 Name CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 CPUCLKT3 CPUCLKC3 MULTSEL0 Description Reser ved Reser ved Reser ved 0=Disabled 1=Enabled Reflects the current value of MULTSEL0 Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via SMBus Byte 0 Bit 3. In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these modes. In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)]. 0601E—12/22/04 4 ICS932S203 Byte 2: Control Register Bit Bit 0 Bit 1 Bit 2 B it 3 B it 4 Bit 5 B it 6 Bit 7 Pin# 10 11 12 13 16 17 18 - Name PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 - PWD 1 1 1 1 1 1 1 0 Type RW RW RW RW RW RW RW - Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) Byte 3: Control Register Bit Bit 0 Bit 1 Bit 2 Pin# 5 6 7 Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PWD 1 1 1 Type RW RW RW Bit 3 5 PCICLK_F0 0 RW Bit 4 6 PCICLK_F1 0 RW Bit 5 7 PCICLK_F2 0 RW Bit 6 Bit 7 39 38 48MHz_USB 48MHz_DOT 1 1 RW RW Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled Allow control of PCICLK_F0 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F1 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F2 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running 0=Disabled 1=Enabled 0=Disabled 1=Enabled Byte 4: Control Register Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# 21 22 23 24 35 33 - Name 66MHz_OUT0/3V66-2 66MHz_OUT0/3V66-3 66MHz_OUT0/3V66-4 3V66_5 3V66_1/VCH_CLK 3V66_0 - PWD 1 1 1 1 1 1 0 0 Type RW RW RW RW RW RW R R Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 0601E—12/22/04 5 Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) (Reserved) ICS932S203 Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# X X X X X X X X Name 48MHz_USB 48MHz_USB 48MHz_DOT 48MHz_DOT - PWD 0 0 0 0 0 0 0 0 Type RW RW RW RW - PWD 1 0 0 0 X X X X Type R R R R R R R R Description USB edge rate cntrol USB edge rate cntrol DOT edge rate control DOT edge rate control (Reserved) (Reserved) (Reserved) (Reserved) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# X X X X X X X X Name Vendor ID Bit0 Vendor ID Bit1 Vendor ID Bit2 Vendor ID Bit3 Revision ID Bit0 Revision ID Bit1 Revision ID Bit2 Revision ID Bit3 Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 0601E—12/22/04 6 Description (Reserved) (Reserved) (Reserved) (Reserved) Revision ID values will be based on individual device's revision ICS932S203 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL CONDITIONS VIH VIL VIN = VDD I IH I IL1 VIN = 0 V; Inputs with no pull-up resistors MIN 2 VSS - 0.3 -5 -5 TYP MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA Input Low Current I IL2 Operating Supply Current I DD3.3OP I DD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 1 Transition time Settling time1 Clk Stabilization1 Delay 1 I DD3.3PD Fi Lpin CIN COUT CINX Ttrans Ts VIN = 0 V; Inputs with pull-up resistors -200 CL = Full load; Select @ 100 MHz 229 230 360 CL =Full load; Select @ 133 MHz 220 233 360 mA 7 5 6 45 3 3 mA MHz nH pF pF pF ms ms 60 VDD = 3.3 V mA 14.318 Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency 27 TSTAB From VDD = 3.3 V to 1% target frequency t PZH,t PZL Output enable delay (all outputs) t PHZ,t PLZ Output disable delay (all outputs) 1 3 10 ms ns 1 10 ns 1 Guaranteed by design, not 100% tested in production. 0601E—12/22/04 7 ICS932S203 Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 1 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP 770 MAX UNITS NOTES Ω 1 850 1 mV -150 5 150 756 -7 350 1150 -300 250 550 mV 1 1 1 12 140 mV 1 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 332 344 30 30 700 700 125 125 1 mV Measurement from differential 45 49 55 % wavefrom tsk3 VT = 50% Skew 8 100 ps Measurement from differential tjcyc-cyc 60 150 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Duty Cycle dt3 0601E—12/22/04 8 1 1 1 ICS932S203 Electrical Characteristics - PCICLK Un-Buffered Mode TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 Duty Cycle VT = 1.5 V dt1 1 VT = 1.5 V Skew tsk1 1 VT = 1.5 V tjcyc-cyc Jitter,cycle to cyc 1 MIN TYP MAX 12 2.4 33 55 1.32 1.39 0.55 -33 38 0.5to 2 0.5 to 2 45 52 247 111 55 500 500 MIN TYP MAX 12 2.4 33 55 1.29 1.32 0.55 -33 38 0.5to 2 0.5 to 2 51.9 209 107 55 500 500 -33 30 0.5 0.5 UNITS MHz Ω V V mA mA ns ns % ps ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK Buffered Mode TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance RDSP11 VO = VDD*(0.5) Output High Voltage VOH1 IOH = -1 mA IOL = 1 mA Output Low Voltage VOL1 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL1 Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle VT = 1.5 V dt11 1 Skew tsk1 VT = 1.5 V tjcyc-cyc1 VT = 1.5 V Jitter,cycle to cyc 1 Guaranteed by design, not 100% tested in production. 0601E—12/22/04 9 -33 30 0.5 0.5 45 UNITS MHz Ω V V mA mA ns ns % ps ps ICS932S203 Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0] TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 Output Impedance RDSP1 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA 1 Output Low Voltage VOL IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle VT = 1.5 V dt1 Skew Jitter 1 1 tsk1 1 tjcyc-cyc MIN 12 2.4 -33 30 0.5 0.5 45 VT = 1.5 V VT = 1.5 V 3V66 TYP MAX UNITS 66.66 MHz 33 55 Ω V 0.55 V -33 mA 38 mA 1.38 2 ns 1.45 2 ns % 54.4 55 90 128 250 250 ps ps Guaranteed by design, not 100% tested in production. Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0] TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 Duty Cycle VT = 1.5 V dt1 Skew Jitter Skew Jitter 1 tsk1 1 VT = 1.5 V 1 tjcyc-cyc 1 tsk1 1 tjcyc-cyc 3V66 [1:0] VT = 1.5 V 3V66 [1:0] VT = 1.5 V 66MHz_OUT [2:0] VT = 1.5 V 66MHz_OUT [2:0] Guaranteed by design, not 100% tested in production. 0601E—12/22/04 10 MIN -33 30 0.5 0.5 1.44 1.36 0.55 -33 38 2 2 45 54.6 55 UNITS MHz W V V mA mA ns ns % 105 250 ps 121 169 89 300 250 300 ps ps ps 12 2.4 TYP 66.66 33 MAX 55 ICS932S203 Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 Output Impedance RDSP1 VO = VDD*(0.5) 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 48DOT Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V 48DOT Fall Time tf1 1 VOL = 0.4 V, VOH = 2.4 V VCH 48 USB Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V VCH 48 USB Fall Time tf1 20 2.4 -29 29 0.5 0.5 1 1 TYP 48 48 MAX 0.6 0.8 1.2 1.3 0.4 -23 27 1 1 2 2 UNITS MHz Ω V V mA mA ns ns ns ns 60 dt1 1 VT = 1.5 V 45 52.8 55 % VCH 48 USB Duty Cycle dt1 1 53.5 183 223 55 350 350 % 48 DOT Jitter VCH Jitter VT = 1.5 V VT = 1.5 V VT = 1.5 V 45 1 tjcyc-cyc 1 tjcyc-cyc MIN TYP MAX 20 2.4 48 48 DOT Duty Cycle 1 MIN ps ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 Output Impedance RDSP1 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA 1 Output Low Voltage VOL IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle VT = 1.5 V dt1 1 tjcyc-cyc VT = 1.5 V Jitter 1 Guaranteed by design, not 100% tested in production. 0601E—12/22/04 11 -29 29 1 1 45 1.25 1.15 53 723 UNITS MHz 60 Ω V 0.4 V -23 mA 27 mA 2 ns 2 ns % 55 1000 ps ICS932S203 General SMBus serial interface information The information in this section assumes familiarity with SMBus programming. For more information, contact ICS for an SMBus software program. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ICS (Slave/Receiver) ACK Byte Count ACK Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, SMBus component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator SMBus interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0601E—12/22/04 12 ICS932S203 Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation value. 66MHz_IN Tpd 66MHz_OUT Tpci PCICLK_F 3V66 No Relationship Group Skews at Common Transition Edges: (Buffered Mode) GROUP 3V66 66MHz_OUT PCI SYMBOL 3V66 66OUT PCI 66MHz_IN 66MHz_OUT Tpd 66MHz_OUT to PCI Tpci 1 CONDITIONS 3V66 (1:0) pin to pin skew 66MHz_OUT (2:0) pin to pin skew PCI_F (2:0) and PCI (6:0) pin to pin skew Propogation delay from 66MHz_IN to 66MHz_OUT (2:0) 66MHz_OUT (2:0) leads 33 MHz PCI Guaranteed by design, not 100% tested in production. 0601E—12/22/04 13 MIN TYP MAX UNITS 0 0 0 500 175 500 ps ps ps 2.5 4.5 ns 1.5 3.5 ns ICS932S203 Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. 3V66 (1:0) 3V66 (4:2) 3V66_5 Tpci PCICLK_F (2:0) PCICLK (6:0) Group Skews at Common Transition Edges: (Un-Buffered Mode) GROUP 3V66 PCI 3V66 to PCI SYMBOL CONDITIONS 3V66 3V66 (5:0) pin to pin skew PCI PCI_F (2:0) and PCI (6:0) pin to pin skew MIN 0 0 3V66 (5:0) leads 33MHz PCI 1.5 S3V66-PCI TYP MAX UNITS 500 ps 500 ps 3.5 ns 1 Guaranteed by design, not 100% tested in production. PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. Assertion of PCI_STOP# Waveforms PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz 0601E—12/22/04 14 ICS932S203 PD# - Assertion (transition from logic "1" to logic "0") When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200MHz. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power Down Assertion of Waveforms - Buffered Mode 25ns 0ns 50ns PD# CPUT 100MHz CPUC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCI 33MHz USB 48MHz REF 14.318MHz PD# Functionality CPU_STOP# CPUT CPUC 3V66 66MHz_OUT PCICLK_F PCICLK PCICLK USB/DOT 48MHz 1 Normal Normal 66MHz 66MHz_IN 66MHz_IN 66MHz_IN 48MHz 0 iref * Mult Float Low Low Low Low Low 0601E—12/22/04 15 ICS932S203 c N SYMBOL L E1 INDEX AREA E 1 2 α h x 45° D In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 2.413 2.794 .095 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e h 0.381 L 0.508 1.016 SEE VARIATIONS N α A A1 0.635 0° .005 .010 SEE VARIATIONS 0.025 BASIC .015 N SEATING PLANE b 8° 0° MIN MAX MIN 56 MAX 18.288 18.542 .720 .730 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B D mm. .10 (.004) C 8° D (inch) 300 mil SSOP Ordering Information ICS932S203yFLFT Example: ICS XXXX y F Lx T Designation for tape and reel packaging Lead Option (optional) LF = Lead Free LN = Lead Free Annealed Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) 0601E—12/22/04 .025 .020 .040 SEE VARIATIONS VARIATIONS -C- e 0.635 BASIC .110 Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 16 ICS932S203 c N SYMBOL L E1 INDEX AREA E 1 2 a D In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A - 1.20 - .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c D 0.09 0.20 SEE VARIATIONS .0035 .008 SEE VARIATIONS E 8.10 BASIC 0.319 E1 6.00 e L A A2 N A1 -Ce SEATING PLANE b 6.20 .236 0.50 BASIC 0.45 0.75 SEE VARIATIONS .018 .30 SEE VARIATIONS α 0° 8° 0° 8° aaa - 0.10 - .004 MIN MAX MIN 13.90 14.10 VARIATIONS aaa C N 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) 56 D mm. D (inch) .547 .555 7/6/00 Rev B ICS932S203yGLFT Example: ICS XXXX y G Lx T Designation for tape and reel packaging Lead Option (optional) LF = Lead Free LN = Lead Free Annealed Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 17 MAX MO-153 JEDEC Doc.# 10-0039 Ordering Information 0601E—12/22/04 .244 0.020 BASIC