ICS93722 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLK_INT N/C VDDA GND VDD CLKT2 CLKC2 Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz): <75ps • CYCLE - CYCLE jitter (66MHz):<110ps • CYCLE - CYCLE jitter (>100MHz):<65ps • OUTPUT - OUTPUT skew: <100ps • Output Rise and Fall Time: 650ps - 950ps • DUTY CYCLE: 49.5% - 50.5% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FB_OUTT Logic CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 FB_INT PLL CLK_INT CLKT4 CLKC4 CLKT5 CLKC5 0539E—07/18/03 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA N/C FB_INT FB_OUTT N/C CLKT3 CLKC3 GND Functionality INPUTS SCLK SDATA 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-Pin SSOP Block Diagram Control ICS93722 Pin Configuration OUTPUTS CLKT CLKC FB_OUTT PLL State AVDD CLK_INT 2.5V (nom) L L H L on 2.5V (nom) H H L H on 2.5V (nom) <20MHz Z Z Z off ICS93722 Pin Descriptions PIN NUMBER 6, 11, 15, 28 PIN NAME DESCRIPTION PWR Ground 27, 25, 16, 14, 5, 1 CLKC(5:0) OUT "Complementar y" clocks of differential pair outputs. 26, 24, 17, 13, 4, 2 CLKT(5:0) OUT "Tr ue" Clock of differential pair outputs. PWR Power supply 2.5V 3, 12, 23 GND TYPE VDD 7 SCLK IN Clock input of I2C input, 5V tolerant input 8 CLK_INT IN "True" reference clock input 9, 18, 21 N/C - Not connected 10 VDDA PWR Analog power supply, 2.5V 19 FB_OUTT OUT "True" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. 20 FB_INT IN "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. 22 SDATA IN Data input for I2C serial input, 5V tolerant input Bytes 0 to 4 are reserved power up default = 1. Byte 6: Output Control (1= enable, 0 = disable) Byte 5: Output Control (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 2, 1 4, 5 13, 14 17, 16 - PWD 1 1 1 1 1 1 1 1 DESCRIPTION CLK0 (T&C) Reserved Reserved Reserved CLK2 (T&C) CLK3 (T&C) Reserved Reserved BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Note: PWD = Power Up Default 0539E—07/18/03 2 PIN# 24, 25 26, 27 - PWD 1 1 1 1 DESCRIPTION Reser ved Reser ved Reser ved Reser ved 1 CLK4 (T&C) 1 Reser ved 1 CLK5 (T&C) 1 Reser ved ICS93722 Absolute Maximum Ratings Supply Voltage (VDD & AVDD) . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND –0.5 V to VDD +0.5 V 0°C to +85°C 115°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input / Supply / Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL Input High Current IIH VIN = VDD or GND µA Input Low Current IIL VIN = VDD or GND µA Operating Supply Current CONDITIONS IDD2.5 CL = 0 pF at 133 MHz IDDPD CL = 0 pF Output High Current IOH VDD = 2.3V, VOUT = 1V Output High Current IOL VDD = 2.3V, VOUT = 1.2V High Impedance Output Current IOZ VDD = 2.7V, VOUT = VDD or GND Input Clamp Voltage VIK IIN = -18 mA; High-level Output Voltage VOH Low-level Output Voltage 1 VOL CIN Input Capacitance 1 Output Capacitance COUT MIN TYP 275 -43 26 MAX UNITS 325 mA 100 µA -18 mA 43 mA 10 µA V VDD = min to max, IOH = -1mA 2.1 2.42 V VDD = 2.3V, IOH = -12mA 1.87 V VDD = min to max, IOH = 1mA 0.04 0.1 V VDD = 2.3V, IOH = 12mA 0.35 0.6 V VIN = VDD or GND VOUT = VDD or GND 1. Guaranteed by design, not 100% tested in production. 0539E—07/18/03 3 pF 3 pF ICS93722 Recommended Operating Conditions TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL Analog / Core Supply Voltage VDD, AVDD CONDITIONS MIN TYP MAX UNITS 2.3 2.5 2.7 V VDD/2 - 0.5V V VIL Input Voltage Level VIH VDD/2 + 0.5V Inpu Duty Cycle IDC 40 Input max jitter ITCYC V 60 500 ps Timing Requirements TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL freqop 1 Operating Clock Frequency Input Clock Duty Cycle Clock Stabilization 1 CONDITIONS dtin 1 tSTAB MIN MAX UNITS 66 TYP 200 MHz 40 60 % 100 µs from VDD = 2.5V to 1% target frequency 1. Guaranteed by design, not 100% tested in production. Switching Characteristics TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL Absolute Jitter1 Tjabs Cycle to cycle Jitter1,2 Tcyc-cyc Phase Error 1 1 Output to output Skew Pulse Skew 1 MIN TYP 120 100 - 200 MHz 75 66 MHz 50 110 100 - 200 MHz 25 65 t(phase error) CLK_INT to FB_INT Tskew VT = 50% 1 DC tR, tF MAX 66 MHz -150 150 ps ps 100 ps 49.5 50 50.5 49 50 51 450 550 950 Load = 120Ω / 12 pF 1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting output. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases. 4 ps 100 VT = 50%, 66 MHz to 100 MHz 0539E—07/18/03 ps 50 VT = 50%, 101 MHz to 167 MHz Single-ended 20 - 80 % UNITS 70 Tskewp Duty Cycle (differential)1,3 Rise Time, Fall Time CONDITIONS % ps ICS93722 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit How to Write: Controlle r (Host) Start Bit Address D4 (H ) Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Read: ICS (Sla ve /Re ce ive r) Controlle r (Host) Start Bit Address D5(H ) A CK ICS (Sla ve /Re ce ive r) A CK Byte Count Dummy Command Code A CK ACK A CK ACK A CK ACK A CK ACK A CK ACK A CK ACK A CK ACK A CK ACK Stop Bit Dummy Byte Count Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 A CK Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0539E—07/18/03 5 ICS93722 c N SYMBOL L E1 INDEX AREA E 1 2 α D A - 2.00 - A1 0.05 - .002 - A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c D 0.09 0.25 SEE VARIATIONS E 7.40 E1 5.00 5.60 0.65 BASIC .197 .220 0.0256 BASIC 0.55 0.95 SEE VARIATIONS .022 .037 SEE VARIATIONS e L A A2 In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX N α A1 8.20 0° .079 .0035 .010 SEE VARIATIONS .291 .323 8° 0° 8° MIN MAX MIN 9.90 10.50 .390 .413 MO-150 JEDEC Doc.# 10-0033 6/1/00 Rev B -Ce b VARIATIONS SEATING PLANE N .10 (.004) C 28 D mm. 209 mil SSOP D (inch) Ordering Information ICS93722yFLFT Example: ICS XXXX y F LF T Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0539E—07/18/03 6 MAX