IN74HC4046A PHASE-LOCKED LOOP High-Performance Silicon-Gate CMOS • • • • • • • The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC4046A phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain opamp DEMOUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1OUT and maintains 90 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 50% duty cycle). Phase comparator 2 (with leading-edge sensing logic) provides digital error signals PC2OUT and PCPOUT and maintains a 0 degree phase shift between SIGIN and COMPIN signals (duty cycle is immaterial). The linear VCO produces an output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEMOUT with an external resistor is used where the VCOIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control. Low Power Consumption Characteristic of CMOS Device Operating Speeds Similary to LS/ALSTTL Wide Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 µA Maximum (except SIGIN and COMPIN) Low Quiescent Current: 80 µA Maximum (VCO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Pin No. Symbol Name and Function 1 PCPOUT Phase Comparator Pulse Output 2 PC1OUT Phase Comparator 1 Output 3 COMPIN Comparator Input 4 VCOOUT VCO Output 5 INH Inhibit Input 6 C1A Capacitor C1 Connection A 7 C1B Capacitor C1 Connection B 8 GND Ground (0 V) VSS 9 VCOIN VCO Input 10 DEMOUT Demodulator Output 11 R1 Resistor R1 Connection 12 R2 Resistor R2 Connection 13 PC2OUT Phase Comparator 2 Output 14 SIGIN Signal Input 15 PC3OUT Phase Comparator 3 Output 16 VCC Positive Supply Voltage 1 tector ORDERING INFORMATION IN74HC4046AN Plastic IN74HC4046AD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT 2. For instance, a signal??2 ti IN74HC4046A MAXIMUM RATINGS* Symbol Parameter Value VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 IIN DC Input Current, per Pin ±20 IOUT DC Output Current, per Pin ±25 ICC DC Supply Current, VCC and GND Pins ±50 PD Power Dissipation in Still Air, Plastic DIP+ 750 SOIC Package+ 500 Tstg Storage Temperature -65 to +150 TL Lead Temperature, 1 mm from Case for 10 260 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VCO only VCC DC Supply Voltage (Referenced to GND) NON-VCO VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 VCC =4.5 VCC =6.0 V V V Min 3.0 2.0 0 -55 0 0 0 Unit V V V mA mA mA mW °C °C Max 6.0 6.0 VCC +125 1000 500 400 Unit V V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HC4046A [Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C ≤85 ≤125 to °C °C -55°C VIH Minimum HighVOUT= 0.1 V or VCC-0.1 V 2.0 1.5 1.5 1.5 Level Input Voltage IOUT≤ 20 µA 4.5 3.15 3.1 3.15 DC Coupled 6.0 4.2 5 4.2 SIGIN , COMPIN 4.2 VIL Maximum Low VOUT=0.1 V or VCC-0.1 V 2.0 0.5 0.5 0.5 Level Input Voltage IOUT ≤ 20 µA 4.5 1.35 1.3 1.35 DC Coupled 6.0 1.8 5 1.8 SIGIN , COMPIN 1.8 VOH Minimum HighVIN=VIH or VIL 2.0 1.9 1.9 1.9 Level Output 4.5 4.4 4.4 4.4 IOUT ≤ 20 µA Voltage PCPOUT, 6.0 5.9 5.9 5.9 PCnOUT VIN= VIH or VIL 4.5 3.98 3.8 3.7 IOUT ≤ 4.0 mA 6.0 5.48 4 5.2 IOUT ≤ 5.2 mA 5.3 4 VOL Maximum LowVIN=VIH or VIL 2.0 0.1 0.1 0.1 Level Output 4.5 0.1 0.1 0.1 IOUT ≤ 20 µA Voltage Qa-Qh 6.0 0.1 0.1 0.1 PCPOUT, PCnOUT VIN= VIH or VIL 4.5 0.26 0.3 0.4 IOUT ≤ 4.0 mA 6.0 0.26 3 0.4 IOUT ≤ 5.2 mA 0.3 3 IIN Maximum Input 2.0 VIN=VCC or GND ±5.0 ±4. ±3.0 Leakage Current 3.0 0 ±11. ±7.0 SIGIN , COMPIN 4.5 0 ±9. ±18.0 6.0 0 ±27. ±30.0 0 ±23 .0 ±45. 0 ±38 .0 IOZ Maximum ThreeOutput in High6.0 ±0.5 ±5. ±10 State Leakage Impedance State 0 Current PC2OUT VIN= VIL or VIH VOUT=VCC or GND ICC Maximum VIN=VCC or GND 6.0 4.0 40 160 Quiescent Supply IOUT=0µA Current (per Package) (VCO disabled) Pins 3,5 and 14 at VCC Pin 9 at GND; Input Leacage at Pin 3 and 14 to be excluded 3 Unit V V V V µA µA µA IN74HC4046A [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to ≤85°C ≤125°C Unit -55°C tPLH, tPHL Maximum Propagation Delay, SIGIN/COMPIN 2.0 175 220 265 ns to PC1OUT (Figure 1) 4.5 35 44 53 6.0 30 37 45 tPLH, tPHL Maximum Propagation Delay, SIGIN/COMPIN 2.0 340 425 510 ns to PCPOUT (Figure 1) 4.5 68 85 102 6.0 58 72 87 tPLH, tPHL Maximum Propagation Delay , SIGIN/COMPIN 2.0 270 340 405 ns to PC3OUT (Figure 1) 4.5 54 68 81 6.0 46 58 69 tPLZ, tPHZ Maximum Propagation Delay , SIGIN/COMPIN 2.0 200 250 300 ns Output Disable Time to PC2OUT 4.5 40 50 60 (Figures 2 and 3) 6.0 34 43 51 tPZL, tPZH Maximum Propagation Delay , SIGIN/COMPIN 2.0 230 290 345 ns Output Enable Time to PC2OUT 4.5 46 58 69 (Figures 2 and 3) 6.0 39 49 59 tTLH, tTHL Maximum Output Transition Time (Figure 1) 2.0 75 95 110 ns 4.5 15 19 22 6.0 13 16 19 [VCO Section] DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbo Parameter Test Conditions V 25 °C to-55°C ≤85°C ≤125°C Unit l VIH Minimum High-Level VOUT= 0.1 V or 3.0 2.1 2.1 2.1 V Input Voltage INH VCC-0.1 V 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 IOUT≤ 20 µA VIL Maximum Low VOUT=0.1 V or 3.0 0.90 0.90 0.90 V Level Input Voltage VCC-0.1 V 4.5 1.35 1.35 1.35 INH 6.0 1.8 1.8 1.8 IOUT ≤ 20 µA VOH Minimum High-Level VIN=VIH or VIL 3.0 1.9 1.9 1.9 V Output Voltage 4.5 4.4 4.4 4.4 IOUT ≤ 20 µA VCOOUT 6.0 5.9 5.9 5.9 VIN= VIH or VIL 4.5 3.98 3.84 3.7 IOUT ≤ 4.0 mA 6.0 5.48 5.34 5.2 IOUT ≤ 5.2 mA VOL Maximum Low-Level VIN=VIH or VIL 3.0 0.1 0.1 0.1 V Output Voltage 4.5 0.1 0.1 0.1 IOUT ≤ 20 µA VCOOUT 6.0 0.1 0.1 0.1 VIN= VIH or VIL 4.5 0.26 0.33 0.4 IOUT ≤ 4.0 mA 6.0 0.26 0.33 0.4 IOUT ≤ 5.2 mA (continued) 4 IN74HC4046A [VCO Section] DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) - continued VCC Guaranteed Limit Symbo Parameter Test Conditions V Unit 25 °C to ≤85°C ≤125°C l -55°C IIN Maximum Input VIN =Vcc or GND 6.0 0.1 1.0 1.0 µA Leakage Current INH, VCOIN Min Max Min Max Min Max VVCOIN Operating Voltage INH= VIL 3.0 0.1 1.0 0.1 1.0 0.1 1.0 V Range at VCOIN 4.5 0.1 2.5 0.1 2.5 0.1 2.5 6.0 0.1 4.0 0.1 4.0 0.1 4.0 over the range specified for R1; For linearity see Fig.13A, Parallel value of R1 and R2 should be >2.7 kΩ R1 Resistor Range 3.0 3.0 300 3.0 300 3.0 300 kΩ 4.5 3.0 300 3.0 300 3.0 300 6.0 3.0 300 3.0 300 3.0 300 R2 3.0 3.0 300 3.0 300 3.0 300 4.5 3.0 300 3.0 300 3.0 300 6.0 3.0 300 3.0 300 3.0 300 C1 Capacitor Range 3.0 40 No pF 4.5 40 Li6.0 40 mit [VCO Section] AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbo Parameter V 25 °C to ≤85°C ≤125°C l -55°C Min Max Min Max Min Max Frequency Stability with Temperature 3.0 ∆f/T Changes (Figures 11A,B,C) 4.5 6.0 fo VCO Center Frequency 3.0 3 (Duty Factor = 50%) 4.5 11 (Figures 12A,B,C) 6.0 13 3.0 See Figures 13A,B ∆fVCO VCO Frequency Linearity 4.5 6.0 3.0 Typical 50% Duty Factor at VCO ∂VCO OUT 4.5 6.0 5 Unit %/K MHz % % IN74HC4046A [Demodulator Section] DC ELECTRICAL CHARACTERISTICS Symbo l RS VOFF RD Parameter Test Conditions Resistor Range At RS > 300 kΩ the Leakage Current can Influence VDEMOUT Offset Voltage VI = VVCOIN = VCOIN to VDEMOUT 1/2 VCC; Values taken over RS Range Dynamic Output VDEMOUT = Resistance at 1/2 VCC DEMOUT VCC V 3.0 4.5 6.0 Guaranteed Limit Unit 25 °C to ≤85°C ≤125°C -55°C Min Max Min Max Min Max 50 300 kΩ 50 300 50 300 3.0 4.5 6.0 See Figure 10 mV 3.0 4.5 6.0 Typical 25 Ω Ω Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit 6 IN74HC4046A (Pin4). The input to the VCO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the VCO input accessible without degrading the loop performance, the VCO input voltage is buffered through a unity gain Opamp, to Demod Output. This Op-amp can drive loads of 50K ohms or more and provides no loading effects to the VCO input voltage (see Figure 10). An inhibit input is provided to allow disabling of the VCO and all Op-amps (see Figure 5). This is useful if the internal VCO is not being used. A logic high on inhibit disables the VCO and all Op-amps, minimizing standby power consumption. The output of the VCO is a standard high speed CMOS output with an equivalent LS-TTL fan out of 10. The VCO output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or feed external prescalers (counters) to enable frequency synthesis. DETAILED CIRCUIT DESCRIPTION Voltage Controlled Oscillator/Demodulator Output The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and Capacitor C1 are selected to determine the center frequency of the VCO (see typical performance curves Figure 12). R2 can be used to set the offset frequency with 0 volts at VCO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the VCO range is from 0 Hz. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/Hz) is decreased. Thus, for a narrow lock range, large swings on the VCO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure 5. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges up to Vref of the comparators, the oscillator logic flips the capacitor which causes the mirror to change the opposite side of the capacitor. The output from the internal logic is then taken to VCO output Figure 5. Logic Diagram for VCO Figure 6. The outputs of these comparators are essentially standard IN74HC outputs (comparator 2 is TRI-STATEABLE). In normal operation VCC and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be considered in the design. Phase Comparators All three phase comparators have two inputs, SIGIN and COMPIN. The SIGIN and COMPIN have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard IN74HC input levels are required. Both input structures are shown in 7 IN74HC4046A Figure 6. Logic Diagram for Phase Comparators VCO input must be VCC and the phase detector Phase Comparator 1 inputs must be 180 degrees out of phase. This comparator is a simple XOR gate The XOR is more susceptible to locking onto similar to the IN74HC86. Its operation is similar to harmonics of the SIGIN than the digital phase an overdriven balanced modulator. To maximize detector 2. For instance, a signal 2 times the VCO lock range the input frequencies must have a 50% frequency results in the same output duty cycle as duty cycle. Typical input and output waveforms a signal equal to the VCO frequency. The are shown in Figure 7. The output of the phase difference is that the output frequency of the 2f detector feeds the loop filter which averages the example is twice that of the other example. The output voltage. The frequency range upon which loop filter and VCO range should be designed to the PLL will lock onto if initially out of lock is prevent locking on to harmonics. defined as the capture range.The capture range for phase detector 1 is dependent on the loop Phase Comparator 2 filter design. The capture range can be as large This detector is a digital memory network. It as the lock range, which is equal to the VCO consists of four flip-flops and some gating logic, a frequency range. three state output and a phase pulse output as To see how the detector operates, refer to shown in Figure 6. This comparator acts only on Figure 7. When two square wave signals are the positive edges of the input signals and is applied to this comparator, an output waveform independent of duty cycle. (whose duty cycle is dependent on the phase Phase comparator 2 operates in such a difference between the two signals) results. As way as to force the PLL into lock with 0 phase the phase difference increases, the output duty difference between the VCO output and the signal cycle increases and the voltage after the loop filter input positive waveform edges. Figure 8 shows increases. In order to achieve lock when the PLL some typical loop waveforms. First assume that input frequency increases, the VCO input voltage SIGIN is leading the COMPIN. This means that the VCO’s frequency must be increased to bring its must increase and the phase difference between leding edge into proper phase alignment. Thus COMPIN and SIGIN will increase. At an input the phase detector 2 output is set high. This will frequency equal to fmin, the VCO input is at 0 V cause the loop filter to charge up the VCO input, increasing the VCO frequency. Once the leading edge of the COMPIN is detected, the output goes TRI-STATE holding the VCO input at the loop filter voltage. If the VCO still lags the SIGIN then the phase detector will again charge up the VCO input for the time between the leading edges of both waveforms. If the VCO leads the SIGIN then when the Figure 7. Typical Waveforms for PLL Using leading edge of the VCO is seen; the output of the Phase Comparator 1 phase comparator goes low. This discharges the This requires the phase detector output to loop filter until the leading edge of the SIGIN is be grounded; hence, the two input signals must detected at which time the output disables itself be in phase. When the input frequency is f , the max 8 IN74HC4046A again. This has the effect of slowing down the VCO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the VCO will be running either slower or faster than the SIGIN. If it is running slower the phase detector will see more SIGIN rising edges and so the output of the phase comparator will be high a majority of the time, raising the VCO’s frequency. Conversely, if the VCO is running faster than the SIGIN, the output of the detector will be low most of the time and the VCO’s output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is TRI-STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire VCO frequency range there is no phase difference between the COMPIN and the SIGIN. The lock range of the PLL is the same as the capture range. Minimal power was consumed in the loop filter since in lock the detector output is a high impedance. When no SIGIN is present, the detector will see only VCO leading edges, so the comparator output will stay low, forcing the VCO to fmin. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the SIGIN, the comparator treats it as another positive edge of the SIGIN and will cause the output to go high until the VCO leding edge is see, potentially for an entire SIGIN period. This would cause the VCO to speed up during that time. When using PC1, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset. Phase Comparator 3 This is positive edge-triggered sequential phase detector using an RS flip-flop as shown in Figure 6. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. It has some similar characteristics to the edge sensitive comparator. To see how this detector works, assume input pulses are applied to the SIGNIN and COMPIN’s as shown in Figure 9. When the SIGNIN leads the COMPIN, the flop is set. This will charge the loop filter and cause the VCO to speed up, bringing the comparator into phase with the SIGIN. The phase angle between SIGIN and COMPIN varies from 0° to 360° and is 180° at fo. The voltage swing for PC3 is greater than for PC2 but consequently has more ripple in the signal to the VCO .When no SIGIN is present the VCO will be forced to fmax as opposed to fmin when PC2 is used. The operating characteristics of all three phase comparators tors should be compared to the requirement of the system design and the appropriate one should be used. Figure 8. Typical Waveforms for PLL Using Phase Comparator 2 Figure 9. Typical Waveforms for PLL Using Phase Comparator 3 9 IN74HC4046A Figure 10. Offset Voltage at Demodulator Output as a Function of VCOIN and RS Figure 11A. Frequency Stability versus Ambient Temperature: VCC = 3.0 V Figure 11B. Frequency Stability versus Ambient Temperature: VCC = 4.5 V Figure 11C. Frequency Stability versus Ambient Temperature: VCC = 6.0 V Figure 12A. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) Figure 12B. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) 10 IN74HC4046A Figure 12C. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) Figure 12D. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) Figure 13A. Frequency Linearity versus R1,C1 and VCC Figure 13B. Definition of VCO Frequency Linearity) 11