UC1726 UC2726 UC3726 Isolated Drive Transmitter FEATURES DESCRIPTION • 750mA Output Drive, Source or Sink • 8 to 35V Operation • Transmits Drive Logic and Power through Low Cost Transformer • Programmable Operating Frequency The UC1726 Isolated Drive Transmitter, and its companion chip, the UC1727 Isolated High Side IGBT Driver, provide a unique solution to driving isolated power IGBTs. They are particularly suited to drive the high side devices on a high voltage H-bridge. The UC1726 device transmits the drive logic and drive power, along with transferring and receiving fault information with the isolated gate circuit using a low cost pulse transformer. • Up to 750kHz Operation • Improved Output Control Algorithm Minimizes Output Jitter • Fault Logic Monitors Isolated High Side IGBT Driver UC1727 for Faults • User Programmable Fault Timing Screens False Fault Signals • Shutdown Mode Disables On Chip Logic Reference for Low Standby Power • Optional External Biasing of Logic Circuitry can Reduce Overall Power Dissipation This drive system utilizes a duty cycle modulation technique that gives instantaneous response to the drive control transitions, and reliably passes steady state, or DC conditions. High frequency operation, up to 750kHz, allows the cost and size of the coupling transformer to be minimized. The UC1726 can be powered from a single VCC supply which internally generates a voltage reference for the logic circuitry. It can also be placed into a low power shutdown mode that disables the internal reference. The IC’s logic circuitry can be powered from an external supply, VL, to minimize overall power dissipation. Fault logic monitors the Isolated High Side IGBT Driver UC1727 for faults. Based on user defined timing, the UC1726 distinguishes valid faults, which it responds to by setting the fault latch pin. This also disables the gate drive information until the fault reset pin is toggled to a logic one. The UC1726 operates over an 8 to 35 volt supply range. The typical VCC voltage will be greater than 28 volts to be compatible with the UC1727. The undervoltage lockout circuitry of the Isolated High Side IGBT Driver UC1727 locks out the drive information during its undervoltage lockout. BLOCK DIAGRAM UDG-94004-1 7/95 UC1726 UC2726 UC3726 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Note 3) Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Source/Sink Current (Pulsed). . . . . . . . . . . . . . . . . . . . . . 1.5A Source/Sink Current (Continuous) . . . . . . . . . . . . . . . . . . 1.0A Output Voltage (pins 12, 14). . . . . . . . . . −0.3 to (VCC + 0.3)V CF, FRESET, FAULT, SHTDWN, FLATCH, VL, PHI, RT . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 6.0V CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 to 6.0V Operating Junction Temperature (Note 2) . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . . −65°C to 150°C Lead Temperature (Soldering, 10 seconds). . . . . . . . . 300°C Note 1: All voltages are with respect to GND (Pin 2); all currents are positive into, negative out of part. Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +9 to +35.0V Sink/Source Current (each output) . . . . . . . . . . . . . . . 0 to 750mA Timing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4k to 200kΩ Timing Capacitor (CT). . . . . . . . . . . . . . . . . . . . . . . 75pF to 2.0nF Timing Capacitor (CF). . . . . . . . . . . . . . . . . . . . . . . 75pF to 3.0nF Note 2: See Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations of packages. Note 3: Range over which the device is functional and parameter limits are guaranteed. CONNECTION DIAGRAMS DIL-16 (Top View) N Package DIL-16 (Top View) SP Package SOIC-28 (Top View) DWP Package DIL-18 (Top View) J Package PLCC-28 (Top View) QP Package PACKAGE PIN FUNCTION FUNCTION PIN GND CT N/C RT SHTDWN VL VCC N/C PVCC OUTB PGND GND OUTA PHI FLATCH FRESET FAULT N/C CF N/C N/C 2 1 2 3-4 5 6 7 8 9 10 11 12-18 19 20 21 22 23 24 25 26 27 28 UC1726 UC2726 UC3726 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 20V, RT = 4.32kΩ, CT = 330pF and CF = 2.2nF, no load on any output, and −55°C < TA < 125°C for the UC1726, −40°C < TA < 85°C for the UC2726, and 0°C < TA < 70°C for the UC3726, TA = TJ. PARAMETERS TEST CONDITIONS MIN TYP MAX UNITS 1.400 1.000 1.600 1.800 2.200 Retriggerable one shot Initial Accuracy µsec µsec Temperature Stability TJ = 25°C Over operating TJ Voltage Stability VCC = 10 to 35V 0.2 %/V Operating Frequency LLOAD = 1.5mH 170 kHz PHI Input (Control Input) HIGH Input Voltage 2.0 V LOW Input Voltage 0.8 HIGH Input Current 10 LOW Input Current Delay to one shot -300 100 Delay to Output CT = 1.4V 250 ISINK = 20mA 0.3 V µA −600 250 µA nsec nsec Output Drivers Output Low Level 0.5 V ISINK = 400mA 0.5 2.6 V Output High Level ISOURCE = −20mA 2.0 2.6 V (volts below VCC) ISOURCE = −400mA 2.0 2.9 V No load 30 60 nsec 4.40 4.60 V 13.0 20.0 mA Rise and Fall Times Logic Voltage Reference VL - Logic Voltage Internal Voltage Logic Supply Current VL = 4.75V to 5.25V, CT = 1.4V 4.20 Shut Down Circuit Logic Voltage - Off 0.5 V High Input Current VIH = 2.4 -100 µA Low Input Current VIL = 0.4 -20 µA Fault Logic Fault Reset High Input Current VIH = 2.4 ±5 µA Fault Reset Low Input Current VIL = 0.4 µA Fault High Input Current VIH = 2.4 -10 ±5 µA Fault Low Input Current VIL = 0.4 -60 µA Fault Pulse Width CF = 330pF 3.0 CF = 2.2nF 17.0 Fault Latch, VOH ILOAD = −1mA, Volts below VL 1.3 1.8 V Fault Latch, VOL ILOAD = 1mA ILOAD = 0, Volts below VL 0.25 0.3 0.5 Fault Latch, VOH V V Fault Latch, VOL ILOAD = 0 Fault Reset Pulse Width µs µs 0.2 V 500 ns 7.1 V UVLO Turn On Threshold Total Supply Current Supply Current CT = 1.4V 22 40 mA CT = 1.4V, VL = 5.0V 12 2.5 20 mA mA CT = 1.4V, Shutdown = 5.0V 3 UC1726 UC2726 UC3726 Refer to Typical Application on Page 5 and Application Note U-143A "New Chip Pair Provides Isolated Drive for High Voltage IGBTs" PIN DESCRIPTIONS OUTB: One output of the two totem pole outputs connected across the transformer primary winding. When PHI is high, the output toggles between VCC - 2V during the one shot charge time and approximately 0.6VCC during the remainder of the period. When PHI is low the output toggles between 0.3V during the one shot charge time and approximately VCC + 0.4V during the remainder of the period. CF: The timing input to the fault logic. A capacitor is placed across the input of CF and ground. The timing window is approximately t = 2.1CFRT. CT: The connection to the timing capacitor that controls the operating frequency. A capacitor to ground is repetitively charged during the one shot pulse width. It is discharged when a comparator senses zero current in the primary side of the transformer. The one shot pulse width is consequently determined by the time it takes to charge the capacitor from a threshold voltage of VL/4 to VL/2. This pin must be tied to a capacitor. See Recommended Operating Conditions. PGND: This is the ground for the output transistors bonded in the 28 pin packages. On the sixteen pin packages it is bonded separately to the GND pin. PHI: A logic control input to the isolated gate drive that changes the outputs as described above. This changes the duty cycle of the voltage wave form applied across the transformer. The Isolated High Side IGBT Driver UC1727 senses the different duty cycles as different drive commands. FAULT: This input to the fault logic initiates the user programmable timer. This time interval, specified by the capacitor on CF, determines the validity of the fault. The pin is tied to a low cost optocoupler, and is high until the UC1727 sends drive information from the PHI pin through the transformer while the FAULT pin stays low. Once this pin goes high, it must stay high during the entire fault window to be accepted as a valid fault. A valid fault sets the FLATCH pin high and prevents the transmitting of gate drive information until the FRESET is toggled high. If fault logic is not used, the FAULT pin must be grounded. PVCC: This is the input voltage for the output transistors on the 28 pin package. On the sixteen pin packages it is bonded separately to the VCC pin. RT: The input that sets the CT and CF capacitor currents with a resistor to ground. The voltage on RT is approximately 0.3VL. The resulting charge currents are: ICT = ICF = VL / 4RT. FLATCH: A valid fault sets this pin to a logic one and prevents the transmitting of gate drive information. The FLATCH pin can only be reset by connecting the FRESET to a logic 0. SHTDWN: This input shuts down the internal reference. A TTL logic one puts the UC1726 into a low standby current mode. This input has a pull down resistor on the chip to guarantee proper operation when left open. If an external logic voltage is applied to VL, this shutdown feature cannot be used without bringing the external voltage source to zero volts. FRESET: The input to the fault logic that resets the fault logic latch (FLATCH) and enables drive transmit data. This input must be low when powered up and stay low until after the fault latch has been set. GND: The signal and power ground for the device. The power ground of the output transistor is isolated on the chip from the substrate ground which biases the remainder of the device. VCC: The input voltage that biases the outputs and the internal reference. It can vary between 8V to 35V. This supply pin will typically be greater than 28V to be compatible with the UC1727. In order to minimize power dissipation use an external logic supply, VCC approximately 15V, and a step up transformer (N = 2). OUTA: One output of the two totem pole outputs connected across the transformer primary winding. When PHI is high, the output toggles between 0.3V during the one shot charge time and approximately VCC + 0.4V during the remainder of the period. When PHI is low the output toggles between VCC - 2V during the one shot charge time and approximately 0.6VCC during the remainder of the period. VL: The logic supply pin that biases all circuits except for the totem pole outputs. A bypass capacitor is recommended on this pin when left unconnected. The internal reference is approximately 4.4V. A 5.0V supply can be applied to this pin to assure minimum power dissipation. When an external supply higher than the VL voltage is applied to this pin, the internal reference turns off. 4 UC1726 UC2726 UC3726 OPERATING FREQUENCY: TPW = 1.1RT(CT + 50pF) The chip operating frequency is determined by the values of components connected to the RT and CT pins. A resistor connected between RT and ground sets the charge current to ICT = VL / 4RT. The operating frequency varies slightly depending on the VCC and VL voltages. The following equations approximate the one shot pulse width at operating frequency when VCC = 20V. FO = 1 3.3RT(CT + 50pF) The 50pF additional capacity represents internal chip capacitance at the CT input. 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