INTEL DD28F032SA-150

E
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DD28F032SA
32-MBIT (2 MBIT X 16, 4 MBIT X 8)
FlashFile™ MEMORY
User-Selectable 3.3V or 5V V CC
n
User-Configurable x8 or x16 Operation
70 ns Maximum Access Time
28.6 MB/sec Burst Write Transfer Rate
1 Million Typical Erase Cycles per Block
56-Lead, 1.2 x 14 x 20 mm Advanced
Dual Die TSOP Package Technology
64 Independently Lockable Blocks
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Revolutionary Architecture
 100% Backwards-Compatible with
Intel 28F016SA
 Pipelined Command Execution
 Program during Erase
2 mA Typical I CC in Static Mode
2 µA Typical Deep Power-Down
State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s DD28F032SA 32-Mbit FlashFile™ memory is a revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and communication products. With innovative
capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal
choice for designing embedded mass storage flash memory systems.
The DD28F032SA is the result of highly-advanced packaging innovation which encapsulates two 28F016SA
die in a single Dual Die Thin Small Outline Package (DDTSOP).
The DD28F032SA is the highest density, highest performance nonvolatile read/program solution for solidstate storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F016SA
16-Mbit FlashFile memory), very high-cycling, low-power 3.3V operation, very fast program and read
performance and selective block locking provide a highly flexible memory component suitable for high-density
memory cards, Resident Flash Arrays and PCMCIA-ATA Flash Drives. The DD28F032SA’s dual read voltage
enables the design of memory cards which can be read/written in 3.3V and 5.0V systems interchangeably. Its
x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in a Resident Flash Array or memory card. The
DD28F032SA will be manufactured on Intel’s 0.6 µm ETOX IV technology.
December 1996
Order Number: 290490-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
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DD28F032SA
CONTENTS
PAGE
1.0 PRODUCT OVERVIEW................................... 5
2.0 DEVICE PINOUT............................................. 6
2.1 Lead Descriptions ........................................ 8
3.0 MODES OF OPERATION ............................. 10
4.0 MEMORY MAPS ........................................... 11
4.1 Extended Status Registers Memory Map ... 12
5.0 BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS................ 13
5.1 Bus Operations for Word-Wide Mode
(BYTE# = VIH).............................................. 13
5.2 Bus Operations for Byte-Wide Mode
(BYTE# = VIL) .............................................. 13
5.3 28F008SA Compatible Mode Command
Bus Definitions ............................................. 14
5.4 28F016SA-Performance Enhancement
Command Bus Definitions............................ 15
5.5 Compatible Status Register ....................... 16
5.6 Global Status Register ............................... 17
5.7 Block Status Register ................................ 18
PAGE
6.0 ELECTRICAL SPECIFICATIONS..................19
6.1 Absolute Maximum Ratings........................19
6.2 Capacitance ...............................................20
6.3 Timing Nomenclature .................................21
6.4 DC Characteristics (VCC = 3.3V ± 0.3V) .....24
6.5 DC Characteristics (VCC = 5.0V ± 0.5V) ....26
6.6 AC Characteristics—Read Only
Operations ...................................................28
6.7 Power-Up and Reset Timings.....................32
6.8 AC Characteristics for WE#—Controlled
Command Write Operations .........................33
6.9 AC Characteristics for CE X#—Controlled
Write Operations ..........................................37
6.10 AC Characteristics for Page Buffer Write
Operations ...................................................41
6.11 Erase and Word/Byte Program
Performance, Cycling Performance and
Suspend Latency .........................................44
7.0 DERATING CURVES ....................................45
8.0 MECHANICAL SPECIFICATIONS ................47
APPENDIX A: Device Nomenclature/
Ordering Information .....................................48
APPENDIX B: Additional Information...............49
3
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DD28F032SA
REVISION HISTORY
Number
—Original Version
—Never Published
—Full Datasheet with Specifications
—CE0#, CE1# control 28F016SA No. 1
—CE0#, CE2# control 28F016SA No. 2
-004
—DC Characteristics (3.3V VCC): ICCR1 (TTL): BYTE# = V IL or VIH
—Full Chip Erase Time (3.3V VCC) = 51.2 sec typ
—Full Chip Erase Time (5.0V VCC) = 38.4 sec typ
—Section 6.7: Added specifications t PHEL3, tPHEL5
—TSOP dimension A1 = 0.05 mm (min)
—Revised Product Status to Preliminary
—tWHGL (3.3V) = 120 ns
—Minor cosmetic changes
—Updated AC/DC parameters
-005
4
Description
-001
-002
-003
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1.0 PRODUCT OVERVIEW
The DD28F032SA is a high-performance 32-Mbit
(33,554,432-bit) block erasable nonvolatile random
access memory organized as either 2 Mword x 16,
or 4 Mbyte x 8. The DD28F032SA is built using
two 28F016SA chips encapsulated in a single
56- lead TSOP Type I package. The DD28F032SA
includes sixty-four 64-KB (65,536) blocks or sixtyfour 32-KW (32,768) blocks.
The DD28F032SA architecture allows operations
to be performed on a single, 16-Mbit chip at a
time.
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and results in greater
product reliability and ease of use.
Among the significant enhancements on the
DD28F032SA:
• 3.3V Low Power Capability
• Improved Program Performance
• Dedicated Block Program/Erase Protection
A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/program
operation.
The DD28F032SA will be available in a 56-lead,
1.2 mm thick, 14 mm x 20 mm Dual Die TSOP
Type I package. This form factor and pinout allow
for very high board layout densities. The
DD28F032SA is pinout and footprint compatible
with the 28F016SA.
Two Command User Interfaces (CUI) serve as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal algorithm automation allows word/byte
programs and block erase operations to be
executed using a two-write command sequence to
the CUI in the same way as the 28F016SA
16-Mbit FlashFile memory.
A super-set of commands has been added to the
basic 28F008SA (8-Mbit FlashFile memory)
command-set to achieve higher program
performance and provide additional capabilities.
DD28F032SA
These new commands and features include:
• Page Buffer Writes to Flash
• Command Queueing Capability
• Automatic Data Programs during Erase
• Software Locking of Memory Blocks
• Two-Byte
Systems
Successive
Programs
in
8-bit
• Erase All Unlocked Blocks
These operations can only be performed on one
16-Mbit device at a time. If the WSM is busy
performing an operation, the system should not
attempt to select the other device.
Writing of memory data is performed in either byte
or word increments typically within 6 µs, a 33%
improvement over the 28F008SA. A block erase
operation erases one of the 64 blocks in typically
0.6 sec, independent of the other blocks, which is
a 65% improvement over the 28F008SA.
Each block can be written and erased a minimum
of 100,000 cycles. Systems can achieve typically
1 million block erase cycles by providing wearleveling algorithms and graceful block retirement.
These techniques have already been employed in
many flash file systems. Additionally, wear leveling
of block erase cycles can be used to minimize the
program/erase performance differences across
blocks.
The DD28F032SA incorporates two Page Buffers
of 256 bytes (128 words) on each 28F016SA to
allow page data programs. This feature can
improve a system program performance by up to
4.8 times over previous flash memory devices.
All operations are started by a sequence of
command writes to the device. Three Status
Registers (described in detail later) and a RY/BY#
output pin provide information on the progress of
the requested operation.
The DD28F032SA allows queueing of the next
operation while the memory executes the current
operation. This eliminates system overhead when
writing several bytes in a row to the array or
erasing several blocks at the same time. The
DD28F032SA can also perform program
operations to one block of memory while
performing erase of another block. However,
simultaneous program and/or erase operations are
not allowed on both 28F016SA devices. See
Modes of Operation, Section 3.0.
5
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DD28F032SA
The DD28F032SA provides user-selectable block
locking to protect code or data such as device
drivers, PCMCIA card information, ROMexecutable O/S or application code. Each block
has an associated nonvolatile lock-bit which
determines the lock status of the block. In
addition, the DD28F032SA has a master Write
Protect pin (WP#) which prevents any
modifications to memory blocks whose lock-bits
are set.
The DD28F032SA contains three types of Status
Registers to accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory’s Status Register. This register, when
used alone, provides a straightforward upgrade
capability to the DD28F032SA from a
28F008SA-based design.
• A Global Status Register (GSR) which informs
the system of Command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
• 64 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
The GSR and BSR memory maps for byte-wide
and word-wide modes are shown in Figures 4
and 5.
The DD28F032SA incorporates an open drain
RY/BY# output pin. This feature allows the user to
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array. Other configurations of the RY/BY# pin are
enabled via special CUI commands and are
described in detail in the 16-Mbit Flash Product
Family User’s Manual.
The DD28F032SA also incorporates three chipenable input pins, CE0#, CE1# and CE2#. The
active low combination of CE0# and CE1# controls
the first 28F016SA. The active low combination of
CE0# and CE2# controls the second 28F016SA.
6
The BYTE# pin allows either x8 or x16
read/programs to the DD28F032SA. BYTE# at
logic low selects 8-bit mode with address A0
selecting between low byte and high byte. On the
other hand, BYTE# at logic high enables 16-bit
operation with address A1 becoming the lowest
order address and address A0 is not used (don’t
care). A device block diagram is shown in Figure
1.
The DD28F032SA is specified for a maximum
access time of 70 ns (tACC) at 5.0V operation
(4.75V to 5.25V) over the commercial temperature
range (0°C to +70°C). A corresponding maximum
access time of 150 ns at 3.3V (3.0V to 3.6V and
0°C to +70°C) is achieved for reduced power
consumption applications.
The DD28F032SA incorporates an Automatic
Power Saving (APS) feature which substantially
reduces the active current when the device is in
static mode of operation (addresses not
switching).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA)
pin is driven low. This mode provides additional
write protection by acting as a device reset pin
during power transitions. In the deep power-down
state, the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.
A CMOS standby mode of operation is enabled
when either CE0#, or both CE1# and CE2#,
transition high and RP# stays high with all input
control pins at CMOS levels.
2.0 DEVICE PINOUT
The DD28F032SA Standard 56-Lead Dual Die
TSOP Type I pinout configuration is shown in
Figure 2.
E
DD28F032SA
DQ
DQ
8-15
Output
Buffer
0-7
Output
Buffer
Input
Buffer
Input
Buffer
3/5#
I/O Logic
BYTE#
Data
Queue
Registers
Output Multiplexer
ID
Register
CSR
Page
Buffers
CE0#
ESRs
CE1#
CUI
0-20
OE#
A
Data
Comparator
WE#
WP#
Input
Buffer
RP#
Y
Decoder
WSM
64-Kbyte
Block 31
64-Kbyte
Block 30
X
Decoder
64-Kbyte
Block 1
RY/BY#
64-Kbyte
Block 0
Address
Queue
Latches
Y Gating/Sensing
Program/Erase
Voltage Switch
VPP
3/5#
VCC
Address
Counter
GND
0490_01
Figure 1. Block Diagram of 16-Mbit Devices in DD28F032SA
Architectural Evolution Includes Page Buffers, Queue Registers and Extended Registers
7
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DD28F032SA
2.1 Lead Descriptions
Symbol
A0
A1–A15
A16–A20
DQ0–DQ7
DQ8–DQ15
CE0#
CEX# =
CE1# or
CE2#
RP#
OE#
WE#
RY/BY#
8
Type
INPUT
Name and Function
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A 0 input buffer is turned off when BYTE# is
high).
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A6-15 selects 1 of 1024 rows, and A 1-5 selects 16 of 512 columns. These
addresses are latched during data programs.
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks in each of
the two 28F016SAs. These addresses are latched during data programs,
block erase and lock block operations.
INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is deselected or the outputs are disabled.
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. CE0#/CE1# enable/disable the first
28F016SA (16 Mbit No. 1) while CE0#/CE2# enable/disable the second
28F016SA (16 Mbit No. 2). CE0# active low enables chip operation while
CE1# or CE2# select between the first and second device, respectively
CE1# and CE2# must not be active low simultaneously. Reference Table
3.0.
INPUT
RESET/POWER-DOWN: RP# low places the device in a deep powerdown state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
OPEN DRAIN READY/BUSY: Indicates status of the internal WSM. When low, it
OUTPUT
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE0#/CE1#/CE2# are high), except if a
RY/BY#
Pin Disable command is issued.
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DD28F032SA
2.1 Lead Descriptions (Continued)
Type
Name and Function
WP#
Symbol
INPUT
BYTE#
INPUT
3/5#
INPUT
VPP
SUPPLY
VCC
SUPPLY
GND
SUPPLY
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile
lock-bit for each block. When WP# is low, those locked blocks as
reflected by the Block-Lock Status bits (BSR.6), are protected from
inadvertent data programs or block erases. When WP# is high, all blocks
can be written or erased regardless of the state of the lock-bits. The WP#
input buffer is disabled when RP# transitions low (deep power-down
mode).
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then
input or output on DQ0-7, and DQ8-15 float. Address A 0 selects between
the high and low byte. BYTE# high places the device in x16 mode, and
turns off the A0 input buffer. Address A1 then becomes the lowest order
address.
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V
operation. 3/5# low configures internal circuits for 5.0V operation.
NOTES:
Reading the array with 3/5# high in a 5.0V system could damage the
device.
There is a significant delay from 3/5# switching to valid data.
ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks
or writing words/bytes/pages into the flash array.
DEVICE POWER SUPPLY (3.3V ± 0.3V, 5.0V ± 0.5V, 5.0V ± 0.25V):
Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
Lead may be driven or left floating.
NC
9
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DD28F032SA
28F016SV 28F016SA
3/5#
CE 1 #
NC
A 20
A 19
A 18
A 17
A 16
V CC
A 15
A 14
A 13
A 12
CE 0#
V PP
RP#
A 11
A 10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
3/5#
CE 1 #
NC
A 20
A 19
A 18
A 17
A 16
V CC
A 15
A 14
A 13
A 12
CE 0#
V PP
RP#
A 11
A 10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
28F016SA 28F016SV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3/5#
CE 1 #
CE 2 #
A 20
A 19
A 18
A 17
A 16
V CC
A 15
A 14
A 13
A 12
CE 0#
V PP
RP#
A 11
A 10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DD28F032SA
56-LEAD TSOP PINOUT
14mm x 20mm
TOP VIEW
WP#
WE#
OE#
RY/BY#
DQ15
DQ 7
DQ 14
DQ 6
GND
DQ 13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ 3
DQ 10
DQ 2
VCC
DQ 9
DQ 1
DQ 8
DQ 0
A0
BYTE#
NC
NC
WP#
WE#
OE#
RY/BY#
DQ15
DQ 7
DQ 14
DQ 6
GND
DQ 13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ 3
DQ 10
DQ 2
VCC
DQ 9
DQ 1
DQ 8
DQ 0
A0
BYTE#
NC
NC
WP#
WE#
OE#
RY/BY#
DQ15
DQ7
DQ14
DQ6
GND
DQ 13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ 3
DQ 10
DQ 2
VCC
DQ 9
DQ 1
DQ 8
DQ 0
A0
BYTE#
NC
NC
0490_02
Figure 2. Dual Die TSOP Pinout Configuration
3.0 MODES OF OPERATION
RP#
CE0#
CE1#
CE2#
28F016SA
No. 1
28F016SA
No. 2
DD28F032SA
Chip
0
X
X
X
DPD
DPD
DPD
1
1
X
X
Standby
Standby
Standby
1
0
0
1
Standby
Active
Active
1
0
1
0
Active
Standby
Active
1
0
1
1
Standby
Standby
Standby
1
0
0
0
NOTES:
X = Don’t Care
DPD = Deep Power-Down
28F016SA No. 1 = First 16-Mbit Device
28F016SA No. 2 = Second 16-Mbit Device
10
Illegal Condition
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DD28F032SA
4.0 MEMORY MAPS
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64-Kbyte Block
31
64-Kbyte Block
30
64-Kbyte Block
29
64-Kbyte Block
28
64-Kbyte Block
27
64-Kbyte Block
26
64-Kbyte Block
25
64-Kbyte Block
24
64-Kbyte Block
23
64-Kbyte Block
22
64-Kbyte Block
21
64-Kbyte Block
20
64-Kbyte Block
19
64-Kbyte Block
18
64-Kbyte Block
17
64-Kbyte Block
16
64-Kbyte Block
15
64-Kbyte Block
14
64-Kbyte Block
13
64-Kbyte Block
12
64-Kbyte Block
11
64-Kbyte Block
10
64-Kbyte Block
9
64-Kbyte Block
8
64-Kbyte Block
7
64-Kbyte Block
6
64-Kbyte Block
5
64-Kbyte Block
4
64-Kbyte Block
3
64-Kbyte Block
2
64-Kbyte Block
1
64-Kbyte Block
0
28F016SA No. 1
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64-Kbyte Block
63
64-Kbyte Block
62
64-Kbyte Block
61
64-Kbyte Block
60
64-Kbyte Block
59
64-Kbyte Block
58
64-Kbyte Block
57
64-Kbyte Block
56
64-Kbyte Block
55
64-Kbyte Block
54
64-Kbyte Block
53
64-Kbyte Block
52
64-Kbyte Block
51
64-Kbyte Block
50
64-Kbyte Block
49
64-Kbyte Block
48
64-Kbyte Block
47
64-Kbyte Block
46
64-Kbyte Block
45
64-Kbyte Block
44
64-Kbyte Block
43
64-Kbyte Block
42
64-Kbyte Block
41
64-Kbyte Block
40
64-Kbyte Block
39
64-Kbyte Block
38
64-Kbyte Block
37
64-Kbyte Block
36
64-Kbyte Block
35
64-Kbyte Block
34
64-Kbyte Block
33
64-Kbyte Block
32
28F016SA No. 2
0490_03
Figure 3. DD28F032SA Memory Map (Byte-Wide Mode)
11
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DD28F032SA
4.1 Extended Status Registers Memory Map for Either 28F016SA No. 1 or
28F016SA No. 2
x8 MODE
A[20-0]
RESERVED
GSR
1F0005H
1F0004H
RESERVED
1F0003H
BSR 31
RESERVED
RESERVED
.
.
.
x16 MODE
A[20-1]
1F0006H
1F0002H
1F0001H
1F0000H
F8003H
RESERVED
GSR
RESERVED
BSR 31
F8001H
RESERVED
RESERVED
.
.
.
010002H
08001H
000006H
RESERVED
000005H
GSR
000004H
RESERVED
RESERVED
000003H
000002H
000001H
RESERVED
000000H
0490_04
Figure 4. Extended Status Register Memory
Map (Byte-Wide Mode)
12
F8000H
RESERVED
RESERVED
BSR 0
F8002H
00003H
RESERVED
GSR
00002H
RESERVED
BSR 0
RESERVED
RESERVED
00001H
00000H
0490_05
Figure 5. Extended Status Register Memory
Map (Word-Wide Mode)
E
DD28F032SA
5.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
5.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)
Notes
RP#
CEX#(8)
CE0#
OE#
WE#
A1
DQ0–15
RY/BY#
Read
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
High Z
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High Z
X
1,3
VIL
X
X
X
X
X
High Z
VOH
Manufacturer ID
4
VIH
VIL
VIL
VIL
VIH
VIL
0089H
VOH
Device ID
4
VIH
VIL
VIL
VIL
VIH
VIH
66A0H
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
Mode
Deep Power-Down
Write
5.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Notes
RP#
CEX#(8)
CE0#
OE#
WE#
A0
DQ0–7
RY/BY#
Read
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
High Z
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High Z
X
1,3
VIL
X
X
X
X
X
High Z
VOH
Manufacturer ID
4
VIH
VIL
VIL
VIL
VIH
VIL
89H
VOH
Device ID
4
VIH
VIL
VIL
VIL
VIH
VIH
A0H
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
Mode
Deep Power-Down
Write
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.
2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down
mode, RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully
completed when VPP = VPPH.
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to
VOH when the WSM is not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations; for example, a Status Register read during a
data program operation.
8. CEX# = CE1# or CE2#.
13
E
DD28F032SA
5.3 28F008SA Compatible Mode Command Bus Definitions
First Bus Cycle
Command
Notes
Read Array
Second Bus Cycle
Oper
Addr
Data
Oper
Addr
Data
Write
X
xxFFH
Read
AA
AD
Intelligent Identifier
1
Write
X
xx90H
Read
IA
ID
Read Compatible Status Register
2
Write
X
xx70H
Read
X
CSRD
Clear Status Register
3
Write
X
xx50H
Word/Byte Program
Write
X
xx40H
Write
PA
PD
Alternate Word/Byte Program
Write
X
xx10H
Write
PA
PD
Block Erase/Confirm
Write
X
xx20H
Write
BA
xxD0H
Erase Suspend/Resume
Write
X
xxB0H
Write
X
xxD0H
ADDRESS
A = Array Address
BA = Block Address
IA = Identifier Address
PA = Program Address
X = Don’t Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
PD = Program Data
NOTES:
1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters data program, block erase, or suspend operations.
3. Clears CSR.3, CSR.4 and CSR.4. Also clears GSR.4 and all BSR.4 and BSR.2 bits.
4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.
See Status Register definitions.
14
E
DD28F032SA
5.4 28F016SA-Performance Enhancement Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Notes
Oper
Addr
Data(12)
Oper
Addr
Data(12)
Read Extended
Status Register
1
Write
X
xx71H
Read
RA
GSRD
BSRD
Page Buffer Swap
7
Write
X
xx72H
Read Page Buffer
Write
X
xx75H
Read
PBA
PD
Single Load to Page
Buffer
Write
X
xx74H
Write
PBA
PD
Command
Sequential Load to
Page Buffer
Mode
Third Bus Cycle
Oper
Addr
Data
x8
4,6,10
Write
X
xxE0H
Write
X
BCL
Write
X
BCH
x16
4,5,6,10
Write
X
xxE0H
Write
X
WCL
Write
X
WCH
x8
3,4,9,10
Write
X
xx0CH
Write
A0
BC(L,H)
Write
PA
BC(H,L)
x16
4,5,10
Write
X
xx0CH
Write
X
WCL
Write
PA
WCH
x8
3
Write
X
xxFBH
Write
A0
WD(L,H)
Write
PA
WD(H,L)
Write
X
xx77H
Write
BA
xxD0H
Write
X
xx97H
Write
X
xxD0H
Upload Device
Information
Write
X
xx99H
Write
X
xxD0H
Erase All Unlocked
Blocks/Confirm
Write
X
xxA7H
Write
X
xxD0H
Page Buffer Write to
Flash
Two-Byte Write
Lock Block/Confirm
Upload Status
Bits/Confirm
2
RY/BY# Enable to
Level-Mode
8
Write
X
xx96H
Write
X
xx01H
RY/BY# Pulse-OnWrite
8
Write
X
xx96H
Write
X
xx02H
RY/BY# Pulse-OnErase
8
Write
X
xx96H
Write
X
xx03H
RY/BY# Disable
8
Write
X
xx96H
Write
X
xx04H
Sleep
11
Write
X
xxF0H
Write
X
xx80H
Abort
ADDRESS
BA = Block Address
PBA = Page Buffer Address
RA = Extended Register Address
PA = Program Address
X = Don’t Care
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
DATA
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
15
E
DD28F032SA
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. A0 is automatically complemented to load the second byte of data. BYTE# must be at VIL.
The A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don’t care.
6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.
9. Program address, PA, is the destination address in the flash array which must match the source address in the Page
Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual.
10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.
11. To ensure that the DD28F032SA’s power consumption during sleep mode reads the deep power-down current level, the
system also needs to de-select the chip by taking either or both CE0# or CE1#/CE2# high.
12. The upper byte of the data bus (DQ8–15) during command programs is a “Don’t Care” in x16 operation of the device.
5.5 Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
NOTES:
RY/BY# output or WSMS bit must be checked to
determine completion of an operation (erase
suspend, block erase or data program) before
the appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
0 = Erase In Progress/Completed
CSR.5 = ERASE STATUS
1 = Error in Block Erasure
0 = Successful Block Erase
If DWS and ES are set to “1” during a block
erase attempt, an improper command sequence
was entered. Clear the CSR and attempt the
operation again.
CSR.4 = DATA WRITE STATUS
1 = Error in Data Program
0 = Data Program Successful
CSR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPPS bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The
WSM interrogates VPP’s level only after the Data
Program or Block Erase command sequences
have been entered, and informs the system if
VPP has not been switched on. VPPS is not
guaranteed to report accurate feedback between
VPPL and VPPH.
CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
16
E
DD28F032SA
5.6 Global Status Register
WSMS
OSS
DOS
DSS
QS
PBAS
PBS
PBSS
7
6
5
4
3
2
1
0
GSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
NOTES:
RY/BY# output or WSMS bit must be checked
to determine completion of an operation (block
lock, erase suspend, any RY/BY# reconfiguration, Upload Status Bits, block erase or data
program) before the appropriate Status bit (OSS
or DOS) is checked for success.
[1]
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
0 = Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS
1 = Operation Unsuccessful
0 = Operation Successful or Currently
Running
GSR.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
0 = Device Not in Sleep
MATRIX = 5/4
0 0 = Operation Successful or Currently
Running
0 1 = Device in Sleep Mode or Pending
Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or Aborted
If operation currently running, then GSR.7 = 0.
If device pending sleep, then GSR.7 = 0.
Operation aborted: unsuccessful due to Abort
command.
GSR.3 = QUEUE STATUS
1 = Queue Full
0 = Queue Available
GSR.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers Available
0 = No Page Buffer Available
GSR.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
0 = Selected Page Buffer Busy
Each 28F016SA device contains two Page
Buffers.
Selected Page Buffer is currently busy with WSM
operation
GSR.0 = PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
0 = Page Buffer 0 Selected
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7, or CSR.7, provides indication when all queued operations are completed.
17
E
DD28F032SA
5.7 Block Status Register
BS
BLS
BOS
BOAS
7
6
5
4
BSR.7 = BLOCK STATUS
1 = Ready
0 = Busy
QS
VPPS
R
R
3
2
1
0
NOTES:
[1] RY/BY# output or BS bit must be checked to
determine completion of an operation (block lock,
erase suspend, any RY/BY# reconfiguration,
Upload Status Bits, block erase or data program)
before the appropriate Status bits (BOS, BLS) is
checked for success.
BSR.6 = BLOCK LOCK STATUS
1 = Block Unlocked for Program/Erase
0 = Block Locked for Program/Erase
BSR.5 = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
0 = Operation Successful or
Currently Running
BSR.4 = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
0 = Operation Not Aborted
MATRIX 5/4
0 0 = Operation Successful or
Currently Running
0 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
The BOAS bit will not be set until BSR.7 = 1.
Operation halted via Abort command.
BSR.3 = QUEUE STATUS
1 = Queue Full
0 = Queue Available
BSR.2 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7, or CSR.7, provides indication when all queued operations are completed.
18
E
DD28F032SA
6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Temperature Under Bias ....................0°C to +80°C
Storage Temperature ...................–65°C to +125°C
NOTICE: This is a production datasheet. The specifications
are subject to change without notice. Verify with your local
Intel Sales office that you have the latest datasheet before
finalizing a design.
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.
VCC = 3.3V ± 0.3V Systems
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
Ambient
Temperature
TA
Operating Temperature, Commercial
1
0
70
°C
VCC
VCC with Respect to GND
2
–0.2
7.0
V
2,3
–0.2
14.0
V
–0.5
VCC
+ 0.5
V
VPP
VPP Supply Voltage with Respect to GND
V
Voltage on any Pin (except VCC,VPP) with
Respect to GND
2
I
Current into Any Non-Supply Pin
5
± 30
mA
IOUT
Output Short Circuit Current
4
100
mA
VCC = 5.0V ± 0.5V, V CC = 5.0V ± 0.25V Systems(6)
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
Ambient
Temperature
TA
Operating Temperature, Commercial
1
0
70
°C
VCC
VCC with Respect to GND
2
–0.2
7.0
V
VPP
VPP Supply Voltage with Respect to GND
2,3
–0.2
14.0
V
V
Voltage on Any Pin (except V CC,VPP) with
Respect to GND
2
–2.0
7.0
V
I
Current into Any Non-Supply Pin
5
± 30
mA
IOUT
Output Short Circuit Current
4
100
mA
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for
periods <20 ns.
3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. This specification also applies to pins marked “NC.”
6. 5% VCC specifications refer to the DD28F032SA-070 in its High Speed Test configuration.
19
E
DD28F032SA
6.2 Capacitance
For a 3.3V System:
Symbol
Parameter
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
12
16
pF
TA = +25°C,
f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
16
24
pF
TA = +25°C,
f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
1
50
pF
For VCC = 3.3V ± 0.3V
2.5
ns
50Ω Transmission Line
Delay
Test Conditions
Equivalent Load Timing Circuit
For a 5.0V System:
Symbol
Parameter
Notes
Typ
Max
Units
CIN
Capacitance Looking into an
Address/Control Pin
1
12
16
pF
TA = +25°C,
f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
16
24
pF
TA = +25°C,
f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
1
100
pF
For VCC = 5.0V ± 0.5V
30
pF
For VCC = 5.0V ±
0.25V
Equivalent Testing Load Circuit for
VCC ± 10%
2.5
ns
25Ω Transmission Line
Delay
Equivalent Testing Load Circuit for
VCC ± 5%
2.5
ns
83Ω Transmission Line
Delay
NOTE:
1. Sampled, not 100% tested.
20
E
DD28F032SA
6.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tELQV time(t) from CEX# (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)
tACC
tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tDH
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
Pin States
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CEX# (Chip Enable)
X
Driven, but not necessarily valid
F
BYTE# (Byte Enable)
Z
High Impedance
G
OE# (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY/BY# (Ready Busy)
V
Any Voltage Level
Y
3/5# Pin
5V
VCC at 4.5V Minimum
3V
VCC at 3.0V Minimum
21
E
DD28F032SA
2.4
2.0
INPUT
2.0
OUTPUT
TEST POINTS
0.8
0.45
0.8
0490_06
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 6. Transient Input/Output Reference Waveform (VCC = 5.0V) for Standard Test Configuration(1)
3.0
INPUT
1.5
TEST POINTS
1.5
OUTPUT
0.0
0490_07
AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 7. Transient Input/Output Reference Waveform (VCC = 3.3V)
and High Speed Reference Waveform (2) (VCC = 5.0V ± 5%)
NOTES:
1. Testing characteristics for DD28F032SA-080/DD28F032SA-100.
2. Testing characteristics for DD28F032SA-070/DD28F032SA-150.
22
E
DD28F032SA
2.5 ns of 25Ω Transmission Line
From Output
Test
under Test
Point
Total Capacitance = 100 pF
0490-08
Figure 8. Transient Equivalent Testing Load Circuit (V CC = 5.0V ± 10%)
2.5 ns of 50 Ω Transmission Line
From Output
Test
under Test
Point
Total Capacitance = 50 pF
0490-09
Figure 9. Transient Equivalent Testing Load Circuit (V CC = 3.3V ± 0.3V)
2.5 ns of 83 Ω Transmission Line
From Output
Test
under Test
Point
Total Capacitance = 30 pF
0490-10
Figure 10. High Speed Transient Equivalent Testing Load Circuit (V CC = 5.0V ± 5%)
23
E
DD28F032SA
6.4 DC Characteristics
VCC = 3.3V ± 0.3V, T A = 0°C to +70°C
3/5# = Pin Set High for 3.3V Operations
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
IIL
Input Load Current
1
±2
µA
VCC = VCC Max
VIN = VCC or GND
ILO
Output Leakage
Current
1
± 20
µA
VCC = VCC Max
VIN = VCC or GND
ICCS
VCC Standby
Current
100
200
µA
2
8
mA
VCC = VCC Max
CE0#, CEX#, RP#, = VCC ±
0.2V
BYTE#, WP#, 3/5# = V CC ±
0.2V or GND ± 0.2V
VCC= VCC Max
CE0#, CEX#, RP# = VIH
BYTE#, WP#, 3/5# = V IH or
VIL
1,5,6,8
ICCD
VCC Deep PowerDown Current
1
2
10
µA
ICCR1
VCC Read Current
1,4,5,6
25
30
mA
RP# = GND ± 0.2V
BYTE# = VCC ± 0.2V or GND
± 0.2V
VCC = VCC Max
CMOS: CE0#, CEX# = GND
± 0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V,
Inputs = GND ± 0.2V or
VCC ± 0.2V
f = 6.67 MHz, I OUT = 0 mA
26
34
mA
TTL: CE0#, CEX# = VIL,
BYTE# = VIL or VIH’
Inputs = VIL or VIH
f = 6.67 MHz, I OUT = 0 mA
ICCW
VCC Program
Current for Word or
Byte
1,7
8
12
mA
Program in Progress
ICCE
VCC Block Erase
Current
VCC Erase
Suspend Current
1,7
6
12
mA
Block Erase in Progress
1,2,6,7
3
6
mA
CE0#, CEX# = VIH
Block Erase Suspended
1
±2
± 20
µA
VPP ≤ VCC
130
400
µA
VPP > VCC
0.4
10
µA
RP# = GND ± 0.2V
ICCES
IPPS
VPP Standby/
IPPR
Read Current
IPPD
VPP Deep PowerDown Current
24
1
E
DD28F032SA
6.4 DC Characteristics (Continued)
VCC = 3.3V ± 0.3V, T A = 0°C to +70°C
3/5# Pin Set High for 3.3V Operations
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
IPPW
VPP Program
Current for Word or
Byte
1
10
15
mA
VPP = VPPH
Program in Progress
IPPE
VPP Block Erase
Current
1
4
10
mA
VPP = VPPH
Block Erase in Progress
IPPES
VPP Erase
Suspend Current
1
130
400
µA
VPP = VPPH
Block Erase Suspended
VIL
Input Low Voltage
–0.3
0.8
V
2.0
VCC
± 0.3
V
0.4
V
VCC = VCC Min
IOL = 4 mA
V
VCC = VCC Min
VIH
Input High Voltage
VOL
Output Low Voltage
VOH1
Output High
Voltage
2.4
IOH = –2.0 mA
VOH2
VPPL
VPPH
VLKO
VCC = VCC Min
IOH = –100 µA
VCC
– 0.2
VPP during Normal
Operations
VPP during
Program/Erase
Operations
VCC Program/Erase
Lock Voltage
3
0.0
11.4
2.0
12.0
6.5
V
12.6
V
V
NOTES:
1. All current are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V, T = 25°C. These currents are
valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the
range between VPPH and VPPL.
4. Automatic Power Savings (APS) reduces ICCR to <1 mA in static operation.
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
6. CEX# = CE1# or CE2#.
7. If operating with TTL levels, add 4 mA of VCC Standby Current to max ICCR1, ICCR2, ICCW, ICCE and ICCES.
8. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.
Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.
25
E
DD28F032SA
6.5 DC Characteristics
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
3/5# Pin Set Low for 5.0V Operations
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
IIL
Input Load Current
1
±2
µA
VCC = VCC Max
VIN = VCC or GND
ILO
Output Leakage
Current
1
± 20
µA
VCC = VCC Max
VIN = VCC or GND
ICCS
VCC Standby
Current
100
200
µA
4
8
mA
VCC = VCC Max
CE0#, CEX#, RP# = VCC ±
0.2V
BYTE#, WP#, 3/5# = V CC ±
0.2V or GND ± 0.2V
VCC = VCC Max
CE0#, CEX#, RP# = VIH
BYTE#, WP#, 3/5# = VIH or
VIL
1,5,6,8
RP# = GND ± 0.2V
BYTE# = VCC ± 0.2V or GND
± 0.2V
VCC = VCC Max
CMOS: CE0#, CEX# = GND ±
0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V,
Inputs = GND ± 0.2V or
VCC ± 0.2V
f = 10 MHz, I OUT = 0 mA
ICCD
VCC Deep PowerDown Current
1
4
25
µA
ICCR1
VCC Read Current
1,4,5,
6,7
50
60
mA
52
64
mA
TTL: CE0#, CEX# = VIL,
BYTE# = VIL or VIH,
Inputs = VIL or VIH
f = 10 MHz, I OUT = 0 mA
30
35
mA
VCC = VCC Max
CMOS: CE0#, CEX# = GND ±
0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V
Inputs = GND ± 0.2V or
VCC ± 0.2V
f = 5 MHz, I OUT = 0 mA
32
39
mA
TTL: CE0#, CEX# = VIL,
BYTE# = VIL or VIH,
Inputs = VIL or VIH
f = 5 MHz, I OUT = 0 mA
25
35
mA
Program in Progress
ICCR2
ICCW
26
VCC Read Current
VCC Prog. Current
for Word or Byte
1,4,5,
6,7
1,7
E
DD28F032SA
6.5 DC Characteristics (Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
3/5# Pin Set Low for 5.0V Operations
Symbol
ICCE
ICCES
Parameter
Notes
VCC Block Erase
Current
VCC Erase Suspend
Current
Min
Typ
Max
Units
Test Conditions
1,7
18
25
mA
Block Erase in Progress
1,2,6,7
5
10
mA
CE0#, CEX# = VIH
Block Erase Suspended
1
±2
± 20
µA
VPP ≤ VCC
130
400
µA
VPP > VCC
IPPS
VPP Standby/
IPPR
Read Current
IPPD
VPP Deep PowerDown Current
1
0.4
10
µA
RP# = GND ± 0.2V
IPPW
VPP Prog. Current
for Word or Byte
1
7
12
mA
VPP = VPPH
Program in Progress
IPPE
VPP Block Erase
Current
VPP Erase
Suspend Current
1
5
10
mA
1
130
400
µA
VPP = VPPH
Block Erase in Progress
VPP = VPPH
Block Erase Suspended
IPPES
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH1
Output High
Voltage
VPPH
VLKO
VPP during Normal
Operations
VPP during Prog.
Erase Operations
VCC Program/Erase
Lock Voltage
0.8
V
2.0
VCC
+ 0.5
V
0.45
V
VCC = VCC Min, IOL = 5.8 mA
V
VCC = VCC Min, IOH = –2.5 mA
0.85
VCC
VCC
– 0.4
VOH2
VPPL
–0.5
3
VCC = VCC Min, IOH = –100 µA
0.0
11.4
2.0
12.0
6.5
V
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V, T = +25°C. These currents are
valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the
range between VPPH and VPPL.
4. Automatic Power Saving (APS) reduces ICCR to <2 mA in static operation.
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
6. CEX#= CE1# or CE2#.
7. If operating with TTL levels, add 4 mA of VCC standby current. to max ICCR1, ICCR2, ICCW, ICCE and ICCES.
8. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.
Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.
27
E
DD28F032SA
6.6 AC Characteristics—Read Only Operations(1)
VCC = 3.3V ± 0.3V, T A = 0°C to +70°C
Versions (5)
Symbol
Parameter
DD28F032SA-150
Notes
Min
Max
150
Units
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CEX# to Output Delay
tPHQV
RP# High to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CEX# to Output in Low Z
3
tEHQZ
CEX# to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# to Output in High Z
3
tOH
Output Hold from Address, CEX# or
OE# Change, Whichever Occurs First
3
tFLQV
tFHQV
BYTE# to Output Delay
3
150
ns
tFLQZ
BYTE# Low to Output in High Z
3
40
ns
tELFL
tELFH
CEX# Low to BYTE# High or Low
3
5
ns
2
ns
150
ns
150
ns
750
ns
50
ns
0
ns
35
0
ns
ns
20
0
ns
ns
For Extended Status Register Reads
tAVEL
Address Setup to CEX# Going Low
3,4
0
ns
tAVGL
Address Setup to OE# Going Low
3,4
0
ns
28
E
DD28F032SA
6.6 AC Characteristics—Read Only Operations(1) (Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
Versions(5)
VCC ± 5%
DD28F032SA070(6)
VCC ± 10%
Sym
Parameter
Notes
Units
DD28F032SA080(7)
Min
Max
70
Min
Max
Min
Max
tAVAV
Read Cycle Time
tAVQV
Address to
Output Delay
tELQV
CEX# to Output
Delay
tPHQV
RP# to Output
Delay
tGLQV
OE# to Output
Delay
2
tELQX
CEX# to Output
in Low Z
3
tEHQZ
CEX# to Output
in High Z
3
tGLQX
OE# to Output in
Low Z
3
tGHQZ
OE# to Output in
High Z
3
tOH
Output Hold from
Address, CEX#
or OE# Change,
Whichever
Occurs First
3
tFLQV
tFHQV
BYTE# to Output
Delay
3
70
80
100
ns
tFLQZ
BYTE# Low to
Output in High Z
3
25
30
30
ns
tELFL
tELFH
CEX# Low to
BYTE# High or
Low
3
5
5
5
ns
2
80
DD28F032SA100(7)
100
ns
70
80
100
ns
70
80
100
ns
400
480
550
ns
30
35
40
ns
0
0
25
0
0
30
0
25
0
ns
30
0
15
0
ns
ns
15
0
ns
ns
For Extended Status Register Reads
tAVEL
Address Setup to
CEX# Going Low
3,4
0
0
0
ns
tAVGL
Address Setup to
OE# Going Low
3,4
0
0
0
ns
29
E
DD28F032SA
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX# without impact in tELQV.
3. Sampled, not 100% tested.
4. This timing parameter is used to latch the correct BSR data onto the outputs.
5. Device speeds are defined as:
70/80 ns at VCC = 5.0V equivalent to
150 ns at VCC = 3.3V
100 ns at VCC = 5.0V equivalent to
150 ns at VCC = VCC = 3.3V
6. See AC Input/Output Reverence Waveforms and AC Testing Load Circuits for High Speed Test Configuration.
7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
V IH
ADDRESSES STABLE
ADDRESSES (A)
VIL
t AVAV
V IH
CEx# (E)(1)
V IL
t AVEL
t EHQZ
VIH
t AVGL
OE# (G)
V IL
t GHQZ
VIH
WE# (W)
t GLQV
V IL
t ELQV
VOH
DATA (D/Q)
t
OH
t GLQX
tELQX
HIGH Z
HIGH Z
VALID OUTPUT
V OL
t AVQV
5.0V
V CC
GND
t
PHQV
VIH
RP# (P)
V IL
0490-11
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.
Figure 11. Read Timing Waveforms
30
E
DD28F032SA
VIH
ADDRESSES STABLE
ADDRESSES (A)
V IL
t AVAV
VIH
CEx #(E)
(1)
V IL
t AVFL = t ELFL
t EHQZ
VIH
t AVEL
OE# (G)
t GHQZ
V IL
t ELFL
t AVGL
VIH
t FLQV = t AVQV
BYTE# (F)
t GLQV
V IL
t
t ELQV
OH
t GLQX
VOH
t ELQX
HIGH Z
DATA (DQ0-DQ7)
t AVQV
VOH
DATA (DQ8-DQ15)
VOL
DATA
OUTPUT
DATA OUTPUT
VOL
HIGH Z
HIGH Z
t FLQZ
DATA
OUTPUT
HIGH Z
0490-12
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.
Figure 12. BYTE# Timing Waveforms
31
E
DD28F032SA
6.7 Power-Up and Reset Timings
VCC Power-Up
RP#
(P)
t YHPH
t YLPH
3/5#
5.0V
(Y)
t PLYL
4.5V
3.3V
VCC
0V
(3V,5V)
t PL5V
CE X #
t PHEL3
Address
(A)
t PHEL5
Valid
Valid
t AVQV
t AVQV
Data
(Q)
Valid 5.0V Outputs
Valid 3.3V Outputs
t PHQV
t PHQV
0490-13
Figure 13. VCC Power-Up and RP# Reset Waveforms
Symbol
Parameter
tPLYL
tPLYH
RP# Low to 3/5# Low (High)
tYLPH
tYHPH
3/5# Low (High) to RP# High
tPL5V
tPL3V
Notes
Min
Max
Units
0
µs
1
2
µs
RP# Low to VCC at 4.5V Minimum (to V CC at
3.0V min or 3.6V max)
2
0
µs
tPHEL3
RP# High to CE# Low (3.3V VCC)
1
500
tPHEL5
RP# High to CE# Low (5V VCC)
1
330
tAVQV
Address Valid to Data Valid for V CC = 5.0V ± 10%
3
80
ns
tPHQV
RP# High to Data Valid for VCC = 5.0V ± 10%
3
480
ns
NOTES:
CE0#, CEX# and OE# are switched low after Power-Up.
1. The tYLPH/tYHPH and tPHEL3/tPHEL5 times must be strictly followed to guarantee all other read and program specifications.
2. The power supply may start to switch concurrently with RP# going low.
3. The address access time and RP# high to data valid time are shown for the DD28F032SA-80 and 5.0V VCC operation.
Refer to the AC Characteristics-Read Only Operations for 3.3V VCC operation and all other speed options.
32
E
DD28F032SA
6.8 AC Characteristics for WE#—Controlled Command Write Operations(1)
VCC = 3.3V ± 0.3V, T A = 0°C to +70°C
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
tVPWH
VPP Setup to WE# Going High
tPHEL
DD28F032SA-150
Notes
Min
Typ
Max
Unit
150
ns
100
ns
RP# Setup to CEX# Going Low
480
ns
tELWL
CEX# Setup to WE# Going Low
10
ns
tAVWH
Address Setup to WE# Going High
2,6
75
ns
tDVWH
Data Setup to WE# Going High
2,6
85
ns
tWLWH
WE# Pulse Width
75
ns
tWHDX
Data Hold from WE# High
2
10
ns
tWHAX
Address Hold from WE# High
2
10
ns
tWHEH
CEX# Hold from WE# High
10
ns
tWHWL
WE# Pulse Width High
75
ns
tGHWL
Read Recovery before Write
0
ns
tWHRL
WE# High to RY/BY# Going Low
tRHPL
RP# Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High
tPHWL
RP# High Recovery to WE# Going Low
tWHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High
tWHQV1
Duration of Word/Byte Program Operation
tWHQV2
Duration of Block Erase Operation
3
100
3
ns
0
ns
1
µs
120
ns
0
µs
4,5
5
4
0.3
9
Note 7
µs
10
sec
33
E
DD28F032SA
6.8 AC Characteristics for WE#—Controlled Command Write Operations(1)
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
Versions
VCC ± 5%
DD28F032SA-070
VCC ± 10%
Sym
tAVAV
tVPWH
tPHEL
tELWL
tAVWH
tDVWH
tWLWH
tWHDX
tWHAX
tWHEH
tWHWL
tGHWL
tWHRL
34
Parameter
Write Cycle
Time
VPP Setup to
WE# Going
High
RP# Setup to
CEX# Going
Low
CEX# Setup
to WE# Going
Low
Address
Setup to WE#
Going High
Data Setup to
WE# Going
High
WE# Pulse
Width
Data Hold
from WE#
High
Address Hold
from WE#
High
CEX# Hold
from WE#
High
WE# Pulse
Width High
Read
Recovery
before Write
WE# High to
RY/BY#
Going Low
Notes
Min
Typ
Max
Unit
DD28F032SA-080
DD28F032SA-100
Min
Min
Typ
Max
Typ
Max
70
80
100
ns
100
100
100
ns
480
480
480
ns
0
0
0
ns
2,6
50
50
50
ns
2,6
60
60
60
ns
40
50
50
ns
2
0
0
0
ns
2
10
10
10
ns
10
10
10
ns
30
30
50
ns
0
0
0
ns
3
100
100
100
ns
E
DD28F032SA
6.8 AC Characteristics for WE#—Controlled Command Write Operations(1)
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
Versions
VCC ± 5%
DD28F032SA-070
VCC ± 10%
Sym
Parameter
RP# Hold
tRHPL
from Valid
Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High
RP# High
tPHWL
Recovery to
WE# Going
Low
Write
tWHGL
Recovery
before Read
VPP Hold from
tQVVL
Valid Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High
tWHQV1 Duration of
Word/Byte
Program
Operation
tWHQV2 Duration of
Block Erase
Operation
DD28F032SA-100
Min
Min
Min
3
0
0
0
ns
1
1
1
µs
60
65
65
ns
0
0
0
µs
4.5
4
0.3
6
Max
DD28F032SA-080
Notes
4,5
Typ
Unit
Note
7
4.5
10
0.3
Typ
6
Max
Note
7
4.5
10
0.3
Typ
6
Max
Note
7
µs
10
sec
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.
1. Read timings during data program and block erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested
4. Data program/block erase durations are measured to valid Status Register data.
5. Word/byte program operations are typically performed with 1 programming pulse.
6. Address and data are latched on the rising edge of WE# for all command write operations.
7. This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for
more information.
35
E
DD28F032SA
DEEP
POWER-DOWN
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
AUTOMATED DATA-WRITE
& DATA (DATA-WRITE) OR
OR ERASE DELAY
ERASE CONFIRM COMMAND
WRITE READ EXTENDED
REGISTER COMMAND
READ EXTENDED
STATUS REGISTER DATA
V
IH
ADDRESSES (A)
V
NOTE 1
IL
A
t
t
t
WHAX
READ COMPATIBLE
STATUS REGISTER DATA
AVWH
NOTE 3
V
IH
ADDRESSES (A)
V
NOTE 2
IL
A
t
V
A=RA
IN
AVAV
t
AVAV
IN
t
AVWH
WHAX
IH
CEx # (E)
NOTE 4
V
IL
t
t
ELWL
WHEH
t
V
OE# (G)
V
IL
t
V
WHGL
IH
t
WHWL
t
WHQV1,2
GHWL
IH
WE# (W)
V
IL
t
t
V
DATA (D/Q)
V
IH
IL
WLWH
t
t
DVWH
HIGH Z
D
IN
WHDX
D
D
IN
t
V
RY/BY# (R)
V
D
IN
D
OUT
IN
PHWL
WHRL
OH
OL
t
V
IH
RHPL
NOTE 5
RP# (P)
V
IL
t
V
V
V
PP
(V)
V
VPWH
t
QVVL
PPH
PPL
IH
V IL
0490-14
NOTES:
1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/block erase operations.
4. For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high
5. RP# low transition is only to show tRHPL; not valid for above Read and Program cycles.
Figure 14. AC Waveforms for Command Write Operations
36
E
DD28F032SA
6.9 AC Characteristics for CEX#—Controlled Command Write Operations(1)
VCC = 3.3V ± 0.3V, T A = 0°C to +70°C
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
tVPEH
VPP Setup to CEX# Going High
tPHWL
DD28F032SA-150
Notes
Min
Typ
Max
Unit
150
ns
100
ns
RP# Setup to WE# Going Low
480
ns
tWLEL
WE# Setup to CEX# Going Low
0
ns
tAVEH
Address Setup to CEX# Going High
2,6
75
ns
tDVEH
Data Setup to CEX# Going High
2,6
85
ns
tELEH
CEX# Pulse Width
75
ns
tEHDX
Data Hold from CEX# High
2
10
ns
tEHAX
Address Hold from CEX# High
2
10
ns
tEHWH
WE# Hold from CEX# High
10
ns
tEHEL
CEX# Pulse Width High
75
ns
tGHEL
Read Recovery before Write
0
ns
tEHRL
CEX# High to RY/BY# Going Low
tRHPL
RP# Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High
tPHEL
RP# High Recovery to CEX# Going Low
tEHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High
tEHQV1
Duration of Word/Byte Program Operation
tEHQV2
Duration of Block Erase Operation
3
100
3
ns
0
ns
1
µs
120
ns
0
µs
4,5
5
4
0.3
9
Note 7
µs
10
sec
37
E
DD28F032SA
6.9 AC Characteristics for CEX#—Controlled Command Write Operations(1)
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
Versions
VCC ± 5%
DD28F032SA-070
VCC ± 10%
Sym
tAVAV
tVPEH
tPHWL
tWLEL
tAVEH
tDVEH
tELEH
tEHDX
tEHAX
tEHWH
tEHEL
tGHEL
tEHRL
tRHPL
38
Parameter
Write Cycle
Time
VPP Setup to
CEX# Going
High
RP# Setup to
WE# Going
Low
WE# Setup to
CEX# Going
Low
Address Setup
to CEX# Going
High
Data Setup to
CEX# Going
High
CEX# Pulse
Width
Data Hold
from CEX#
High
Address Hold
from CEX#
High
WE# Hold
from CEX#
High
CEX# Pulse
Width High
Read
Recovery
before Write
CEX# High to
RY/BY# Going
Low
RP# Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High
Notes
Min
Typ
Max
Unit
DD28F032SA-080
DD28F032SA-100
Min
Min
Typ
Max
Typ
Max
70
80
100
ns
3
100
100
100
ns
3
480
480
480
ns
0
0
0
ns
2,6
50
50
50
ns
2,6
60
60
60
ns
40
50
50
ns
2
0
0
0
ns
2
10
10
10
ns
10
10
10
ns
30
30
50
ns
0
0
0
ns
100
3
0
100
0
100
0
ns
ns
E
DD28F032SA
6.9 AC Characteristics for CEX#—Controlled Command Write Operations(1)
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
Versions
VCC ± 5%
DD28F032SA-070
VCC ± 10%
Sym
Parameter
RP# High
Recovery to
CEX#
Going Low
Write
tEHGL
Recovery
before Read
VPP Hold from
tQVVL
Valid Status
Register
(CSR, GSR,
BSR) Data at
RY/BY# High
tEHQV1 Duration of
Word/Byte
Program
Operation
tEHQV2 Duration of
Block Erase
Operation
Notes
tPHEL
Min
Typ
Max
Unit
DD28F032SA-080
DD28F032SA-100
Min
Min
Typ
Max
Typ
Max
1
1
1
µs
60
65
80
ns
0
0
0
µs
4,5
4.5
4
0.3
6
Note
7
4.5
10
0.3
6
Note
7
4.5
10
0.3
6
Note
7
µs
10
sec
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.
1. Read timings during data program and block erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Data program/block erase durations are measured to valid Status Register data.
5. Word/byte program operations are typically performed with 1 programming pulse.
6. Address and data are latched on the rising edge of CEX# for all command write operations.
7. This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for
more information.
39
E
DD28F032SA
DEEP
POWER-DOWN
WRITE VALID ADDRESS
AUTOMATED DATA-WRITE
& DATA (DATA-WRITE) OR
OR ERASE DELAY
ERASE CONFIRM COMMAND
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE READ EXTENDED
REGISTER COMMAND
READ EXTENDED
STATUS REGISTER DATA
V
IH
ADDRESSES (A)
V
NOTE 1
IL
A
t
A=RA
IN
t
AVAV
t
READ COMPATIBLE
STATUS REGISTER DATA
EHAX
AVEH
NOTE 3
V
IH
ADDRESSES (A)
V
NOTE 2
IL
A
t
V
t
AVAV
IN
t
AVEH
EHAX
IH
WE# (W)
V
IL
t
t
WLEL
EHWH
t
V
OE# (G)
V
IL
t
V
CEx#(E)
V
NOTE 4
GHEL
IH
IL
ELEH
t
t
DVEH
HIGH Z
D
IN
EHDX
D
D
IN
D
IN
D
OUT
IN
PHEL
t
V
RY/BY# (R)
V
t
EHQV1,2
IL
t
DATA (D/Q)
V
t
EHEL
IH
t
V
EHGL
IH
EHRL
OH
OL
t
V
IH
RHPL
NOTE 5
RP# (P)
V
IL
t
V
V
V
(V)
PP
V
V
VPEH
t
QVVL
PPH
PPL
IH
IL
0490_15
NOTES:
1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/block erase operations.
4. For 28F016SA No. 1:CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.
5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 15. Alternate AC Waveforms for Command Write Operations
40
E
DD28F032SA
6.10 AC Characteristics for Page Buffer Write Operations(1)
VCC = 3.3V ± 0.3V, T A = 0°C to +70°C
Versions
Symbol
Parameter
DD28F032SA-150
Notes
Min
Typ
Max
Unit
tAVAV
Write Cycle Time
150
ns
tELWL
CEX# Setup to WE# Going Low
10
ns
tAVWL
Address Setup to WE# Going Low
3
0
ns
tDVWH
Data Setup to WE# Going High
2
75
ns
tWLWH
WE# Pulse Width
75
ns
tWHDX
Data Hold from WE# High
2
10
ns
tWHAX
Address Hold from WE# High
2
10
ns
tWHEH
CEX# Hold from WE# High
10
ns
tWHWL
WE# Pulse Width High
75
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
120
ns
41
DD28F032SA
6.10 AC Characteristics for Page Buffer Write Operations(1) (Continued)
E
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0°C to +70°C
Versions
Symbol
Parameter
Notes
DD28F032SA-070
DD28F032SA-080
DD28F032SA-100
Min
Min
Min
Typ
Max
Typ
Max
Typ
Max
Unit
tAVAV
Write Cycle
Time
70
80
100
ns
tELWL
CEX# Setup to
WE# Going
Low
0
0
0
ns
tAVWL
Address Setup
to WE# Going
Low
3
0
0
0
ns
tDVWH
Data Setup to
WE# Going
High
2
50
50
50
ns
tWLWH
WE# Pulse
Width
40
50
50
ns
tWHDX
Data Hold from
WE# High
2
0
0
0
ns
tWHAX
Address Hold
from WE# High
2
10
10
10
ns
tWHEH
CEX# Hold from
WE# High
10
10
10
ns
tWHWL
WE# Pulse
Width High
30
30
50
ns
tGHWL
Read Recovery
before Write
0
0
0
ns
tWHGL
Write Recovery
before Read
60
65
80
ns
NOTES:
For 28F016SA No. 1: CEX # is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX # is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.
1. These are WE#-controlled write timings, equivalent CEX#-controlled write timings apply.
2. Sampled, not 100% tested.
3. Address must be valid during the entire WE# low pulse or the entire CEX # low pulse (for CEX #-controlled write timings).
42
E
DD28F032SA
V
IH
CEx#
(E)
t WHEH
V
IL
t ELWL
V
IH
WE#
(W)
t WHWL
V
t AVWL
IL
t WLWH
t
WHAX
V
IH
ADDRESSES (A)
VALID
V
IL
t DVWH
t WHDX
V
IH
DATA
(D/Q)
V
HIGH Z
DIN
IL
0490-16
Figure 16. Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
43
DD28F032SA
6.11 Erase and Word/Byte Write Performance, Cycling Performance
and Suspend Latency(3)
E
VCC = 3.3V ± 0.3V, V PP = 12.0V ± 0.6V, T A = 0°C to +70°C
Sym
Parameter
Notes
Page Buffer Byte Write Time
2,4
Page Buffer Word Write Time
Min
2,4
Typ(1)
Max
Units
3.26
Note 6
µs
Note 6
µs
6.53
Test Conditions
tWHRH1
Word/Byte Program Time
tWHRH2
Block Program Time
2
0.6
2.1
sec
Byte Program
Block Program Time
2
0.3
1.0
sec
Word Program
10
sec
tWHRH3
2
9
Note 6 µs
Block Erase Time
2
0.8
Full Chip Erase Time
2
51.2
sec
7.0
µs
10.0
µs
Erase Suspend Latency Time
to Read
Auto Erase Suspend Latency
Time to Program
Erase Cycles
5
100,000 1,000,000
Cycles
VCC = 5.0V ± 0.5V, V PP = 12.0V ± 0.6V, T A = 0°C to +70°C
Sym
Typ(1)
Max
Units
2,4
2.76
Note 6
µs
Parameter
Notes
Page Buffer Byte Write Time
Page Buffer Word Write Time
Min
Test Conditions
2,4
5.51
Note 6
µs
tWHRH1
Word/Byte Program Time
2
6
Note 6
µs
tWHRH2
Block Program Time
2
0.4
2.1
sec
Byte Program
tWHRH3
Block Program Time
2
0.2
1.0
sec
Word Program
10
sec
Block Erase Time
2
0.6
Full Chip Erase Time
2
38.4
sec
5.0
µs
8.0
µs
Erase Suspend Latency Time
to Read
Auto Erase Suspend Latency
Time to Program
Erase Cycles
5
100,000 1,000,000
Cycles
NOTES:
1. +25°C, VCC = 3.3V or 5.0V nominal, VPP = 12.0V nominal, 10K cycles.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. This assumes using the full Page Buffer to program to the flash memory (256 bytes or 128 words).
5. 1,000,000 cycle performance assumes the application uses block retirement techniques.
6. This information will be available in a technical paper. Please call Intel’s Application hotline or your local Intel sales office for
more information.
44
E
DD28F032SA
7.0 DERATING CURVES
290489-16.eps
290489-19.eps
Figure 17. ICC vs. Frequency (VCC = 5.5V) for x8
or x16 Operation
Figure 19. ICC vs. Frequency (VCC = 3.6V) for x8
or x16 Operation
290489-18.eps
Figure 18. ICC during Block Erase
290489-21.eps
Figure 20. IPP during Block Erase
45
E
DD28F032SA
290489-24.eps
Figure 21. Access Time (tACC) vs. Output Loading
290489-25.eps
Figure 22. IPP during Word Write Operation
46
290490-26.eps
Figure 23. IPP during Page Buffer Write
Operation
E
DD28F032SA
8.0 MECHANICAL SPECIFICATIONS
Z
A2
O
SEE DETAIL
O
e
E
Y
O
O
D1
A1
D
SEATING
PLANE
SEE DETAIL A
A
DETAIL B
DETAIL A
C
Ø
L
b
290490-26
Figure 24. Mechanical Specifications of the Dual Die 56-Lead TSOP Type I Package
Family: Dual Die Thin Small Out-Line Package
Symbol
Millimeters
Minimum
Nominal
A
Notes
Maximum
1.20
A1
0.05
A2
0.965
0.995
1.025
b
0.100
0.150
0.200
c
0.115
0.125
0.135
D1
18.20
18.40
18.60
E
13.80
14.00
14.20
D
19.80
20.00
20.20
L
0.500
0.600
0.700
e
0.50
N
∅
56
0°
3°
Y
Z
5°
0.100
0.150
0.250
0.350
47
E
DD28F032SA
APPENDIX A
DEVICE NOMENCLATURE/ORDERING INFORMATION
DD 2 8 F 0 3 2 SA - 0 7 0
DUAL DIE
ACCESS SPEED (ns)
70 ns
100 ns
NOTES:
Two valid combinations of speeds exist:
DD28F032SA-070, DD28F032SA-080, DD28F032SA-150
or
DD28F032SA-100, DD28F032SA-150
Option
Order Code
Valid Combinations
VCC = 3.3V
± 0.3V, 50 pF
48
1
DD28F032SA-070
DD28F032SA-150
2
DD28F032SA-100
DD28F032SA-150
VCC = 5.0V
± 5%, 30 pF
DD28F032SA-070
VCC = 5.0V
± 10%, 100 pF
DD28F032SA-080
DD28F032SA-100
E
Order Number
DD28F032SA
APPENDIX B
ADDITIONAL INFORMATION(1,2)
Document/Tool
297372
16-Mbit Flash Product Family User’s Manual
290489
28F016SA 16-Mbit FlashFile™ Memory Datasheet
290528
28F016SV FlashFile™ Memory Datasheet
290429
28F008SA 8-Mbit FlashFile™ Memory Datasheet
292092
AP-357 Power Supply Solutions for Flash Memory
292123
AP-374 Flash Memory Write Protection Techniques
292124
AP-375 Upgrade Considerations from the 28F008SA to the 28F016SA”
292126
AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV,
28F016XS, 28F016XD
292127
AP-378 System Optimization Using the Enhanced Features of the 28F016SA
292144
AP-393 28F016SV Compatibility with 28F016SA
292159
AP-607 Multi-Site Layout Planning with Intel’s Flash File™ Components
294016
ER-33 ETOX™ Flash Memory Technology– Insight to Intel’s Fourth Generation
Process Innovation
297534
Small and Low-Cost Power Supply Solutions for Intel’s Flash Memory Products
(Technical Paper)
297508
FLASHBuilder Design Resource Tool
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
49