TI TPA6211A1DRB

TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
3.1-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
Designed for Wireless or Cellular Handsets
and PDAs
3.1 W Into 3Ω From a 5-V Supply at
THD = 10% (Typ)
Low Supply Current: 4 mA Typ at 5 V
Shutdown Current: 0.01 µA Typ
Fast Startup With Minimal Pop
Only Three External Components
– Improved PSRR (-80 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
– Fully Differential Design Reduces RF
Rectification
– -63 dB CMRR Eliminates Two Input
Coupling Capacitors
Ideal for Wireless Handsets, PDAs, and
Notebook Computers
DESCRIPTION
The TPA6211A1 is a 3.1-W mono fully-differential
amplifier designed to drive a speaker with at least
3-Ω impedance while consuming only 20 mm2 total
printed-circuit board (PCB) area in most applications.
The device operates from 2.5 V to 5.5 V, drawing
only 4 mA of quiescent supply current. The
TPA6211A1 is available in the space-saving
3-mm × 3-mm QFN (DRB) and the 8-pin MSOP
(DGN) PowerPAD™ packages.
Features like -80 dB supply voltage rejection from
20 Hz to 2 kHz, improved RF rectification immunity,
small PCB area, and a fast startup with minimal pop
makes the TPA6211A1 ideal for PDA/smart phone
applications.
APPLICATION CIRCUIT
VDD
6
In From
DAC
RI
+ RI
4
3
ININ+
_
C(BYPASS)(1)
(1)
1
VO+
5
VO-
8
GND
7
SHUTDOWN
1
8 V
O-
BYPASS
2
7 GND
IN+
3
6 VDD
IN-
4
5 VO+
+
40 kΩ
SHUTDOWN
To Battery
Cs
40 kΩ
-
8-PIN QFN (DRB) PACKAGE
(TOP VIEW)
Bias
Circuitry
100 kΩ
2
DGN PACKAGE
(TOP VIEW)
SHUTDOWN
BYPASS
IN+
IN-
1
8
2
7
3
6
4
5
VOGND
VDD
VO+
C(BYPASS) is optional.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES (1)
(1)
TA
SMALL OUTLINE
(DRB)
MSOP PowerPAD™
(DGN)
EVALUATION MODULES
-40°C to 85°C
TPA6211A1DRB
TPA6211A1DGN
TPA6211A1EVM
The DGN and DRB are available taped and reeled. To order taped and reeled parts, add the suffix R
to the part number (TPA6211A1DGNR or TPA6211A1DRBR).
Terminal Functions
TERMINAL
NAME
DRB, DGN
I/O
DESCRIPTION
IN-
4
I
Negative differential input
IN+
3
I
Positive differential input
VDD
6
I
Power supply
VO+
5
O
Positive BTL output
GND
7
I
High-current ground
VO-
8
O
Negative BTL output
SHUTDOWN
1
I
Shutdown terminal (active low logic)
BYPASS
2
Thermal Pad
-
Mid-supply voltage, adding a bypass capacitor improves PSRR
-
Connect to ground. Thermal pad must be soldered down in all applications to properly secure
device on the PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
VDD
Supply voltage
VI
Input voltage
-0.3 V to 6 V
-0.3 V to VDD + 0.3 V
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature
-40°C to 85°C
TJ
Junction temperature
-40°C to 150°C
Tstg
Storage temperature
-65°C to 85°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
(1)
DRB
260°C
DGN
235°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
(1)
2
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR (1)
TA= 70°C
POWER RATING
TA= 85°C
POWER RATING
DGN
2.13 W
17.1 mW/°C
1.36 W
1.11 W
DRB
2.7 W
21.8 mW/°C
1.7 W
1.4 W
Derating factor based on high-k board layout.
TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
RECOMMENDED OPERATION CONDITIONS
MIN
VDD
Supply voltage
VIH
High-level input voltage
SHUTDOWN
VIL
Low-level input voltage
SHUTDOWN
TA
Operating free-air temperature
TYP
MAX
2.5
5.5
1.55
UNIT
V
V
0.5
V
85
°C
-40
ELECTRICAL CHARACTERISTICS
TA = 25°C
PARAMETER
TEST CONDITIONS
VOS
Output offset voltage (measured
differentially)
VI = 0 V differential, Gain = 1 V/V, VDD = 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
VIC
Common mode input range
VDD = 2.5 V to 5.5 V
CMRR
Common mode rejection ratio
Low-output swing
High-output swing
MIN
TYP
-9
MAX
UNIT
0.3
9
mV
-85
-60
dB
VDD-0.8
V
0.5
VDD = 5.5 V,
VIC = 0.5 V to 4.7 V
-63
-40
VDD = 2.5 V,
VIC = 0.5 V to 1.7 V
-63
-40
RL = 4 Ω,
VIN+ = VDD,
VIN+ = 0 V,
VDD = 5.5 V
Gain = 1 V/V,
VIN- = 0 V or VDD = 3.6 V
VIN- = VDD
VDD = 2.5 V
0.45
RL = 4 Ω,
VIN+ = VDD,
VIN- = VDD
VDD = 5.5 V
Gain = 1 V/V,
VIN- = 0 V or VDD = 3.6 V
VIN+ = 0 V
VDD = 2.5 V
4.95
0.37
0.26
V
0.4
3.18
2
dB
V
2.13
| IIH |
High-level input current, shutdown
VDD = 5.5 V,
VI = 5.8 V
58
100
| IIL |
Low-level input current, shutdown
VDD = 5.5 V,
VI = -0.3 V
3
100
µA
IQ
Quiescent current
VDD = 2.5 V to 5.5 V, no load
4
5
mA
I(SD)
Supply current
V(SHUTDOWN) ≤ 0.5 V, VDD = 2.5 V to 5.5 V,
RL = 4Ω
0.01
1
µA
Gain
RL = 4Ω
Resistance from shutdown to GND
38 k
RI
40 k
RI
100
42 k
RI
µA
V/V
kΩ
3
TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
THD + N= 1%, f = 1 kHz, RL = 3 Ω
PO
Output power
THD + N= 1%, f = 1 kHz, RL = 4 Ω
THD + N= 1%, f = 1 kHz, RL = 8 Ω
MIN
THD+N
Total harmonic distortion plus
noise
f = 1 kHz, RL = 4 Ω
f = 1 kHz, RL = 8 Ω
MAX
VDD = 5 V
2.45
VDD = 3.6 V
1.22
VDD = 2.5 V
0.49
VDD = 5 V
2.22
VDD = 3.6 V
1.1
VDD = 2.5 V
0.47
VDD = 5 V
1.36
VDD = 3.6 V
0.72
VDD = 2.5 V
f = 1 kHz, RL = 3 Ω
TYP
VDD = 5 V
0.045%
PO = 1 W
VDD = 3.6 V
0.05%
PO = 300 mW
VDD = 2.5 V
0.06%
PO = 1.8 W
VDD = 5 V
0.03%
PO = 0.7 W
VDD = 3.6 V
0.03%
PO = 300 mW
VDD = 2.5 V
0.04%
PO = 1 W
VDD = 5 V
0.02%
PO = 0.5 W
VDD = 3.6 V
0.02%
PO = 200 mW
VDD = 2.5 V
0.03%
f = 217 Hz
-80
f = 20 Hz to 20 kHz
-70
kSVR
Supply ripple rejection ratio
VDD = 3.6 V, Inputs ac-grounded with
Ci = 2 µF, V(RIPPLE) = 200 mVpp
SNR
Signal-to-noise ratio
VDD = 5 V, PO = 2 W, RL = 4 Ω
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 µF
No weighting
15
A weighting
12
CMRR
Common mode rejection ratio
VDD = 3.6 V, VIC = 1 Vpp
f = 217 Hz
-65
ZI
Input impedance
Start-up time from shutdown
4
dB
105
38
VDD = 3.6 V, CBYPASS = 0.1 µF
W
0.33
PO = 2 W
VDD = 3.6 V, No CBYPASS
UNIT
40
dB
µVRMS
dB
44
kΩ
4
µs
27
ms
TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
PO
Output power
PD
Power dissipation
THD+N
Total harmonic distortion + noise
vs Supply voltage
1
vs Load resistance
2
vs Output power
3, 4
vs Output power
5, 6, 7
vs Frequency
8-12
vs Common-mode input voltage
13
KSVR
Supply voltage rejection ratio
vs Frequency
KSVR
Supply voltage rejection ratio
vs Common-mode input voltage
18
GSM Power supply rejection
vs Time
19
GSM Power supply rejection
vs Frequency
20
vs Frequency
21
vs Common-mode input voltage
22
Closed loop gain/phase
vs Frequency
23
Open loop gain/phase
vs Frequency
24
vs Supply voltage
25
vs Shutdown voltage
26
vs Bypass capacitor
27
CMRR
IDD
Common-mode rejection ratio
Supply current
Start-up time
14, 15, 16, 17
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
3.5
3
3.5
f = 1 kHz
Gain = 1 V/V
3
VDD = 5 V, THD 1%
PO = 3 Ω, THD 1%
PO - Output Power - W
PO - Output Power - W
PO = 4 Ω, THD 10%
2.5
PO = 4 Ω, THD 1%
2
1.5
PO = 8 Ω, THD 10%
PO = 8 Ω, THD 1%
1
0.5
0
2.5
f = 1 kHz
Gain = 1 V/V
VDD = 5 V, THD 10%
PO = 3 Ω, THD 10%
2.5
VDD = 3.6 V, THD 10%
2
VDD = 3.6 V, THD 1%
1.5
VDD = 2.5 V, THD 10%
VDD = 2.5 V, THD 1%
1
0.5
0
3
3.5
4
VDD - Supply Voltage - V
Figure 1.
4.5
5
3
8
13
18
23
28
RL - Load Resistance - Ω
Figure 2.
5
TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
POWER DISSIPATION
vs
OUTPUT POWER
POWER DISSIPATION
vs
OUTPUT POWER
1.4
0.8
VDD = 3.6 V
1.2
4Ω
0.6
PD - Power Dissiaption - W
PD - Power Dissiaption - W
0.7
0.5
0.4
8Ω
0.3
0.2
0
0
0.3
0.6
0.9
1.2
PO - Output Power - W
1.5
8Ω
0.6
0.4
0
0.3
0.6
0.9
1.2
PO - Output Power - W
1.5
1.8
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
RL = 3 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
0.8
0
1.8
10
5
1
0.2
0.1
2
1
0.5
0.2
2.5 V
3.6 V
0.1
5V
0.05
0.02
0.01
20m
50m 100m 200m
500m 1
PO - Output Power - W
Figure 5.
6
4Ω
VDD = 5 V
2
3
10
5
RL = 4 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
2
1
0.5
2.5 V
0.2
3.6 V
5V
0.1
0.05
0.02
0.01
10m 20m
50m 100m 200m 500m 1
PO - Output Power - W
Figure 6.
2 3
TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
5
10
RL = 8 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
20
2
1
2.5 V
0.5
3.6 V
0.2
5V
0.1
0.05
0.02
0.01
10m 20m
2
1
0.5
1W
0.2
0.1
2W
0.05
0.02
0.01
0.005
50m 100m 200m 500m 1
PO - Output Power - W
20
2 3
50
100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
10
VDD = 5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
VDD = 5 V,
RL = 3 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2W
0.5
1.8 W
0.2
1W
0.1
0.05
0.02
0.01
VDD = 3.6 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
0.5
1W
0.1 W
0.2
0.5 W
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.005
20
50
100 200 500 1k 2k
f - Frequency - Hz
Figure 9.
5k 10k 20k
20
50
100 200 500 1k 2k
f - Frequency - Hz
5k
10k 20k
Figure 10.
7
TPA6211A1
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VDD = 2.5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
0.5
0.4 W
0.2
0.28 W
0.1
0.05
0.02
0.01
0.005
0.002
0.001
50
100 200
500 1k 2k
f - Frequency - Hz
5k
1
0.5
0.25 W
0.6 W
0.2
0.1 W
0.1
0.05
0.02
0.01
0.005
0.002
10k 20k
20
k SVR - Supply Voltage Rejection Ratio - dB
VDD = 2.5 V
0.05
VDD = 5 V
0.048
0.046
VDD = 3.6 V
0.044
0.042
0.04
10k 20k
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
0.054
0.052
5k
TOTAL HARMONIC DISTORTION + NOISE
vs
COMMON MODE INPUT VOLTAGE
+0
0.056
100 200
500 1k 2k
f - Frequency - Hz
Figure 12.
f = 1 kHz
PO = 200 mW,
RL = 1 kHz
0.058
50
Figure 11.
0.06
THD+N - Total Harmonic Distortion + Noise - %
2
0.001
20
-10
-20
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 1 V/V,
CI = 2 µF,
Inputs ac Grounded
-30
-40
-50
-60
VDD = 3.6 V
VDD = 2.5 V
-70
-80
-90
VDD = 5 V
-100
0
1
2
3
4
VIC - Common Mode Input Voltage - V
Figure 13.
8
VDD = 3.6 V,
RL = 8 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
5
20
50
100 200
500 1k
f - Frequency - Hz
Figure 14.
2k
5k
10k 20k
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
-10
-20
-30
+0
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 5 V/V,
CI = 2 µF,
Inputs ac Grounded
k SVR - Supply Voltage Rejection Ratio - dB
k SVR - Supply Voltage Rejection Ratio - dB
+0
-40
-50
VDD = 2.5 V
-60
VDD = 3.6 V
-70
-80
VDD = 5 V
-90
-100
20
50
100 200
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
500 1k
2k
5k
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
CI = 2 µF,
VDD = 2.5 V to 5 V
Inputs Floating
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10k 20k
20
50
100 200
f - Frequency - Hz
−10
−20
SUPPLY VOLTAGE REJECTION RATIO
vs
DC COMMON MODE INPUT
0
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
VDD = 3.6 V
C(BYPASS) = 0.1 µF
−60
No C(BYPASS)
−70
−80
−100
20
10k 20k
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
−40
−90
5k
Figure 16.
−30
−50
2k
Figure 15.
k SVR − Supply Voltage Rejection Ratio − dB
k SVR − Supply Voltage Rejection Ratio − dB
+0
500 1k
f - Frequency - Hz
C(BYPASS) = 1 µF
C(BYPASS) = 0.47 µF
50
100 200
500 1k
2k
f − Frequency − Hz
Figure 17.
5k
10k 20k
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
C(BYPASS) = 0.47 µF
VDD = 3.6 V,
f = 217 Hz,
Inputs ac Grounded
−10
−20
−30
−40
VDD = 2.5 V
VDD = 3.6 V
−50
−60
−70
VDD = 5 V
−80
−90
−100
0
1
2
3
4
DC Common Mode Input − V
5
6
Figure 18.
9
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
GSM POWER SUPPLY REJECTION
vs
TIME
VDD
Voltage − V
C1
Frequency
217 Hz
C1 − Duty
20%
C1 Pk−Pk
500 mV
RL = 8 Ω
CI = 2.2 µF
VOUT
C(BYPASS) = 0.47 µF
2 ms/div
Ch1 100 mV/div
Ch4 10 mV/div
t − Time − ms
Figure 19.
0
−50
VO − Output Voltage − dBV
−100
VDD Shown in Figure 19,
RL = 8 Ω,
CI = 2.2 µF,
Inputs Grounded
−100
−120
−140
−160
−180
0
C(BYPASS) = 0.47 µF
400
800
1200
f − Frequency − Hz
1600
Figure 20.
10
−150
2000
VDD − Supply Voltage − dBV
GSM POWER SUPPLY REJECTION
vs
FREQUENCY
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SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
COMMON MODE REJECTION RATIO
vs
FREQUENCY
-20
-30
-40
VDD = 2.5 V
-50
-60
-70
VDD = 5 V
-80
-90
-100
20
50
100 200
500 1k
2k
5k
-20
-30
-40
-50
VDD = 2.5 V
-60
-80
0
0.5
180
100
150
90
3.5
-20
0
-30
-30
-40
-60
-50
-90
VDD = 5 V
RL = 8 Ω
AV = 1
-120
-150
-180
-80
Figure 23.
5
1M
10 M
120
90
60
Gain
50
Gain − dB
30
Phase - Degrees
60
Gain
-10
1 k 10 k 100 k
f - Frequency - Hz
4.5
150
70
90
100
4
180
VDD = 5 V,
RL = 8 Ω
80
120
10
Gain - dB
3
OPEN LOOP GAIN/PHASE
vs
FREQUENCY
20
10
2.5
CLOSED LOOP GAIN/PHASE
vs
FREQUENCY
30
1
2
Figure 22.
Phase
-70
1.5
Figure 21.
40
-60
1
VIC - Common Mode Input Voltage - V
f - Frequency - Hz
0
VDD = 5 V
VDD = 3.5 V
-70
-90
10k 20k
RL = 4 Ω,,
Gain = 1 V/V,
dc Change in VIC
-10
60
40
30
30
0
20
−30
10
−60
Phase
0
−10
Phase − Degrees
-10
0
RL = 4 Ω,,
VIC = 200 mV Vp-p,
Gain = 1 V/V,
CMRR - Common Mode Rejection Ratio - dB
CMRR - Common-Mode Rejection Ratio - dB
+0
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
−90
−20
−120
−30
−150
−40
100
1k
10 k
100 k
f − Frequency − Hz
−180
1M
Figure 24.
11
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SUPPLY CURRENT
vs
SUPPLY VOLTAGE
5
10
VDD = 5 V
TA = 125°C
4.5
VDD = 5 V
1
4
I DD - Supply Current - mA
I DD - Supply Current - mA
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
TA = 25°C
3.5
3
TA = -40°C
2.5
2
1.5
1
VDD = 3.6 V
0.1
VDD = 2.5 V
0.01
0.001
0.0001
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0.00001
VDD - Supply Voltage - V
1
2
3
4
5
Voltage on SHUTDOWN Terminal - V
Figure 25.
Figure 26.
0
START-UP TIME
vs
BYPASS CAPACITOR
300
Start-Up Time - ms
250
200
150
100
50
0
0
0.2
0.4
0.6
0.8
C(Bypass) - Bypass Capacitor - µF
Figure 27.
12
1
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
APPLICATION INFORMATION
•
Mid-supply bypass capacitor, C(BYPASS), not
required: The fully differential amplifier does not
require a bypass capacitor. Any shift in the
mid-supply voltage affects both positive and
negative channels equally, thus canceling at the
differential output. Removing the bypass capacitor slightly worsens power supply rejection ratio
(kSVR), but a slight decrease of kSVR may be
acceptable when an additional component can be
eliminated (See Figure 17).
Better RF-immunity: GSM handsets save power
by turning on and shutting off the RF transmitter
at a rate of 217 Hz. The transmitted signal is
picked-up on input and output traces. The fully
differential amplifier cancels the signal much
better than the typical audio amplifier.
FULLY DIFFERENTIAL AMPLIFIER
The TPA6211A1 is a fully differential amplifier with
differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a
common- mode amplifier. The differential amplifier
ensures that the amplifier outputs a differential voltage that is equal to the differential input times the
gain. The common-mode feedback ensures that the
common-mode voltage at the output is biased around
VDD/2 regardless of the common- mode voltage at the
input.
•
Advantages of Fully Differential Amplifiers
• Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the
TPA6211A1, allows the inputs to be biased at
voltage other than mid-supply. For example, if a
DAC has a lower mid-supply voltage than that of
the TPA6211A1, the common-mode feedback
circuit compensates, and the outputs are still
biased at the mid-supply point of the TPA6211A1.
The inputs of the TPA6211A1 can be biased from
0.5 V to VDD - 0.8 V. If the inputs are biased
outside of that range, input coupling capacitors
are required.
APPLICATION SCHEMATICS
Figure 28 through Figure 31 show application schematics for differential and single-ended inputs. Typical
values are shown in Table 1.
Table 1. Typical Component Values
COMPONENT
VALUE
RI
40 kΩ
C(BYPASS)
(1)
1 µF
CI
0.22 µF
C(BYPASS) is optional.
4
IN−
+ RI
3
IN+
_
VO− 8
1
C(BYPASS)(1)
2
(1)
VO+ 5
+
40 kΩ
SHUTDOWN
To Battery
Cs
40 kΩ
In From
DAC
0.22 µF
CS
VDD 6
− RI
(1)
GND 7
Bias
Circuitry
100 kΩ
C(BYPASS) is optional
Figure 28. Typical Differential Input Application Schematic
13
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
VDD 6
CI
−
4
IN−
+
RI
3
IN+
CI
_
VO+ 5
VO− 8
+
40 kΩ
1
SHUTDOWN
C(BYPASS)(1)
(1)
Cs
40 kΩ
RI
To Battery
GND 7
Bias
Circuitry
100 kΩ
2
C(BYPASS) is optional
Figure 29. Differential Input Application Schematic Optimized With Input Capacitors
VDD 6
CI
IN
4
IN−
RI
3
IN+
CI
40 kΩ
SHUTDOWN
C(BYPASS)(1)
(1)
Cs
40 kΩ
RI
1
To Battery
_
VO+ 5
VO− 8
+
GND 7
Bias
Circuitry
100 kΩ
2
C(BYPASS) is optional
Figure 30. Single-Ended Input Application Schematic
14
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
CF
CF
VDD 6
Ra
−
CI
Ca
Ra
4
IN−
RI
3
IN+
CI
+
_
SHUTDOWN
C(BYPASS)(1)
VO+ 5
VO− 8
+
40 kΩ
Ca
(1)
Cs
40 kΩ
RI
To Battery
1
GND 7
Bias
Circuitry
100 kΩ
2
C(BYPASS) is optional
Figure 31. Differential Input Application Schematic With Input Bandpass Filter
Input Capacitor (CI)
Selecting Components
Resistors (RI)
The input resistor (RI) can be selected to set the gain
of the amplifier according to equation 1.
Gain = RF/RI
(1)
The internal feedback resistors (RF) are trimmed to
40 kΩ.
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second
harmonic distortion diminishes if resistor mismatch
occurs. Therefore, 1%-tolerance resistors or better
are recommended to optimize performance.
The TPA6211A1 does not require input coupling
capacitors when driven by a differential input source
biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance
or better gain-setting resistors if not using input
coupling capacitors.
In the single-ended input application, an input capacitor, CI, is required to allow the amplifier to bias the
input signal to the proper dc level. In this case, CI and
RI form a high-pass filter with the corner frequency
defined in Equation 2.
1
fc 2 R C
I I
(2)
-3 dB
Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this
device sets a mid-supply voltage for internal references and sets the output common mode voltage to
VDD/2. Adding a capacitor filters any noise into this
pin, increasing kSVR. C(BYPASS)also determines the rise
time of VO+ and VO- when the device exits shutdown.
The larger the capacitor, the slower the rise time.
fc
15
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
The value of CI is an important consideration. It
directly affects the bass (low frequency) performance
of the circuit. Consider the example where RI is 10
kΩ and the specification calls for a flat bass response
down to 100 Hz. Equation 2 is reconfigured as
Equation 3.
1
C I
2 R f c
I
(3)
In this example, CI is 0.16 µF, so the likely choice
ranges from 0.22 µF to 0.47 µF. Ceramic capacitors
are preferred because they are the best choice in
preventing leakage current. When polarized capacitors are used, the positive side of the capacitor faces
the amplifier input in most applications. The input dc
level is held at VDD/2, typically higher than the source
dc level. It is important to confirm the capacitor
polarity in the application.
Band-Pass Filter (Ra, Ca, and Ca)
It may be desirable to have signal filtering beyond the
one-pole high-pass filter formed by the combination of
CI and RI. A low-pass filter may be added by placing
a capacitor (CF) between the inputs and outputs,
forming a band-pass filter.
An example of when this technique might be used
would be in an application where the desirable
pass-band range is between 100 Hz and 10 kHz, with
a gain of 4 V/V. The following equations illustrate how
the proper values of CF and CI can be determined.
1
c(LPF)
2 R C
F F
where R is the internal 40 k resistor
F
1
f
c(LPF)
2 40 k C
F
(8)
Therefore,
1
C I
2 10 k f
c(HPF)
(9)
Substituting 100 Hz for fc(HPF) and solving for CI:
CI = 0.16 µF
At this point, a first-order band-pass filter has been
created with the low-frequency cutoff set to 100 Hz
and the high-frequency cutoff set to 10 kHz.
The process can be taken a step further by creating a
second-order high-pass filter. This is accomplished by
placing a resistor (Ra) and capacitor (Ca) in the input
path. It is important to note that Ra must be at least
10 times smaller than RI; otherwise its value has a
noticeable effect on the gain, as Ra and RI are in
series.
Step 3: Additional Low-Pass Filter
Ra must be
Set Ra = 1 kΩ
f
c(LPF)
at
least
10x
smaller
than
1
2 R a Ca
RI,
(10)
Therefore,
Ca Step 1: Low-Pass Filter
f
Substituting RI into equation 6.
1
f
c(HPF)
2 10 k C
I
1
2 1kΩ f
c(LPF)
(11)
Substituting 10 kHz for fc(LPF) and solving for Ca:
(4)
(5)
Therefore,
Ca = 160 pF
Figure 32 is a bode plot for the band-pass filter in the
previous example. Figure 31 shows how to configure
the TPA6211A1 as a band-pass filter.
AV
1
C F
2 40 k f
c(LPF)
(6)
12 dB
9 dB
Substituting 10 kHz for fc(LPF) and solving for CF:
−20 dB/dec
+20 dB/dec
CF = 398 pF
−40 dB/dec
Step 2: High-Pass Filter
1
2 R C
I I
where R is the input resistor
I
f
c(HPF)
fc(HPF) = 100 Hz
Figure 32. Bode Plot
(7)
Since the application in this case requires a gain of
4 V/V, RI must be set to 10 kΩ.
16
fc(LPF) = 10 kHz
f
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
V
Decoupling Capacitor (CS)
The TPA6211A1 is a high-performance CMOS audio
amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion
(THD) is as low as possible. Power-supply decoupling
also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher
frequency transients, spikes, or digital hash on the
line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF to 1 µF, placed as
close as possible to the device VDD lead works best.
For filtering lower frequency noise signals, a 10-µF or
greater capacitor placed near the audio power amplifier also helps, but is not required in most applications
because of the high PSRR of this device.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout
this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in
series with an ideal capacitor. The voltage drop
across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent
value of this resistance the more the real capacitor
behaves like an ideal capacitor.
DIFFERENTIAL OUTPUT VERSUS
SINGLE-ENDED OUTPUT
Figure 33 shows a Class-AB audio power amplifier
(APA) in a fully differential configuration. The
TPA6211A1 amplifier has differential outputs driving
both ends of the load. One of several potential
benefits to this configuration is power to the load. The
differential drive to the speaker means that as one
side is slewing up, the other side is slewing down,
and vice versa. This in effect doubles the voltage
swing on the load as compared to a
ground-referenced load. Plugging 2 × VO(PP) into the
power equation, where voltage is squared, yields 4×
the output power from the same supply rail and load
impedance Equation 12.
V (rms) V
Power O(PP)
2 2
2
(rms)
R
L
(12)
VDD
VO(PP)
RL
2x VO(PP)
VDD
-VO(PP)
Figure 33. Differential Output Configuration
In a typical wireless handset operating at 3.6 V,
bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 200
mW to 800 mW. This is a 6-dB improvement in sound
power—loudness that can be heard. In addition to
increased power, there are frequency-response concerns. Consider the single-supply SE configuration
shown in Figure 34. A coupling capacitor (CC) is
required to block the dc-offset voltage from the load.
This capacitor can be quite large (approximately 33
µF to 1000 µF) so it tends to be expensive, heavy,
occupy valuable PCB area, and have the additional
drawback of limiting low-frequency performance. This
frequency-limiting effect is due to the high-pass filter
network created with the speaker impedance and the
coupling capacitance. This is calculated with
Equation 13.
1
fc 2 R C
L C
(13)
For example, a 68-µF capacitor with an 8-Ω speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors.
Low-frequency performance is then limited only by
the input network and speaker response. Cost and
PCB space are also minimized by eliminating the
bulky coupling capacitor.
17
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
VDD
VO(PP)
CC
RL
VO(PP)
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the
power supply to the power delivered to the load. To
accurately calculate the RMS and average values of
power in the load and in the amplifier, the current and
voltage waveform shapes must first be understood
(see Figure 35).
VO
-3 dB
V(LRMS)
IDD
fc
Figure 34. Single-Ended Output and Frequency
Response
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the
BTL configuration produces 4× the output power of
the SE configuration.
FULLY DIFFERENTIAL AMPLIFIER
EFFICIENCY AND THERMAL INFORMATION
Class-AB amplifiers are inefficient, primarily because
of voltage drop across the output-stage transistors.
The two components of this internal voltage drop are
the headroom or dc voltage drop that varies inversely
to output power, and the sinewave nature of the
output. The total voltage drop can be calculated by
subtracting the RMS value of the output voltage from
VDD. The internal voltage drop multiplied by the
average value of the supply current, IDD(avg), determines the internal power dissipation of the amplifier.
18
IDD(avg)
Figure 35. Voltage and Current Waveforms for
BTL Amplifiers
Although the voltages and currents for SE and BTL
are sinusoidal in the load, currents from the supply
are different between SE and BTL configurations. In
an SE application the current waveform is a
half-wave rectified shape, whereas in BTL it is a
full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for
most of the waveform both the push and pull transistors are not on at the same time, which supports the
fact that each amplifier in the BTL device only draws
current from the supply for half the waveform. The
following equations are the basis for calculating
amplifier efficiency.
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
P
Efficiency of a BTL amplifier P
L
SUP
Where:
2
V rms 2
V
V
P L
, and V
P , therefore, P P
L
LRMS
L
2
R
2R
L
L
and P SUP V DD I DDavg and
I
avg 1
DD
2V
V
P
P sin(t) dt 1 P [cos(t)] 0
R
R
R
L
L
0
L
V
Therefore,
2V
P
SUP
V
DD P
R
L
substituting PL and PSUP into equation 6,
2
Efficiency of a BTL amplifier Where:
V
P
VP
2 RL
2 V DD V P
RL
VP
4 VDD
2 PL RL
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
(14)
Therefore,
BTL 2 PL RL
4V
DD
(15)
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power
Output Power
(W)
Efficiency
(%)
Internal Dissipation
(W)
Power From Supply
(W)
Max Ambient Temperature
(°C)
0.5
27.2
1.34
1.84
85 (2)
(1)
5-V, 3-Ω Systems
1
38.4
1.60
2.60
76
2.45
60.2
1.62
4.07
75
3.1
67.7
1.48
4.58
82
5-V, 4-Ω BTL Systems
0.5
31.4
1.09
1.59
85 (2)
1
44.4
1.25
2.25
85 (2)
2
62.8
1.18
3.18
85 (2)
2.8
74.3
0.97
3.77
85 (2)
0.5
44.4
0.625
1.13
85 (2)
1
62.8
0.592
1.60
85 (2)
1.36
73.3
0.496
1.86
85 (2)
1.7
81.9
0.375
2.08
85 (2)
5-V, 8-Ω Systems
(1)
(2)
DRB package
Package limited to 85°C ambient
19
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
Table 2 employs Equation 15 to calculate efficiencies
for four different output power levels. Note that the
efficiency of the amplifier is quite low for lower power
levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less
than in the half power range. Calculating the efficiency for a specific system is the key to proper
power supply design. For a 2.8-W audio system with
4-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 3.8 W.
A final point to remember about Class-AB amplifiers
is how to manipulate the terms in the efficiency
equation to the utmost advantage when possible.
Note that in Equation 15, VDD is in the denominator.
This indicates that as VDD goes down, efficiency goes
up.
A simple formula for calculating the maximum power
dissipated, PDmax, may be used for a differential
output application:
2V2
DD
P Dmax 2R L
(16)
PDmax for a 5-V, 4-Ω system is 1.27 W.
20
The maximum ambient temperature depends on the
heat sinking ability of the PCB system. The derating
factor for the 3 mm x 3 mm DRB package is shown in
the dissipation rating table. Converting this to θJA:
1
1
θ
45.9°CW
JA
0.0218
Derating Factor
(17)
Given θJA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum ambient temperature can be calculated with
Equation 18. The maximum recommended junction
temperature for the TPA6211A1 is 150°C.
T A Max T J Max θJA P Dmax
150 45.9(1.27) 91.7°C
(18)
Equation 18 shows that the maximum ambient temperature is 91.7°C (package limited to 85°C ambient)
at maximum power dissipation with a 5-V supply.
Table 2 shows that for most applications no airflow is
required to keep junction temperatures in the specified range. The TPA6211A1 is designed with thermal
protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to
the IC. In addition, using speakers with an impedance
higher than 4-Ω dramatically increases the thermal
performance by reducing the output current.
TPA6211A1
www.ti.com
SLOS367B – AUGUST 2003 – REVISED AUGUST 2004
PCB LAYOUT
Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste
should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the
package.
0.7 mm
0.33 mm plugged vias (5 places)
1.4 mm
0.38 mm
0.65 mm
1.95 mm
Solder Mask: 1.4 mm x 1.85 mm centered in package
Make solder paste a hatch pattern to fill 50%
3.3 mm
Figure 36. TPA6211A1 8-Pin QFN (DRB) Board Layout (Top View)
21
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