TI TLC2551ID

TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
D
D
D
D
D
D
Maximum Throughput . . . 400 KSPS
INL/DNL: ±1 LSB Max, SINAD: 72 dB,
fi = 20 kHz, SFDR: 85 dB, fi = 20 kHz
SPI/DSP-Compatible Serial Interfaces With
SCLK up to 20 MHz
Single 5 V Supply
Rail-to-Rail Analog Input With 500 kHz BW
Three Options Available:
– TLC2551 – Single Channel Input
PACKAGE TOP VIEW
TLC2551
CS
VREF
GND
AIN
1
8
2
7
3
6
4
5
D
D
D
– TLC2552 – Dual Channels With
Autosweep
– TLC2555 – Single Channel With
Pseudo-Differential Input
Optimized DSP Mode – Requires FS Only
Low Power With Autopower Down
– Operating Current : 3.5 mA
Autopower Down: 8 µA
Small 8-Pin MSOP and SOIC Packages
TLC2552
SDO
FS
VDD
SCLK
CS/FS
VREF
GND
AIN0
TLC2555
1
8
2
7
3
6
4
5
SDO
SCLK
VDD
AIN1
CS/FS
VREF
GND
AIN(+)
1
8
2
7
3
6
4
5
SDO
SCLK
VDD
AIN(–)
description
The TLC2551/2552/2555 are a family of high performance, 12-bit, low power, miniature 1.5 µs, CMOS
analog-to-digital converters (ADC). The TLC255x family uses a 5 V supply. Devices are available with single,
dual, or single pseudo-differential inputs. The TLC2551 has a 3-state output chip select (CS), serial output clock
(SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular
host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate
the start of a serial data frame. The TLV2552/55 have a shared CS/FS terminal.
TLC2551/2/5 are designed to operate with very low power consumption. The power saving feature is further
enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host
processors with SCLK up to 20 MHz. TLC255x family uses the SCLK as the conversion clock, thus providing
synchronous operation allowing a minimum conversion time of 1.5 µs using 20 MHz SCLK.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
8-MSOP
(DGK)
8-SOIC
(D)
TLC2551CDGK
0°C to 70°C
TLC2552CDGK
TLC2555CDGK
– 40°C to 85°C
TLC2551IDGK
TLC2551ID
TLC2552IDGK
TLC2552ID
TLC2555IDGK
TLC2555ID
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
functional block diagram
TLC2551
TLC2552
VDD
VDD
REF
REF
AIN0
AIN
LOW POWER
12-BIT
SAR ADC
S/H
Mux
AIN1
SDO
LOW POWER
SAR ADC
S/H
Conversion
Clock
SCLK
CS
FS
Conversion
Clock
CONTROL
LOGIC
CONTROL
LOGIC
SCLK
CS/FS
GND
GND
TLC2555
VDD
REF
AIN (+)
S/H
AIN (–)
LOW POWER
12-BIT
SAR ADC
Conversion
Clock
SCLK
CS/FS
CONTROL
LOGIC
GND
2
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SDO
SDO
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
Terminal Functions
TLC2551
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AIN
4
I
Analog input channel
CS
1
I
Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.
CS can be used as the FS pin when a dedicated serial port is used. If TLC2551 is attached to a dedicated DSP serial
port, this terminal can be grounded.
FS
7
I
DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK
5
I
Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO
8
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge.
The output format is MSB first.
When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge
and output data is valid on the falling edge of SCLK.
When FS is used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the falling edge of
FS or the falling edge of CS (whichever happens first). Output data is valid on the falling edge of SCLK. (This is
typically used with an active FS from a DSP).
VDD
VREF
6
I
Positive supply voltage
2
I
External reference input
TLC2552/55
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AIN0 /AIN(+)
4
I
Analog input channel 0. (positive input for TLV2555)
AIN1/AIN (–)
5
I
Analog input channel 1 (inverted input for TLV2555)
CS/FS
1
I
Chip select/frame sync. A high-to-low transition on the CS/FS removes SDO from 3-state within a maximum delay
time.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK
7
I
Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO
8
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS/FS is
high and presents output data after the CS/FS falling edge until the LSB is presented. The output format is MSB
first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.
VDD
VREF
6
I
Positive supply voltage
2
I
External reference input
detailed description
The TLC2551/2/5 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the ADC.
The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
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3
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
detailed description (continued)
Charge
Redistribution
DAC
_
AIN
Control
Logic
+
ADC Code
GND/AIN(–)
Figure 1. Simplified SAR Circuit
serial interface
OUTPUT DATA FORMAT
MSB
LSB
D15–D4
Conversion result (OD11–OD0)
D3–D0
Don’t care
The output data format is binary (unipolar straight binary).
binary
Zero scale code = 000h, Vcode = GND
Full scale code = FFFh, Vcode = VREFP – 1 LSB
pseudo-differential inputs
The TLC2555 operates in pseudo-differential mode. The inverted input is available on terminal 5. It can have
a maximum input ripple of ±0.2 V. This is normally used for ground noise rejection.
control and timing
start of the cycle
TLC2551
D
D
When FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Output
data changes on the rising edge of SCLK. This is typically used for a microcontroller with SPI interface,
although it can also be used for a DSP. The microcontroller SPI interface should be programmed for
CPOL=0 (serial clock reference to ground) and CPHA=1 (data is valid on the falling edge of serial clock).
When FS is used ( FS is an active signal from a DSP), the falling edge of FS is the start of the cycle. Output
data changes on the rising edge of SCLK. This is typically used for a TMS320 DSP. If the TLC2551 is
attached to a dedicated DSP serial port. CS terminal can be grounded.
TLC2552/5
The CS and FS inputs are accessed via the same pin (pin 1) on the TLC2552 and TLC2555. The cycle is started
by the falling edge transition provided by either a CS (interfacing with a SPI interface microcontroller) signal or
FS (interfacing with a TMS320 DSP) signal. Timing for the TLC2555 is much like the TLC2551, with the
exception of the CS/FS line.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
detailed description (continued)
TLC2552 channel MUX reset cycle
The TLC2552 uses CS/FS to reset the AIN multiplexer. A short active CS/FS cycle (4–7 SCLKs) resets the MUX
to AIN0. If the CS/FS cycle is sufficient to complete the conversion (16 SCLKs plus maximum conversion time),
the MUX toggles to the next channel (see Figure 4 for timing).
sampling
The converter sample time is 12 SCLKs beginning on the 5th SCLK received after the converter has received
an active CS or FS signal (CS/FS for the TLC2552/5).
conversion
The TLC2551 completes conversion in the following manner. The conversion is started after the 16th SCLK
edge. The conversion takes 1.4 µs using 20 MHz SCLK plus 0.1 µs overhead. Enough time (for conversion)
should be allowed before a rising CS/FS edge so that no conversion is terminated prematurely.
TLC2552 input channel selection is toggled on each rising CS /FS edge. The MUX channel can be reset to AIN0
via CS /FS as described in the earlier section and in Figure 5. The input is sampled for 12 SCLKs, converted,
and the result is presented on SDO during the next cycle. Care should also be taken to allow enough time
between samples to avoid prematurely terminating the conversion, which occurs on a rising CS /FS transition
if the conversion is not complete.
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5
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
timing diagrams/conversion cycles
DSP Interface
1
2
3
4
5
6
12
13
14
15
16
1
SCLK
CS
FS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
t(sample)
SDO
OD11
OD10
OD9
OD8
OD7
OD6
t(powerdown)
tc
OD0
Figure 2. TLC2551 DSP Mode/FS Active
µP Interface
1
2
3
4
5
6
7
12
13
14
15
16
1
SCLK
CS
FS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
t(sample)
SDO
OD11
OD10
OD9
OD8
OD7
OD6
OD5
t(powerdown)
tc
OD0
Figure 3. TLC2551 Microcontroller Mode/(SPI, CPOL = 0, CPHA = 1)
1
2
3
4
5
1
4
12
16
1
4
12
16
SCLK
CS/FS
>8 SCLKs, MUX Toggles to AIN1
<8 SCLKs, MUX
Resets to AIN0
t(powerdown)
t(sample)
t(sample)
SDO
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
tc
Figure 4. TLC2552 Timing
6
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AIN0 Result
OD11
ÎÎÎ
ÎÎÎ
OD0
tc
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
timing diagrams/conversion cycles (continued)
1
2
3
4
5
6
7
12
13
14
15
16
1
SCLK
CS/FS
t(sample)
SDO
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD0
ÎÎÎÎÎ
ÎÎÎÎÎ
tc
t(powerdown)
OD11
OD10
OD9
Figure 5. TLC2555 Timing
use CS as FS input
When interfacing the TLC2551 with the TMS320 DSP, the FSR signal from the DSP may be connected to the
CS input if this is the only device on the serial port. This will save one output terminal from the DSP. (Output data
changes on the falling edge of SCLK. Default for TLC2552 and TLC2555).
SCLK and conversion speed
It takes 14 conversion clocks to complete the conversion. The conversion clock for the TLC2551/2/5 is equal
to SCLK/2. This yields a minimum conversion time of 1.4 µs plus 0.1 µs overhead. These devices can operate
with an SCLK up to 20 MHz for the supply voltage range specified. The total conversion time is 14× (1/10M)
+16× (1/20M)+ 0.1 µs} = 2.3 µs for a 20 MHz SCLK. This is the minimum cycle time for an active CS or CS/FS
signal. If violated, the conversion will terminate, invalidating the next data output cycle.
reference voltage
An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of
the analog inputs to produce a full-scale reading. The value of VREF and the analog input should not exceed
the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital
output is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal
is equal to or lower than GND.
powerdown and powerup initialization
Autopower down is built in to the devices in order to reduce power consumption. The wake-up time is fast
enough to provide power down between each cycle. The power-down state is initiated at the end of conversion
and wakes up upon a falling edge on CS or FS.
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7
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, GND to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD+ 0.3 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating free-air temperature range, TA: C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, VDD
MIN
NOM
MAX
2.7
3.3
5.5
V
VDD
VDD
V
Positive external reference voltage input, VREFP (see Note 1)
2
Analog input voltage (see Note 1)
0
High level control input voltage, VIH
2.1
Low-level control input voltage, VIL
VDD = REF = 5.5 V
Hold time, CS rising edge after SCLK falling edge, th(SCLKL-CSH)
40
0.5
Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL)
0.35
Hold time, FS hold high after SCLK falling edge, th(SCLKL-FSL)
V
ns
5
Delay time, delay from CS falling edge to FS rising edge (td(CSL-FSH)
V
V
0.6
Setup time, CS falling edge (for 2551) or CS/FS falling edge (for
2552/55) before first SCLK falling edge, tsu(CSL-SCLKL)
UNIT
ns
7
SCLKs
SCLKs
0.65
SCLKs
Pulse width CS high time, twH(CS)
100
ns
Pulse width FS high time, twH(FS)
0.75
SCLKs
SCLK cycle time, VDD = 5.5–4.5 V, tc(SCLK)
50
10000
Pulse width low time, twL(SCLK)
0.4
0.6
SCLKs
Pulse width high time, twH(SCLK)
0.4
0.6
SCLKs
Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of
conversion time, tc)
0.1
Active CS/FS cycle time to reset internal MUX to AIN0, reset cycle
Operating
O
erating free-air tem
temperature
erature, TA
ns
µs
TLC2552 only
4
7
SCLKs
TLC2551/2/5C
0
70
–40
85
°C
TLC2551/2/5I
NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that
applied to GND convert as all zeros(000000000000).
2. This is the time required for the clock input signal to fall from VIH max or to rise from VILmax to VIHmin. In the vicinity of normal room
temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where the
sensor and A/D converter are placed several feet away from the controlling microprocessor.
8
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TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
electrical characteristics over recommended operating free-air temperature range,
VDD = VREF = 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VOH
High-level output voltage
VDD = 5.5 V, IOH = –0.2 mA at 30 pF load
VOL
Low-level output voltage
VDD = 5.5 V, IOL = 0.8 mA at 30 pF load
IOZ
O
Off-state output current
(high-impedance-state)
VO = VDD
IIH
High-level input current
VI = VDD
IIL
Low-level input current
VI = 0 V
ICC
Operating supply current
CS at 0 V,
Autopower-down current (0.5 µs inactive)
For all digital inputs,
0≤ VI ≤ 0
0.3
3 V or VI ≥ VDD– 0
0.3
3V
V,
SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref
8
Selected channel at VDD
1
ICC(AUTOPWDN)
CC(
O
)
Selected analog
g input channel leakage
g
current
VDD = 4.5 V ~ 5.5 V
Input capacitance
1
2.5
–1
–2.5
V
µA
0.005
2.5
µA
–0.005
2.5
µA
3
3.5
mA
µA
1
Selected channel at 0 V
Analog inputs
Ci
UNIT
V
0.4
CS = VDD
VO = 0
Autopower-down current (5 µs inactive)
2.4
–1
20
Control Inputs
45
50
5
25
µA
pF
500
Ω
VDD = REF = 5.5 V, 30 pF
40
ns
Delay time, delay from FS falling edge to
SDO valid, td(FSL-SDOV)
VDD = REF = 5.5 V, 30 pF
1
ns
Delay time, delay from SCLK rising edge
to SDO valid, td(SCLKH-SDOV)
VDD = REF = 5.5 V, 30 pF
11
ns
Delay time, delay from 17th SCLK rising
edge to SDO 3-state, td(SCLK17H-SDOZ)
VDD = REF = 5.5 V, 30 pF
30
ns
tc
Conversion time
Conversion clock = internal oscillator
t(sample)
Sampling time
See Note 3
Action time
ICC start to decrease
Wakeup time
ICC down to MIN [ICC(AUTOPWDN)]
Autopower down
Input on resistance
VDD = 5.5 V
Delay time, delay from CS falling edge to
SDO valid, td(CSL-SDOV)
28
SCLK
300
Autopower down
ns
0.5
1
0.5
SCLK
2
ms
SCLK
† All typical values are at VDD = 5 V, TA = 25°C.
NOTE 3: Minimal t(sample) is given by 0.9 × 50 pF × (RS + 0.5 kΩ), where RS is the source output impedance.
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9
TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
ac specifications (fi = 20 kHz)
PARAMETER
SINAD
Signal-to-noise ratio + distortion
THD
Total harmonic distortion
ENOB
Effective number of bits
SFDR
Spurious free dynamic range
TEST CONDITIONS
400 KSPS, VDD = VREF = 5 V
400 KSPS, VDD = VREF = 5 V
MIN
TYP
70
72
–84
400 KSPS, VDD = VREF = 5 V
400 KSPS, VDD = VREF = 5 V
MAX
dB
–80
11.8
–84
UNIT
dB
Bits
–80
dB
Analog Input
Full power bandwidth, –3 dB
1
MHz
Full-power bandwidth, –1 dB
500
kHz
external reference specifications
PARAMETER
Reference input voltage
VREF
TEST CONDITIONS
MIN
TYP
VDD = =4.5 V ~ 5.5 V
Reference input impedance
5V
VDD = 5
5.5
Reference current
VDD = VREF = 5.5 V
Reference input capacitance
VDD = VREF = 5
5.5
5V
Reference voltage
VDD = =4.5 V – 5.5 V
MAX
VDD
CS = 1,
SCLK = 0
CS = 0,
SCLK = 20 MHz
100
20
SCLK = 0
CS = 0,
SCLK = 20 MHz
25
5
20
V
MΩ
100
CS = 1,
UNIT
kΩ
400
15
45
50
VDD
µA
pF
V
dc specification, VDD = VREF = 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)
PARAMETER
INL
Integral linearity error (see Note 5)
DNL
Differential linearity error
TEST CONDITIONS
Offset error (see Note 6)
See Note 4
EG
Gain error (see Note 6)
See Note 4
Et
Total unadjusted error (see Note 7)
See Note 4
NOM
MAX
UNIT
±0.6
±1
LSB
±1
LSB
±0.5
See Note 4
EO
MIN
TLC2551/52
±1.5
TLC2555
±2.5
TLC2551/52
±2
TLC2555
±5
TLC2551/52
±2
TLC2555
±5
LSB
LSB
LSB
NOTES: 4. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that
applied to REFM convert as all zeros (0000000000).
5. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage.
7. Total unadjusted error comprises linearity, zero, and full-scale errors.
10
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TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
PARAMETER MEASUREMENT INFORMATION
t(sample)
tc
twH(SCLK)
VIH
1
2
4
12
16
SCLK
VIL
twL(SCLK)
tsu(CSL-SCLKL)
t(powerdown)
CS
th(SCLKL-FSL)
tWH(CS)
tsu(FSH-SCLKL)
th(EOC-CSH)
td(CSL-FSH)
td(SCLKH-SDOV)
FS
SDO
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
twh(FS)
OD11
OD8
td(SCLK17H-SDOZ)
OD0
td(CSL-SDOV)
Figure 6. Critical Timing TLC2551 (FS is active)
t(sample)
tsu(CSL–SCLKL)
1
2
tc
4
12
16
SCLK
t(powerdown)
CS
td(SCLKH-SDOV)
SDO
OD11
OD10
OD9
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
td(SCLK17H-SDOZ)
OD0
th(EOC–CSH)
td(CSL-SDOV)
Figure 7. Critical Timing TLC2551 (FS = 1)
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SLAS276 –MARCH 2000
PARAMETER MEASUREMENT INFORMATION
t(sample)
tc
1
1
4
12
16
SCLK
t(Reset Cycle)
MUX = AIN0
CS/FS
ÎÎÎÎ
ÎÎÎÎ
SDO
th(EOC-CSH)
td(CSLKH-SDOV)
td(CSL-SDOV)
ÎÎÎÎÎ
ÎÎÎÎÎ
OD11
OD0
td(CSL-SDOV)
OD11
td(SCLK17H-SDOZ)
Figure 8. Critical Timing TLC2552 Reset Cycle
t(sample)
twH(SCLK)
VIH
1
2
4
12
tc
16
SCLK
VIL
twL(SCLK)
th(SCLKL-FSL)
tsu(FSH-SCLKL)
t(powerdown)
CS/FS
th(EOC-CSH)
td(SCLKH-SDOV)
twh(FS)
SDO
OD11
OD8
td(CSL-SDOV)
ÎÎÎÎÎ
ÎÎÎÎÎ
td(SCLK17H-SDOZ)
OD0
Figure 9. Critical Timing TLC2555 Power-Down Cycle
12
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SLAS276 –MARCH 2000
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs
TEMPERATURE
0.7
0.4
DNL – Differential Nonlinearity – LSB
INL – Integral Nonlinearity – LSB
VDD = REF = 5.5 V
400 KSPS
0.65
0.6
–40
25
VDD = REF = 5.5 V
400 KSPS
0.35
0.3
–40
90
t – Temperature – °C
25
t – Temperature – °C
Figure 10
90
Figure 11
OFFSET ERROR
vs
TEMPERATURE
GAIN ERROR
vs
TEMPERATURE
0.5
0.9
VDD = REF = 5.5 V
400 KSPS
VDD = REF = 5.5 V
400 KSPS
Gain Error – LSB
Offset Error – LSB
0.85
0.45
0.8
0.75
0.4
–40
25
t – Temperature – °C
90
0.7
–40
25
90
t – Temperature – °C
Figure 12
Figure 13
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5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
3.1
Supply Current – mA
VDD = REF = 5.5 V
400 KSPS
3.05
3
–40
25
t – Temperature – °C
90
Figure 14
DNL – Differential Nonlinearity –LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODES
1
VDD = REF = 5 V
400 KSPS
0.5
0
–0.5
–1
4094
1
Digital Output Codes
Figure 15
14
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5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
TYPICAL CHARACTERISTICS
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODES
1
VDD = REF = 5 V
400 KSPS
0.5
0
–0.5
–1
4094
1
Digital Output Codes
Figure 16
2048 POINTS FAST FOURIER TRANSFORM (FFT)
0
VDD = REF = 5.5 V
400 KSPS
fi = 20 kHz
Magnitude – dB
–20
–40
–60
–80
–100
–120
–140
–160
0
20
40
60
80
100
120
140
160
180
200
f – Input Frequency – KHz
Figure 17
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SLAS276 –MARCH 2000
TYPICAL CHARACTERISTICS
ENOB
vs
FREQUENCY
SINAD
vs
FREQUENCY
12
75
VDD = REF = 5.5 V
400 KSPS
VDD = REF = 5.5 V
400 KSPS
73
ENOB – Bits
SINAD – dB
11.5
71
69
11
10.5
67
10
65
0
20
40
60
80
0
100 120 140 160 180 200
20
40
60
Figure 18
–65
VDD = REF = 5.5 V
400 KSPS
–70
THD – dB
100 120 140 160 180 200
Figure 19
THD
vs
FREQUENCY
–75
–80
–85
–90
0
20
40
60
80
100 120 140 160 180 200
f – Input Frequency – KHz
Figure 20
16
80
f – Input Frequency – KHz
f – Input Frequency – KHz
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SLAS276 –MARCH 2000
TYPICAL CHARACTERISTICS
4095
111111111111
VFS
See Notes A and B
111111111110
4094
111111111101
4093
VFT = VFS – 1/2 LSB
100000000001
2049
2048
100000000000
VZT =VZS + 1/2 LSB
Step
Digital Output Code
VFS Nom
2047
011111111111
VZS
000000000001
1
000000000000
0
0.0012
0.0024
2.4564
2.4576
2.4588
4.9128
4.9134
2
0.0006
000000000010
4.9140
0
4.9152
VI – Analog Input Voltage – V
NOTES: A. This curve is based on the assumption that Vref+ and Vref– have been adjusted so that the voltage at the transition from digital 0 to
1 (VZT) is 0.0006 V, and the transition to full scale (VFT) is 4.9134 V, 1 LSB = 1.2 mV.
B. The full scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 21. Ideal 12-Bit ADC Conversion Characteristics
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5 V, LOW POWER, 12-BIT, 400 KSPS,
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SLAS276 –MARCH 2000
APPLICATION INFORMATION
VDD
10 kΩ
VDD
XF
RXD
SCLK
TMS320 DSP
EXT
Reference
10 kΩ
FS
SDO
SCLK
VREF
TLC2551
CS
Ain
GND
VDD
10 kΩ
VDD
CS/FSD
VREF
SDO
SCLK
XF
RXD
SCLK
TMS320 DSP
EXT
Reference
10 kΩ
TLC2552/55
GND
AIN 0/AIN (+)†
AIN 1/AIN (–)†
† For TLC2555 only
Figure 22. Typical Interface to a TMS320 DSP
simplified analog input analysis
Using the equivalent circuit in Figure 23, the time required to charge the analog input capacitance from 0 to Vs
within 1/2 LSB can be derived as follows.
ǒ ǒ ǓǓ
The capacitance charging voltage is given by:
Vc
+ Vs
1–EXP
–tch
Rt Ci
(1)
Where:
Rt = Rs + Zi
tch = Charge time
The input impedance Zi is 0.5 kΩ at 5 V, and is higher (~ 0.6 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:
ń
Vc (1 2 LSB)
18
+ Vs–
ǒ Ǔ
Vs
8192
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SLAS276 –MARCH 2000
APPLICATION INFORMATION
simplified analog input analysis (continued)
ǒ Ǔ + ǒ ǒ ǓǓ
Equating equation 1 to equation 2 and solving for cycle time tc gives:
Vs–
VS
8192
Vs
1–EXP
–tch
Rt Ci
(3)
and time to change to 1/2 LSB (equal to minimum sampling time) is:
ń
tch (1 2 LSB)
Where:
+ Rt
Ci
In(8192)
+ Min[t(sample)]
In(8192) = 9.011
Therefore, with the values given, the time for the analog input signal to settle is:
ń
tch (1 2 LSB)
+ (Rs ) 0.5 kW)
Ci
(4)
In(8192)
ƪ
ƫ ǒ Ǔ
This time must be less than the converter sample time shown in the timing diagrams. This is 12× SCLKs.
t (sample)
+ 12
w Min t(sample) + tch
1
f (SCLK)
ƪ ǒ Ǔƫ +
1 LSB
2
(5)
Therefore the maximum SCLK frequency is:
max f
SCLK
Ǔ + [In(8192)12 Rt
ǒń
12
tch 1 2 LSB
(6)
Ci ]
maximum conversion throughput
ǒ Ǔ
ǒ Ǔ
For a supply voltage of 5 V, if the source impedance is less than 1 kΩ, and the ADC analog input capacitance
Ci is less than 50 pF, this equates to a minimum sampling time tch 1 LSB of 0.676 µs ( 1 µs). Since the
2
sampling time requires 12 SCLKs, the fastest SCLK frequency is 12 tch 1 LSB = 12 MHz for Rs ≤ 1 kΩ.
2
The minimal total cycle time, t(cycle), is given as:
t (cycle)
+ t(sample) ) tc ) t(overhead) + Max ƪf16(SCLK) ƫ ) f [(SCLK14)]
0.5
t
) 0.1 ms + 3.77 ms
This is equivalent to a maximum throughput, max[fs] of 265 KSPS.
The throughput can be even higher with a smaller source impedance. When source impedance is 100 Ω, the
minimum sampling time becomes:
ń
tch (1 2 LSB)
+ Rt
Ci
In(8192)
+ 0.27 ms
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APPLICATION INFORMATION
maximum conversion throughput (continued)
ǒ Ǔ
The maximum SCLK frequency possible is 12/tch 1 LSB = 44 MHz. Then a 20 MHz clock (maximum SCLK
2
frequency allowed for the internal comparator can be used. The minimal total cycle time is then reduced to:
t (cycle)
+ t(sample) ) tc ) toverhead + max ƪf16(SCLK) ƫ ) max ƪf (16
) 0.1 ms + 2.3 ms
SCLK) ƫń2
The maximum throughput, MAX[fs], is 1/2.3 µs = 134 KSPS for this case.
Driving Source Requirements:
Driving Source
RS
VS
Data Converter
Vi
ri
VC
+
_
ts AMP
Ci
VI = Input Voltage at AIN
VS= External Driving Source Voltage
RS= Source Resistance
ri = Input Resistance (Mux On Resistance)
Ci = Input Capacitance
VC = Capacitance Charging Voltage
NOTE: Noise and distortion must for the source be equivalent to the resolution of the converter.
Rs must be real at the input frequency.
Figure 23. Equivalent Input Circuit Including the Driving Source
power down calculations
Total power consumption at different conversion rate fs, (fs ≤ MAX [fs]) can be calculated by:
VDD × i(AVERAGE) = VDD [(fS/MAX [fs]) × i(ON) + (1–fs/MAX [fs]) × i(OFF)]
If VDD = 5 V for TLC2551, and the sampling rate fs = 10 kHz, the maximum sampling rate fSMAX = 200 kHz
then i(ON) = ~3.5 mA operating current
and i(OFF) = ~8 µA auto-powerdown current
so VDD × i(AVERAGE) = 5 × (0.05 × 3500 µA + 0.95 × 8 µA)
= (5 × 182.6) µW
= 0.9 mW
20
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SLAS276 –MARCH 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°– 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073329/B 04/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-187
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SLAS276 –MARCH 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
22
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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