PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 SINGLE-ENDED ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER FEATURES D 24-Bit Delta-Sigma Stereo A/D Converter D Single-Ended Voltage Input: 3 V p-p D Antialiasing Filter Included D Oversampling Decimation Filter Oversampling Frequency: ×64, ×128 Passband Ripple: ±0.05 dB Stopband Attenuation: –65 dB On-Chip HPF (Low Cut Filter): 0.84 Hz (44.1 kHz) High Performance – THD+N: 96 dB (Typical) – SNR: 105 dB (Typical) – Dynamic Range: 105 dB (Typical) PCM Audio Interface – Master/Slave Mode Selectable – Data Formats: 24-Bit Left-Justified; 24-Bit I2S; 20-, 24-Bit Right-Justified Sampling Rate: 16 kHz to 96 kHz System Clock: 256 fS, 384 fS, 512 fS, 768 fS Dual Power Supplies: 5 V for Analog, 3.3 V for Digital Package: 20-Pin SSOP Lead-Free Product – – – – D D D D D D D APPLICATIONS D AV Amp Receiver D MD Player D CD Recorder D Multitrack Receiver D Electric Musical Instrument DESCRIPTION The PCM1802 is a high-performance, low-cost, single-chip stereo analog-to-digital converter with single-ended analog voltage input. The PCM1802 uses a delta-sigma modulator with 64- or 128-times oversampling, and includes a digital decimation filter and HPF (low cut filter) which removes the dc component of the input signal. For various applications, the PCM1802 supports master and slave modes and four data formats in serial interface. The PCM1802 is suitable for a wide variety of cost-sensitive consumer applications where good performance, 5-V analog supply, and 3.3-V digital supply operation is required. The PCM1802 is fabricated using a highly advanced CMOS process and is available in the DB 20-pin SSOP package. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Audio Precision and System Two are trademarks of Audio Precision. Other trademarks are the property of their respective owners. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM1802DB 20 Lead SSOP 20-Lead 20DB –40°C 40°C to 85°C PCM1802 ORDERING NUMBER TRANSPORT MEDIA PCM1802DB Tube PCM1802DBR Tape and reel pin assignments PCM1802 (TOP VIEW) VINL VINR VREF1 VREF2 VCC AGND PDWN BYPAS FSYNC LRCK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 MODE1 MODE0 FMT1 FMT0 OSR SCKI VDD DGND DOUT BCK block diagram VINL Single-End /Differential Converter 5th Order Delta-Sigma Modulator BCK LRCK ×1/64 (×1/128) Decimation Filter with DC Cut Filter VREF1 Reference VREF2 VINR Single-End /Differential Converter Serial Interface FSYNC DOUT Mode/ Format Control 5th Order Delta-Sigma Modulator FMT0 FMT1 MODE0 MODE1 BYPAS Clock and Timing Control Power Supply OSR PDWN SCKI VCC 2 AGND DGND VDD www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 Terminal Functions TERMINAL NAME PIN I/O AGND 6 – BCK 11 I/O DESCRIPTIONS Analog GND Bit clock input/output‡ BYPAS 8 I HPF bypass control. Low: normal mode (dc cut); High: bypass mode (through)† DGND 13 – Digital GND DOUT 12 O Audio data output FMT0 17 I FMT1 18 I Audio data format select 0. See data format† Audio data format select 1. See data format† FSYNC 9 I/O LRCK 10 I/O MODE0 19 I MODE1 20 I OSR 16 I PDWN 7 I SCKI 15 I VCC VDD 5 – System clock input; 256 fS, 384 fS, 512 fS or 768 fS§ Analog power supply, 5 V 14 – Digital power supply, 3.3 V 1 I Analog input, L-channel 2 I Analog input, R-channel VINL VINR Frame synchronous clock input/output‡ Sampling clock input/output‡ Mode select 0. See interface mode† Mode select 1. See interface mode† Oversampling ratio select. Low: ×64 fS; High: ×128 fS† Power-down control, active low† VREF1 3 – Reference 1 decoupling capacitor VREF2 4 – Reference 2 voltage input, normally connected to VCC † Schmitt-trigger input with internal pulldown (50 kΩ typically), 5-V tolerant ‡ Schmitt-trigger input § Schmitt-trigger input, 5-V tolerant absolute maximum ratings over operating free-air temperature (unless otherwise noted)¶ VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Ground voltage differences: AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Digital input voltage: FSYNC, LRCK, BCK, DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V) PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 . . . . . . . . . . . . –0.3 V to 6.5 V Analog input voltage: VINL, VINR, VREF1, VREF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V) Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 s Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Supply voltage: ¶ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. www.ti.com 3 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, over sampling ratio = ×128, 24-bit data (unless otherwise noted) PCM1802DB TEST CONDITIONS MIN TYP Resolution MAX 24 UNIT bits DATA FORMAT Left justified, I2S, right justified Audio data interface format Audio data bit length 20, 24 Audio data format fS Sampling frequency System clock frequency bits MSB first, 2s complement 16 44.1 96 256 fS 4.096 11.2896 24.576 384 fS 6.144 16.9344 36.864 512 fS 8.192 22.5792 49.152 768 fS 12.288 33.8688 kHz MHz INPUT LOGIC VIH VIL See Note 1 VIH VIL See Note 2 IIH IIL IIH IIL 2 Input logic level 0 VDD 0.8 2 5.5 0 See Note 3 Input logic current See Note 4 VDC 0.8 ±10 VIN = VDD VIN = 0 V ±10 VIN = VDD VIN = 0 V 65 100 µA A ±10 OUTPUT LOGIC VOH VOL See Note 5 Output logic level IOUT = –1 mA IOUT = 1 mA 2.8 0.5 VDC DC ACCURACY Gain mismatch channel-to-channel ±1 ±4 %FSR Gain error ±2 ±6 %FSR Bipolar zero error LCF bypass (see Note 6) NOTES: 1. 2. 3. 4. ±2 %FSR Pins 9–11: FSYNC, LRCK, BCK (Schmitt-trigger input, in slave mode) Pins 7–8, 15–20: PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, 5-V tolerant). Pins 9–11, 15: FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode), SCKI (Schmitt-trigger input). Pins 7–8, 16–20: PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-kΩ typical pulldown resistor). 5. Pins 9–12: FSYNC, LRCK, BCK (in master mode), DOUT 6. Low cut filter 4 www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, over sampling ratio = ×128, 24-bit data (unless otherwise noted) (continued) PCM1802DB TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE (see Note 7) fS = 44.1 kHz fS = 96 kHz (see Note 8) 0.0015% THD+N (VIN = –0.5 0 5 dB) fS = 44.1 kHz fS = 96 kHz (see Note 8) 0.7% THD N (VIN = –60 THD+N 60 dB) fS = 44.1 kHz, A-weighted fS = 96 kHz, A-weighted (see Note 8) 100 Dynamic range fS = 44.1 kHz, A-weighted fS = 96 kHz, A-weighted (see Note 8) 100 S/N ratio Channel separation fS = 44.1 kHz fS = 96 kHz (see Note 8) 0.003% 0.0025% 1.2% 105 dB 103 105 dB 103 96 103 dB 98 ANALOG INPUT Input voltage 0.6 VCC Center voltage (VREF1) 0.5 VCC V 20 kΩ 300 kHz Input impedance Antialiasing filter frequency response –3 dB Vp–p DIGITAL FILTER PERFORMANCE Passband 0.454 fS Stopband 0.583 fS Hz ±0.05 Passband ripple Stopband attenuation –65 Delay time HPF frequency response dB dB 17.4/fS 0.019 fS –3 dB Hz s mHz POWER SUPPLY REQUIREMENTS VCC VDD Voltage range ICC IDD PD Supply current (see Note 9) 4.5 5 5.5 2.7 3.3 3.6 24 30 8.3 10 VCC = 5 V, VDD = 3.3 V fS = 44.1 kHz VCC = 5 V, VDD = 3.3 V fS = 96 kHz, Note 8) VCC = 5 V, VDD = 3.3 V (see VDC mA 17 fS = 44.1 kHz, VCC = 5 V, VDD = 3.3 V fS = 96 kHz, VCC = 5 V, VDD = 3.3 V (see Note 8) 147 Power dissipation; operation Power dissipation; power down VCC = 5 V, VDD = 3.3 V 0.5 183 mW 176 mW TEMPERATURE RANGE Operation temperature –40 85 _C Thermal resistance (θJA) 20-pin SSOP 115 °C/W NOTES: 7. Analog performance specs are tested with System Two audio measurement system by Audio Precision, using 400-Hz HPF, 20-kHz LPF at 44.1-kHz operation, 40-kHz LPF at 96-kHz operation in RMS mode. 8. fS = 96 kHz, system clock = 256 fS, oversampling ratio = ×64. 9. Minimum load on DOUT (pin 12), BCK (pin 11), LRCK (pin 10), FSYNC (pin 9). www.ti.com 5 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER digital filter—decimation filter frequency response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 50 50 Oversampling Ratio = x64 Oversampling Ratio = x128 0 Amplitude – dB Amplitude – dB 0 –50 –100 –50 –100 –150 –150 –200 –200 0 8 16 24 32 40 48 56 0 64 8 16 24 32 Frequency [× fS] Frequency [× fS] Figure 1. Overall Characteristics Figure 2. Overall Characteristics AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.2 –10 –0.0 –20 Amplitude – dB Amplitude – dB –30 –40 –50 –60 –70 –0.2 –0.4 –0.6 –80 –0.8 –90 Oversampling Ratio = x128 and x64 –100 0.00 0.25 Oversampling Ratio = x128 and x64 0.50 0.75 1.00 Frequency [× fS] –1.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [× fS] Figure 3. Stopband Attenuation Characteristics Figure 4. Passband Ripple Characteristics All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted. 6 www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER HPF (low cut filter) frequency response AMPLITUDE vs FREQUENCY 0 AMPLITUDE vs FREQUENCY 0.2 –10 –0.0 –20 Amplitude – dB Amplitude – dB –30 –40 –50 –60 –70 –0.2 –0.4 –0.6 –80 –0.8 –90 –100 0.0 0.1 0.2 0.3 –1.0 0.4 0 1 Frequency [× fS/1000] 2 3 4 Frequency [× fS/1000] Figure 5. LCF Stopband Characteristics Figure 6. LCF Passband Characteristics analog filter—antialiasing filter frequence response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 –0.0 –0.1 –5 –0.2 –10 –0.3 Amplitude – dB Amplitude – dB –15 –20 –25 –30 –0.5 –0.6 –0.7 –35 –0.8 –40 –0.9 –45 –50 100 –0.4 –1.0 1k 10k 100k 1M 1 10M 10 100 1k 10k 100k f – Frequency – Hz f – Frequency – Hz Figure 7. Antialias Filter Stopband Characteristics Figure 8. Antialias Filter Passband Characteristics All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted. www.ti.com 7 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 TYPICAL PERFORMANCE CURVES TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE and SNR vs FREE-AIR TEMPERATURE 110 109 Dynamic Range and SNR – dB THD+N – Total Harmonic Distortion + Noise – % 0.04 0.004 0.03 0.003 0.02 0.002 108 107 Dynamic Range 106 105 SNR 104 103 102 101 0.01 0.001 –50 –25 0 25 50 75 100 –50 100 TA – Free-Air Temperature – °C –25 Figure 9 25 50 75 100 Figure 10 TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 0.04 0.004 110 109 Dynamic Range and SNR – dB THD+N – Total Harmonic Distortion + Noise – % 0 TA – Free-Air Temperature – °C 0.03 0.003 0.02 0.002 108 107 Dynamic Range 106 105 SNR 104 103 102 101 0.01 0.001 4.25 4.50 4.75 5.00 5.25 5.50 5.75 VCC – Supply Voltage – V 100 4.25 4.50 4.75 5.00 5.25 5.50 5.75 VCC – Supply Voltage – V Figure 11 Figure 12 All specifications at TA = 25°C, VCC = 5.0 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted. 8 www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 TYPICAL PERFORMANCE CURVES TOTAL HARMONIC DISTORTION + NOISE vs fSAMPLE CONDITION DYNAMIC RANGE and SNR vs fSAMPLE CONDITION 110 †fS = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. ‡fS = 96 kHz, System Clock = 256 fS, Oversampling Ratio = ×64. †fS = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. ‡fS = 96 kHz, System Clock = 256 fS, Oversampling Ratio = ×64. 109 Dynamic Range and SNR – dB THD+N – Total Harmonic Distortion + Noise – % 0.04 0.004 0.03 0.003 0.02 0.002 108 107 Dynamic Range 106 105 SNR 104 103 102 101 0.01 0.001 0 10 44.1 20† 48 30‡ 96 100 40 0 10 44.1 fSAMPLE Condition – kHz 20† 48 30‡ 96 40 fSAMPLE Condition – kHz Figure 13 Figure 14 output spectrum AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 Input Level = –60 dB Data Points = 8192 –20 –20 –40 –40 Amplitude – dB Amplitude – dB Input Level = –0.5 dB Data Points = 8192 –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 20 f – Frequency – kHz 0 5 10 15 20 f – Frequency – kHz Figure 15 Figure 16 All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted. www.ti.com 9 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 TYPICAL PERFORMANCE CURVES TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL THD+N – Total Harmonic Distortion + Noise – % 100 10 1 0.1 0.01 0.001 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 Signal Level – dB Figure 17 supply current SUPPLY CURRENT vs fSAMPLE CONDITION ICC and IDD – Supply Current – mA 30 ICC 25 20 15 IDD 10 †fS = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. ‡fS = 96 kHz, System Clock = 256 fS, Oversampling Ratio = ×64. 5 0 0 10 44.1 20† 48 30‡ 96 40 fSAMPLE Condition – kHz Figure 18 All specifications at TA = +25°C, VCC = 5 V, VDD = 3.3 V, Master Mode, fS = 44.1 kHz, system clock = 384fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted. 10 www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION PCM1802 consists of a reference circuit, two channels of single-ended-to-differential converter, fifth-order delta-sigma modulator with full differential architecture, decimation filter with low cut filter, and a serial interface circuit. Figure 19 illustrates the total architecture of PCM1802, Figure 20 illustrates the architecture of single-ended-to-differential converter and antialiasing filter, and Figure 21 illustrates the block diagram of fifth-order delta-sigma modulator and transfer function. An on-chip high-precision reference with one external capacitor provides all reference voltages that are needed in the PCM1802, and defines the full scale voltage range for both channels. On-chip single-ended-to-differential signal converters save the design, space, and extra parts cost for external signal converters. Full differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at a ×64 or ×128 oversampling rate, thus eliminating an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using the switched capacitor technique and a comparator, shapes the quantization noise generated by the comparator and 1-bit DAC outside of the audio signal band. The high-order delta-sigma modulation randomizes the modulator outputs and reduces the idle tone level. The 64-fS or 128-fS, 1-bit stream from the delta-sigma modulator is converted to a 1-fS, 24-bit or 20-bit digital signal by removing high-frequency noise components with a decimation filter. The dc component of the signal is removed by the LCF, and the LCF output is converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial formats. VINL Single-End /Differential Converter 5th Order Delta-Sigma Modulator BCK LRCK ×1/64 (×1/128) Decimation Filter with DC Cut Filter VREF1 Reference VREF2 VINR Single-End /Differential Converter Serial Interface FSYNC DOUT Mode/ Format Control 5th Order Delta-Sigma Modulator FMT0 FMT1 MODE0 MODE1 BYPAS Clock and Timing Control Power Supply OSR PDWN SCKI VCC AGND DGND VDD Figure 19. Block Diagram www.ti.com 11 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION 1 µF 20 kΩ + VINL – 1 – + (+) + (–) VREF1 Delta-Sigma Modulator 3 + 0.1 µF Reference 10 µF VREF2 4 VCC 5 Figure 20. Analog Front End (Left Channel) Analog In X(z) + – 1st SW-CAP Integrator + – 2nd SW-CAP Integrator + 3rd SW-CAP Integrator + + + + – 4th SW-CAP Integrator + 5th SW-CAP Integrator + H(z) 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] Figure 21. Block Diagram of Fifth-Order Delta-Sigma Modulator 12 www.ti.com + Qn(z) Digital Out Y(z) + Comparator PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION system clock The PCM1802 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 15). The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be selected by MODE0 (pin 19) and MODE1 (pin 20), and 768 fS is not available. For system clock inputs of 384 fS, 512 fS, and 768 fS, the system clock is divided to 256 fS automatically, and the 256 fS clock is used to operate the delta-sigma modulator and the digital filter. Table 1 shows the relationship of typical sampling frequencies and system clock frequencies, and Figure 22 shows system clock timing. Table 1. Sampling Frequency and System Clock Frequency SAMPLING RATE FREQUENCY (kHz) 256 fS 384 fS 512 fS 768 fS 32 8.192 12.288 16.384 24.576 44.1 11.2896 16.9344 22.5792 33.8688 48 12.288 18.432 24.576 36.864 SYSTEM CLOCK FREQUENCY (MHz) 64 16.384 24.576 32.768 49.152 88.2 22.5792 33.8688 45.1584 — 96 24.576 36.864 49.152 — tSCKH tSCKL SCKI 2.0 V SCKI 0.8 V PARAMETER tSCKH tSCKL MIN MAX UNIT System clock pulse width, high 7 ns System clock pulse width, low 7 ns Figure 22. System Clock Timing www.ti.com 13 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION power-on reset sequence The PCM1802 has an internal power-on reset circuit and initialization (reset) is performed automatically when the power supply (VDD) exceeds 2.2 V (typ). While VDD < 2.2 V (typ), and for 1024 system-clock counts after VDD > 2.2 V (typ), the PCM1802 stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset state is released and the time of 4480/fS has passed. Figure 23 illustrates the internal power-on reset timing and the digital output for power-on reset. VDD 2.6 V 2.2 V 1.8 V Reset Reset Removal Internal Reset 1024 System Clocks 4480 / fS System Clock DOUT Zero Data Normal Data Figure 23. Internal Power-On Reset Timing serial audio data interface The PCM1802 interfaces with the audio system through BCK (pin 11), LRCK (pin 10), FSYNC (pin 9), and DOUT (pin 12). 14 www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION interface mode The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1 (pin 20) and MODE0 (pin 19) as shown in Table 2. In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802 and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data transfer from an external controller. Table 2. Interface Mode MODE1 MODE0 0 0 Slave mode (256 fS, 384 fS, 512 fS, 768 fS) INTERFACE MODE 0 1 Master mode (512 fS) 1 0 Master mode (384 fS) 1 1 Master mode (256 fS) (1) Master mode In master mode, BCK, LRCK and FSYNC work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802. The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK. The 768 fS system clock is not available in master mode. (2) Slave mode In slave mode, BCK, LRCK and FSYNC work as input pins. FSYNC is used to enable the BCK signal, and the PCM1802 can shift out the converted data while FSYNC is HIGH. The PCM1802 accepts either the 64 BCK/LRCK or the 48 BCK/LRCK format. The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64 BCK/LRCK format and within 12 BCKs for the 48 BCK/LRCK format. data format The PCM1802 supports four audio data formats in both master and slave modes, and they are selected by FMT1 (pin 18) and FMT0 (pin 17) as shown in Table 3. Figure 24 and Figure 26 illustrate the data formats in slave mode and master mode, respectively. Table 3. Data Format FORMAT# FMT1 FMT0 0 0 0 1 0 1 Left justified, 24 bit I2S, 24 bit FORMAT 2 1 0 Right justified, 24 bit 3 1 1 Right justified, 20 bit www.ti.com 15 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION interface timing Figure 25 and Figure 27 illustrate the interface timing in slave mode and master mode, respectively. FORMAT 0: FMT[1:0] = 00 24-Bit, MSB-First, Left-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB 1 LSB FORMAT 1: FMT[1:0] = 01 24-Bit, MSB-First, IIS FSYNC Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 2 3 22 23 24 MSB LSB LSB FORMAT 2: FMT[1:0] = 10 24-Bit, MSB-First, Right-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 24 1 2 3 22 23 24 MSB LSB 1 2 3 22 23 24 MSB LSB FORMAT 3: FMT[1:0] = 11 20-Bit, MSB-First, Right-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 20 1 2 MSB 3 18 19 20 LSB 1 2 3 18 19 20 MSB Figure 24. Audio Data Format (Slave Mode: FSYNC, LRCK, BCK Work as Inputs) 16 www.ti.com LSB PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION interface timing (continued) 1.4 V FSYNC t(FSHD) t(FSSU) t(LRCP) 1.4 V LRCK t(LRSU) t(BCKL) t(LRHD) t(BCKH) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT PARAMETER t(BCKP) t(BCKH) BCK period t(BCKL) t(LRSU) t(LRHD) t(LRCP) MIN TYP MAX UNIT 150 ns BCK pulse duration high 60 ns BCK pulse duration low 60 ns LRCK setup time to BCK rising edge 40 ns LRCK hold time to BCK rising edge 20 ns LRCK period 10 µs t(FSSU) t(FSHD) FSYNC setup time to BCK rising edge 20 ns FSYNC hold time to BCK rising edge 20 ns t(CKDO) t(LRDO) Delay time, BCK falling edge to DOUT valid –10 20 ns Delay time, LRCK edge to DOUT valid –10 20 ns tr tf Rise time of all signals 10 ns Fall time of all signals 10 ns NOTE: Timing measurement reference level is (VIH/VIL)/2. Rise and fall times are measured from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT is 20 pF. Figure 25. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, BCK Work as Inputs) www.ti.com 17 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION interface timing (continued) FORMAT 0: FMT[1:0] = 00 24-Bit, MSB-First, Left-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB 1 LSB FORMAT 1: FMT[1:0] = 01 24-Bit, MSB-First, IIS FSYNC Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 2 3 22 23 24 MSB LSB LSB FORMAT 2: FMT[1:0] = 10 24-Bit, MSB-First, Right-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 24 1 2 3 22 23 24 MSB LSB 1 2 3 22 23 24 MSB LSB FORMAT 3: FMT[1:0] = 11 20-Bit, MSB-First, Right-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 20 1 2 MSB 3 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB Figure 26. Audio Data Format (Master Mode: FSYNC, LRCK, BCK Work as Outputs) 18 www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION interface timing (continued) t(FSYP) 0.5 VDD FSYNC t(CKFS) t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT PARAMETER t(BCKP) t(BCKH) BCK period t(BCKL) t(CKLR) BCK pulse width low t(LRCP) t(CKFS) LRCK period t(FSYP) t(CKDO) FSYNC period Delay time, BCK falling edge to DOUT valid t(LRDO) tr Delay time, LRCK edge to DOUT valid BCK pulse width high Delay time BCK falling edge to LRCK valid MIN TYP MAX UNIT 150 1/(64 fS) 1200 ns 75 600 ns 75 600 ns –10 20 ns 80 µs 10 Delay time BCK falling edge to FSYNC valid 1/ fS –10 20 ns 40 µs –10 20 ns –10 20 ns 10 ns 5 Rise time of all signals 1/(2 fS) tf Fall time of all signals 10 ns NOTE: Timing measurement reference level is (VIH/VIL) / 2. Rise and fall times are measured from 10% to 90% of IN/OUT signal swing. Load capacitance of all signals is 20 pF. Figure 27. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, BCK Work as Outputs) www.ti.com 19 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION synchronization with digital audio system In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced into BPZ code until re-synchronization between LRCK and SCKI is completed. In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization does not occur. Figure 28 illustrates digital output response for loss of synchronization and resynchronization. During undefined data, some noise might be generated in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal creates a data discontinuity in the digital output, which can generate some noise in the audio signal. It is recommended to set PDWN low to get stable analog performance when the sampling rate, interface mode, data format, or oversampling control is changed. Synchronization Lost State of Synchronization SYNCHRONOUS Resynchronization ASYNCHRONOUS SYNCHRONOUS 1/fS DOUT NORMAL DATA UNDEFINED DATA 32/fS ZERO DATA NORMAL DATA Figure 28. ADC Digital Output for Loss of Synchronization and Resynchronization power down, LCF bypass, oversampling control PDWN (pin 7) controls the entire ADC operation. During power-down mode, both the supply current for the analog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized. Also, DOUT (pin 12) is disabled and no system clock is accepted during power-down mode. Table 4. Power-Down Control PDWN Power-down mode LOW Power-down mode HIGH Normal operation mode The built-in function for dc component rejection can be bypassed using the BYPAS (pin 8) control. In bypass mode, the dc components of the analog input signal, internal dc offset, etc., are also converted and included in the digital output data. Table 5. LCF Bypass Control BYPAS 20 LCF (low-cut filter) mode LOW Normal (no dc component on DOUT) mode HIGH Bypass (dc component on DOUT) mode www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 PRINCIPLES OF OPERATION power down, LCF bypass, oversampling control (continued) OSR (pin 16) controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is available for fS < 50 kHz, and must be used carefully as performance is affected by the duty cycle of the 384 fS system clock. Table 6. Oversampling Control OSR Oversampling ratio LOW ×64 HIGH ×128 (fS < 50 kHz) APPLICATION INFORMATION typical circuit connection diagram Figure 29 illustrates a typical circuit connection diagram in which the cutoff frequency of the input HPF is about 8 Hz. L-Ch IN R-Ch IN C1† + C2† + 1 VINL MODE1 20 2 VINR MODE0 19 3 VREF1 FMT1 18 Mode [1:0] C5§ C6W + + 4 VREF2 5 VCC 6 Power Down LCF Bypass R1# 5V 0V + Control Format [1:0] C4‡ FMT0 17 OSR 16 Oversampling AGND SCKI 15 System Clock 7 PDWN VDD 14 8 BYPAS DGND 13 9 FSYNC DOUT 12 Data Out BCK 11 Data Clock PCM1802 Control 10 LRCK + C3‡ 3.3 V 0V L/R Clock Audio Data Processor Frame Sync. † C1, C2: A 1-µF capacitor gives 8-Hz ( τ = 1 µF × 20 kΩ) cutoff frequency for input HPF in normal operation, and requires a power-on settling time with 20-ms time constant in the power-on initialization period. ‡ C3, C4: Bypass capacitors, 0.1-µF ceramic and 10-µF tantalum, depending on layout and power supply. § C5: 0.1-µF ceramic and 4.7-µF tantalum capacitors are recommended. ¶ C6: 0.1-µF ceramic and 4.7-µF tantalum capacitors are recommended for using a noise analog power supply. These capacitor are not required for clean analog supply. # R1: 1-kΩ resistor is recommended for using a noisy analog power supply. This resistor is shorted for a clean analog supply. Figure 29. Typical Circuit Connection www.ti.com 21 PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 APPLICATION INFORMATION board design and layout considerations VCC, VDD pins The digital and analog power supply lines to the PCM1802 should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. AGND, DGND pins To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected internally. These grounds should have very low impedance to avoid digital noise feeding back into the analog ground. They should be connected directly to each other under the parts to reduce the potential noise problem. VIN pins A 1-µF capacitor is recommended as an ac-coupling capacitor which gives 8-Hz cutoff frequency. If a higher full-scale input voltage is required, it can be accommodated by adding only one series resistor to each VIN pin. VREF1 pin A 0.1-µF ceramic and 10-µF chemical capacitors are recommended between VREF1 and AGND to insure low source impedance of ADC references. These capacitors should be located as close as possible to the VREF1 pin to reduce the dynamic errors on ADC references. VREF2 pin The differential voltage between VREF2 and AGND sets the analog input full-scale range. A 0.1-µF ceramic and 10-µF chemical capacitors are recommended between VREF2 and AGND with insertion of a 1-kΩ resistor between VCC and VREF2 for using a noisy analog power supply. These capacitors and resistor are not required for clean analog supply. These capacitors should be located as close as possible to the VREF2 pin to reduce the dynamic errors on ADC references. Full-scale input level is affected by this 1-kΩ resistor and decreases by 3%. DOUT pin The DOUT pin has enough load drive capability, but locating a buffer near the PCM1802 and minimizing load capacitance is recommended if the DOUT line is long, in order to minimize the digital-analog crosstalk and maximize the dynamic performance of the ADC. system clock The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time difference between the system clock transition and the BCK or LRCK transition. 22 www.ti.com PCM1802 SLES023B – DECEMBER 2001 – REVISED MARCH 2002 MECHANICAL DATA DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,15 NOM 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /D 09/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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