19-3315; Rev 0; 7/04 L MANUA ION KIT HEET T A U L EVA TA S WS DA FOLLO Programmable Audio Clock Generator Features ♦ 27MHz Crystal with ±30ppm Frequency Reference Applications Digital TVs DVD Players Set-Top Boxes HDTVs Home Entertainment Centers ♦ Two Buffered Output Ports with Multiple Audio Clocks: 256, 384, or 768 Times fS ♦ Supports Standard and Double Sampling Rates (12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2 kHz, and 96kHz) ♦ I2C Interface or Hardwired Output Clock Selection ♦ Separate Output Clock Enable ♦ Low Jitter Typical 21ps (RMS at 73.728MHz) ♦ No External Components for PLL ♦ Integrated VCXO with ±200ppm Tuning Range ♦ Small Footprint, Thin QFN Package, 4mm x 4mm Ordering Information TEMP RANGE PIN-PACKAGE MAX9485ETP PART -40°C to +85°C 20 Thin QFN-EP* MAX9485EUP -40°C to +85°C 20 TSSOP *EP = Exposed pad. I 2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 14 CLK_OUT1 SDA/FS1 8 13 MODE FS2 9 12 RST GND 10 11 GND TSSOP X2 3 VDD 4 SCL/FS0 5 VDD_P SAO2 SAO1 MCLK 18 17 16 MAX9485 EXPOSED PAD (GROUND) 10 SCL/FS0 7 2 RST 15 GND X1 9 VDD 6 16 CLK_OUT2 1 8 MAX9485 TUN GND X2 5 17 VDD GND X1 4 19 18 MCLK 7 TUN 3 FS2 19 SAO1 GND_P 20 SAO2 6 VDD_P 1 GND_P 2 SDA/FS1 TOP VIEW 20 Pin Configurations 15 VDD 14 CLK_OUT2 13 GND 12 CLK_OUT1 11 MODE THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9485 General Description The MAX9485 programmable multiple-output clock generator provides a cost-efficient solution for MPEG-2 audio systems such as DVD players, DVD drives for multimedia PCs, digital HDTV systems, home entertainment centers, and set-top boxes. The MAX9485 accepts an input reference frequency of 27MHz from a crystal or system reference clock. The device provides two buffered clock outputs of 256, 384, or 768 times the chosen sampling frequency (fS) selected through an I 2 C™ interface or hardwired inputs. Sampling frequencies of 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, or 96kHz are available. The MAX9485 also offers a buffered 27MHz output and an integrated voltage-controlled oscillator (VCXO) that is tuned by a DC voltage generated from the MPEG processor. The use of VCXO allows the audio system clock to lock with the overall system clock. The MAX9485 features the lowest jitter in its class, guaranteeing excellent dynamic performance with audio ADCs and DACs in an MPEG-2 audio system. The device operates with a 3.3V supply and is specified over the -40°C to +85°C extended temperature range. The MAX9485 is offered in 6.5mm x 4.4mm 20-pin TSSOP and 4mm x 4mm 20-pin thin QFN packages. MAX9485 Programmable Audio Clock Generator ABSOLUTE MAXIMUM RATINGS VDD, VDD_P to GND ...............................................-0.3V to +4.0V GND_P to GND ...................................................................±0.3V All Inputs and Outputs to GND...................-0.3V to (VDD + 0.3V) Short-Circuit Duration of Outputs to GND ..................Continuous Continuous Power Dissipation (TA = +70°C) 20-Pin TSSOP (derate 11mW/°C above +70°C) ......... 879mW 20-Lead Thin QFN (derate 16.9mW/°C above +70°C).............................................................1349mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF)...........> ±2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VDD = VDD_P = 3.0V to 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD = VDD_P = 3.3V.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS/LVTTL INPUTS (MODE, RST, X1) (Note 2) High Level-Input Voltage VIH1 2.0 VDD V Low Level-Input Voltage VIL1 0.0 0.8 V Input Current IIL1 -20 +20 µA 2.5 VDD V Input voltage = 0 or VDD THREE-LEVEL INPUTS (FS0, FS1, FS2, SAO1, SAO2) High Level-Input Voltage VIH2 Low Level-Input Voltage VIL2 Input Open Level VIO2 Input Current IIN 0.0 0.8 V Input open 1.3 2.0 V Input voltage = 0 or VDD -10 +10 µA 0.4 V VDD V LVCMOS/LVTTL OUTPUTS (CLK_OUT1, CLK_OUT2, MCLK) Output High Level VOH1 IOH1 = -4mA Output Low Level VOL1 IOL1 = 4mA VDD - 0.6 V I2C INTERFACE INPUT AND OUTPUT (SCL, SDA) Input High Level VIH3 Input Low Level VIL3 Input Current IIN Low-Level Output VOL3 Input Capacitance CIN 0.7 x VDD 0 Input voltage = 0 or VDD 0.3 x VDD -1 +1 IOL3 = 4mA 0.4 8.4 V µA V pF POWER SUPPLY (VDD, VDD_P) Power-Supply Ranges VDD, VDD_P Power-Supply Current IDD+IDD_P 2 3.0 CLK_OUT1, CLK_OUT2 at 73.728MHz, no load, VTUN = 3.0V 3.3 12 _______________________________________________________________________________________ 3.6 V mA Programmable Audio Clock Generator (VDD = VDD_P = 3.0V to 3.6V, TA = -40°C to +85°C, output frequency is 73.728MHz, CL = 20pF, unless otherwise noted. Typical values are at TA = +25°C, VDD = VDD_P = 3.3V.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCXO (MCLK) Crystal Frequency fXTL Nominal frequency Crystal Accuracy Tuning Voltage Range VTUN VCXO Tuning Range VTUN = 0 to 3.0V TUN Input Impedance RTUN Output Clock Frequency fMCLK Output Clock Accuracy 27 MHz ±30 ppm 0 3.0V V -200 +200 ppm 94 kΩ VTUN = 1.75V 27 MHz VTUN = 1.75V (Note 4) ±50 ppm Output Duty Cycle 45 55 65 % Output Jitter tMJ RMS 28 ps Output Rise Time tMR Figure 8 2 ns Output Fall Time tMF Figure 8 2 ns Tuning Response Time tTUN Figure 9 10 µs Power-On Settling Time TPO1 Figure 9 5 ms CLOCK OUTPUTS (CLK_OUT1, CLK_OUT2) Frequency Range (Note 5) fout 256 x fS 8.192 24.576 384 x fS 12.288 36.864 768 x fS 24.576 73.728 Clock Rise Time tR1 Figure 8 2 Clock Fall Time tF1 Figure 8 2 Duty Cycle 45 Output Clock Period Jitter tRJ RMS 50 CLK_OUT1, 2 at 73.728MHz (Note 6) 21 CLK_OUT1, 2 at 36.864MHz 37 MHz ns ns 55 % ps Frequency Settling Time tFST Figure 1 10 ms Power-On Time TPO2 Figure 9 15 ms _______________________________________________________________________________________ 3 MAX9485 AC ELECTRICAL CHARACTERISTICS MAX9485 Programmable Audio Clock Generator I2C TIMING CHARACTERISTICS (VDD = VDD_P = 3.0V to 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD = VDD_P = 3.3V; Figure 7.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial Clock fSCL Bus Free Time Between a STOP and a START Condition tBUF 1.3 µs Hold Time (Repeated) START Condition tHD, STA 0.6 µs Repeated START Condition Setup Time tSU, STA 0.6 µs STOP Condition Setup Time tSU, STO Data Hold Time tHD,DAT Data Setup Time 0.6 (Note 7) 0.05 µs 0.9 µs tSU,DAT 100 ns SCL Clock Low Period tLOW 1.3 µs SCL Clock High Period tHIGH 0.6 µs Rise Time of SDA and SCL, Receiving tR (Notes 3, 8) 20 + 0.1Cb 300 ns Fall Time of SDA and SCL, Receiving tF (Notes 3, 8) 20 + 0.1Cb 300 ns Fall Time of SDA, Transmitting tF (Notes 8, 9) 20 + 0.1Cb 250 ns Pulse Width of Spike Suppressed tSP (Notes 3, 10) Capacitive Load for Each Bus Line Cb 0 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 50 ns 400 pF All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design and characterization. When X1 is used as an external reference. Guaranteed by design and characterization; limits are set at ±6 sigma. Includes crystal accuracy. FXTL = 27MHz. Nominal frequency. See frequency selection paragraph in the Applications Information section. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. Note 8: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. Note 9: Bus sink current is less than 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. Note 10: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. 4 _______________________________________________________________________________________ Programmable Audio Clock Generator 40 30 20 50 VTUN = 1.5V CL = 20pF 40 30 20 10 10 0 0 10 20 30 40 50 60 70 80 90 100 0.5 1.0 1.5 2.0 3.0 2.5 1.5 RISE TIME (tR) 0.5 FALL TIME (tF) 50 60 70 80 CX1 = CX2 = 4.7pF 200 CX1 = CX2 = 5.6pF 100 0 CX1 = CX2 = 6.8pF -100 -200 0 -300 0 4 8 12 20 16 0 0.5 1.0 1.5 2.0 2.5 LOAD CAPACITANCE (pF) VTUN (V) MCLK PERIOD JITTER vs. OUTPUT FREQUENCY CLK_OUT PERIOD JITTER vs. OUTPUT FREQUENCY 500 MAX9485 toc06 50 VTUN = 1.5V CL = 15pF VTUN = 1.5V CL = 15pF 400 PERIOD JITTER (psRMS) 40 30 20 10 3.0 MAX9485 toc07 RISE/FALL TIME (ns) 2.0 1.0 40 300 PULLING RANGE (ppm) VTUN = 1.5V fCLK_OUT = 73.728MHz 30 MCLK PULLING RANGE vs. VTUN MAX9485 toc04 3.0 20 OUTPUT FREQUENCY (MHz) OUTPUT CLOCK RISE/FALL TIME vs. LOAD CAPACITANCE 2.5 10 0 VTUN (V) LOAD CAPACITANCE (pF) PERIOD JITTER (psRMS) 0 20 10 0 0 30 MAX9485 toc05 SUPPLY CURRENT (mA) 40 CL = 20pF fCLK_OUT = 73.728MHz SUPPLY CURRENT (mA) VTUN = 1.5V fCLK_OUT = 73.728MHz MAX9485 toc02 50 MAX9485 toc01 50 SUPPLY CURRENT (mA) SUPPLY CURRENT vs. OUTPUT FREQUENCY SUPPLY CURRENT vs. VTUN MAX9485 toc03 SUPPLY CURRENT vs. LOAD CAPACITANCE 300 200 100 0 0 0 10 20 30 40 50 60 OUTPUT FREQUENCY (MHz) 70 80 0 10 20 30 40 50 60 70 80 OUTPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX9485 Typical Operating Characteristics (VDD = VDD_P = 3.3V, TA = +25°C.) Programmable Audio Clock Generator MAX9485 Pin Description PIN NAME FUNCTION TSSOP TQFN 1 19 VDD_P PLL Power Supply. Bypass VDD_P with a 0.1µF and 0.001µF capacitor to GND_P. 2 20 GND_P PLL Ground 3 1 TUN 4 2 X1 Crystal Connection 1. Connect a fundamental mode crystal between X1 and X2 for use as a VCXO, or drive X1 directly with a 27MHz input reference clock. 5 3 X2 Crystal Connection 2. Connect a fundamental mode crystal between X1 and X2 for use as a VCXO, or leave X2 unconnected when driving X1 with a 27MHz system reference clock. 6, 17 4, 15 VDD 7 5 VCXO Tuning Voltage Input. Apply 0 to 3V at TUN to adjust the VCXO frequency. Connect TUN to VDD when driving X1 directly with a 27MHz input reference clock. Digital Power Supply. Bypass VDD with a 0.1µF and 0.001µF capacitor to GND. SCL/FS0 Serial Clock/Function Selection Input 0. When MODE = low, SCL/FS0 functions as the I2C serial clock input. When MODE = high, SCL/FS0 functions as a three-level input to select sampling frequency. 8 6 SDA/FS1 Serial Data I/O/Function Selection Input 1. When MODE = low, SDA/FS1 functions as the I2C serial data input/output. When MODE = high, SDA/FS1 functions as a three-level input to select output frequency scaling factor. 9 7 FS2 Function Selection Input 2. When MODE = high, FS2 functions as a three-level input to select sampling rate. When MODE = low, voltage levels at FS2 do not affect device operation. 10, 11, 15 8, 9, 13 GND Ground 12 10 RST Reset Input. Drive RST low resets the I2C register to its default state. RST is internally pulled to VDD. 13 11 MODE Mode Control Input. When MODE = low, the I2C interface is active. When MODE = high, the hardwired interface is active, and function selection is programmed by SCL/FS0, SDA/FS1, and FS2. Mode is internally pulled to GND. 14 12 CLK_OUT1 Output Clock Port 1. CLK_OUT1 operates at 256/384/768fs, depending on the function selection. CLK_OUT1 is pulled low when disabled. 16 14 CLK_OUT2 Output Clock Port 2. CLK_OUT2 operates at 256/384/768fs, depending on the function selection. CLK_OUT2 is pulled low when disabled. 18 16 MCLK Master System Clock Buffered Output. MCLK outputs the 27MHz clock generated by the internal VCXO. MCLK is pulled low when disabled. 19 17 SAO1 I2C Device Address Selection Input 1 or MCLK Output Enable Control Input. When MODE = low, SAO1 is a three-level I2C device address programming input. When MODE = high, SAO1 controls MCLK enable/disable. 20 18 SAO2 I2C Device Address Selection Input 2 or CLK_OUT Output Enable Control Input. When MODE = low, SAO2 is a three-level I2C device address programming input. When MODE = high, SAO2 controls CLK_OUT1 and CLK_OUT2 enable/disable. — Exposed Pad EP 6 Exposed Pad. Connect EP to ground. _______________________________________________________________________________________ Programmable Audio Clock Generator VDD_P VDD MAX9485 MCLK COUNTER N COUNTER M PHASE DETECTOR AND LOOP FILTER CLK_OUT1 VCO DIVIDING COUNTER PLL CLK_OUT2 TUN X1 VCXO MODE RST SCL/FS0 SDA/FS1 FS2 CONTROL REGISTERS X2 RESET GND Detailed Description The MAX9485 uses an input reference frequency of 27MHz from a crystal or system reference clock. The device provides two buffered clock outputs of 256, 384, or 768 times the chosen sampling frequency (fS) selected through an I 2 C interface or hardwired inputs. Sampling frequencies of 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, or 96kHz are available. The MAX9485 offers a buffered 27MHz output and an integrated VCXO tuned by a DC voltage generated from the MPEG system. The device operates with a 3.3V supply. Reference and Output Clock The MAX9485 uses the 27MHz crystal or reference clock (master clock) from the audio system and generates an output of 256, 384, or 768 times the audio system sampling frequency (fS). Connect a fundamental SAO1 SAO2 GND_P mode crystal between X1 and X2 or drive X1 with a 27MHz system clock. The choices of sampling frequencies are 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, and 96kHz. The MAX9485 offers two identical outputs: CLK_OUT1 and CLK_OUT2. In the following, the CLK_OUT is used to refer to both outputs. Table 1 shows the relations of fS and the output frequency. Select the output frequency by programming the I2C register or hardwiring inputs FS0, FS1, and FS2. CLK_OUT settling is typically 15ms from power-on or from applying the clock to X1. Delay time from sampling frequency change to CLK_OUT settling is 10ms (typ). Figure 1 illustrates CLK_OUT transient timing in the I2C programmed case. The I2C register is set through a master-write data transfer. The frequency settling time tFST is counted from the end of the next ACK pulse of the written byte in SDA until the CLK_OUT is settled. _______________________________________________________________________________________ 7 MAX9485 Functional Diagram Table 1. Sampling Frequency and Output Clock SAMPLING FREQUENCY fS (kHz) CLK_OUT 256 x fS (MHz) 384 x fS (MHz) 3.072 4.608 9.126 Standard 32 8.1920 12.2880 24.5760 Standard 44.1 11.2896 16.9344 33.8688 Standard 48 12.2880 18.4320 36.8640 Standard 64 16.3840 24.5760 49.1520 Double 88.2 22.5792 33.8688 67.7376 Double 96 24.5760 36.8640 73.7280 Double Voltage-Controlled Crystal Oscillator (VCXO) tFST SDA LOW STABLE CLK_OUT STABLE TRANSITION Figure 1. CLK_OUT Transient Timing 27.0054 27 400ppm The MAX9485 internal VCXO produces a 27MHz reference clock for the PLL used to generate CLK_OUT1 and CLK_OUT2. The oscillator uses a 27MHz crystal as the base frequency reference and has a voltage-controlled tuning input for micro adjustment in a range of ±200ppm. The tuning voltage VTUN can vary from 0 to 3V as shown in Figure 2. Use an AT-cut crystal that oscillates at 27MHz on its fundamental mode with ±30ppm. Use a crystal shunt capacitor less than 12pF, including board parasitic capacitance. Choose an oscillator with a load capacitance less than 14pF to achieve ±200ppm pullability. VCXO, a free-run oscillator, and the buffered output MCLK are not affected by power-on reset and external reset. VCXO has a 5ms settling time at power-on and 10µs at a change of the VTUN voltage. The MAX9485 can be used as a synthesizer with a 27MHz input reference clock. For this mode, connect the 27MHz input clock to X1. Connect TUN to VDD and leave X2 open. This configuration is for applications where the micro tuning is not needed and there is a 27MHz system master clock available. Chip Reset Function 26.9946 0V Figure 2. VCXO Tuning Range 8 SAMPLING RATE 768 x fS (MHz) 12 ACK PULSE HIGH VCXO OUTPUT FREQUENCY (MHz) MAX9485 Programmable Audio Clock Generator 3V VTUN The MAX9485 has an internal reset function. The device resets at power-up or can be externally reset by driving RST low. The reset function sets the registers to default values. MODE sets the device’s programming mode at power-up. When MODE = low, the device is set to software-programmable mode. Set MODE = high for hardwired mode. If MODE = low, the reset sets default values for CLK_OUT1 and CLK_OUT2 to 256 x f S with f S = 32kHz. If MODE = high, the reset sets CLK_OUT1 and CLK_OUT2, according to the values of the hardwired inputs. _______________________________________________________________________________________ Programmable Audio Clock Generator VDD 2.6V 2.2V 1.8V Software and Hardwire Control Modes The MAX9485 sampling frequency, sampling rate, and clock outputs can be programmed through the I 2C 2-wire interface (software mode, MODE = low), or hardwired directly through three-level inputs (hardwire mode, MODE = high). The offered functions for each mode are shown in Table 2. CLK_OUT and MCLK are pulled low when disabled. Hardwire Mode Programming (MODE = High) In hardwire mode, FS2 selects the sampling rate (Table 3). With FS2 = low, the sampling rate is standard. With FS2 = high, the sampling rate is doubled. When FS2 = open, the 12kHz standard rate is selected, overriding the setting of FS0. FS1 selects the scaling factors: 256, 384, and 768 (Table 4). FS0 selects the sample frequencies: 32kHz, 44.1kHz, and 48kHz (Table 5). When MODE = high, inputs SAO1 and SAO2 enable or disable the clock outputs (Tables 6 and 7). CLK_OUT and MCLK are pulled low when disabled. Table 2. Selectable Functions POWER-ON RESET RANGE HARDWIRE MODE MODE = HIGH SOFTWARE MODE MODE = LOW Standard sampling frequencies: 12kHz, 32kHz, 44.1kHz, 48kHz ✓ ✓ Double sampling frequencies: 64kHz, 88.2kHz, 96kHz ✓ ✓ CLK_OUT1, CLK_OUT2, MCLK: enable/disable ✓ ✓ FUNCTIONS INTERNAL RESET RESET PERIOD = 1024 CYCLES AT 27MHz RESET REMOVAL Figure 3. Power-On Reset Timing RST Table 3. Sampling Rate Selection (MIN: 20ns) FS2 INTERNAL RESET RESET PERIOD = 1024 CYCLES AT 27MHz RESET REMOVAL SAMPLING RATE Low Standard (32kHz, 44.1kHz, 48kHz) High Doubled (64kHz, 88.2kHz, 96kHz) Open Standard (12kHz) Table 4. Frequency Scaling Factors Figure 4. External Reset Timing FS1 OUTPUT SCALING FACTOR Low 256 High 384 Open 768 _______________________________________________________________________________________ 9 MAX9485 The internal power-on reset completes after 1024 cycles of the reference clock starting when V DD is greater than 2.2V with a tolerance of ±0.4V. When using the internal power-on reset, RST must be high. Figure 3 shows power-on reset timing. The internal reset function also accepts an external forced reset by driving RST = low. The reset is triggered when RST = low and completes after 1024 reference clock cycles. When a reset is initiated, any pulses on RST during the 1024 reference clock cycles are ignored. If RST is held low at the end of a reset cycle, reset does not initiate until a high-to-low transition is detected at RST. Figure 4 shows external reset timing. MAX9485 Programmable Audio Clock Generator Table 5. Selection of Sampling Frequency FS0 Table 8. Register Address Selection 2 SAMPLING FREQUENCY (kHz) SAO1 SAO2 I C DEVICE ADDRESS Low 32 Open Open 110 0000 High 44.1 Low Open 110 0011 Open 48 High Open 110 0010 Open Low 110 0100 Low Low 110 1000 Low 111 0000 111 0001 Table 6. MCLK Enable/Disable Control SAO1 MCLK High Low Disabled Open High Enabled Low High 111 0010 Reserved High High 111 0100 High Open Table 7. CLK_OUT Enable/Disable Control FUNCTION SAO2 High/low Open Enabled Enabled C7 High/low Low Enabled Disabled C6, C5 Enabled C4 High Disabled CLK_OUT2 BIT SAO1 High/low CLK_OUT1 Table 9. Control Register Bit Mapping Software Mode Programming (MODE = Low) In software mode, the I2C interface writes or reads an 8-bit control register in the MAX9485. The control register controls the rate settings and the clock outputs. Since there is only one register in the MAX9485, no address is assigned to this register. The device has a programmable 7-bit address for the I2C bus, selected by SAO1 and SAO2 (Table 8). At power-up with MODE = low, the MAX9485 reads the state of SAO1 and SAO2, then latches the I2C device address. Table 9 shows the control register bit mapping. Bit C7 enables the MCLK output. Bits C5 and C6 enable the clock outputs CLK_OUT1 and CLK_OUT2, respectively. Bit C4 selects the sampling rates. Bits C3 and C2 choose the output frequency-scaling factor. Bits C1 and C0 determine the sampling frequency. The details are shown in Tables 10–14. MCLK enable/disable CLK_OUT2, CLK_OUT1 enable/disable Sampling-rate selection C3, C2 Frequency-scaling factors C1, C0 Sampling-frequency selection Table 10. MCLK Enable/Disable Control C7 MCLK 0 Disabled 1 Enabled Table 11. CLK_OUT1, 2 Enable/Disable Control C6 C5 CLK_OUT2 1 1 Enabled CLK_OUT1 Enabled 1 0 Enabled Disabled 0 1 Disabled Enabled 0 0 Disabled Disabled Serial Interface The MAX9485 control interface uses a 2-wire I2C serial interface. The device operates as a slave that sends and receives data through clock line SCL and data line SDA to achieve bidirectional communication with the master. A master (typically a microcontroller) initiates all data transfers to and from the MAX9485, and generates the SCL clock that synchronizes the data transfer. The 10 Table 12. Sampling Rate Selection C4 SAMPLING RATE 0 Standard 1 Doubled ______________________________________________________________________________________ Programmable Audio Clock Generator C3 C2 OUTPUT SCALING FACTOR 0 0 256 0 1 384 1 0 768 1 1 Reserved SDA SCL Table 14. Sampling Frequency Selection C1 C0 SAMPLING FREQUENCY (kHz) 0 0 12 0 1 32 1 0 44.1 1 1 48 Note: (C1, C0) = (0, 0) and C4 = 1 (double) is not a proper selection. However, when set, it selects 12kHz sampling frequency. SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on SDA. The SCL line operates only as an input. A pullup resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2-wire bus, or if the master in a single-master system has an open-drain SCL output. Start and Stop Conditions Both SCL and SDA remain high when the interface is idle. The active master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. After communication, the MAX9485 issues a STOP (P) condition by transitioning SDA from low to high while SCL is high, freeing the bus for another transmission (Figure 5). If a START or STOP occurs while a bus transaction is in progress, then it terminates the transaction. Data Transfer and Acknowledge Following the START condition, each SCL clock pulse transfers 1 bit. For the MAX9485 interface, between a START and a STOP, 18 bits are transferred on the 2-wire bus. The first 7 bits are for the device address. Bit 8 indicates the writing (low) or reading (high) operation (R/W). Bit 9 is the ACK for the address and operation type. Bits 10 though 17 form the data byte. Bit 18 is the ACK for the data byte. The master always transfers MAX9485 Table 13. Frequency Scaling Factors S P START CONDITION STOP CONDITION Figure 5. Start and Stop Conditions MASTER-WRITE DATA STRUCTURE S SLAVE ADDRESS 7 BITS R/W A DATA 8 BITS A P A P MASTER-READ DATA STRUCTURE S SLAVE ADDRESS 7 BITS R/W A DATA 8 BITS A = ACK; A = 0: ACKNOWLEDGE, A = 1: NOT ACKNOWLEDGE S = START CONDITION P = STOP CONDITION MASTER TRANSFERS TO SLAVE SLAVE TRANSFERS TO MASTER Figure 6. Serial Interface Data Structure the first 8 bits (address + R/W). The slave (MAX9485) can receive the data byte from the bus or transfer it to the bus from the internal register. The ACK bits are transmitted by the address or data recipient. A low ACK bit indicates a successful transfer (Acknowledge), a high ACK bit indicates an unsuccessful transfer (Not Acknowledge). Figure 6 shows the structure of the data transfer. During a write operation, if more synchronous data is transferred, it overwrites the data in the register. During a read operation, if more clocks are reset on SCL, the SDA continues to respond to the register data. ______________________________________________________________________________________ 11 MAX9485 Programmable Audio Clock Generator SDA tSU, DAT tBUF tSU, STA tLOW tHD, STA tHD, DAT tSU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 7. 2-Wire Serial Interface (tR1, tMR) 80% (tF1, tMF) 80% 2.2V CLK_OUT, MCLK 20% VDD 20% t STOP PULSE AFTER WRITING STOP EDGE RISE AND FALL TIME MEASURED BETWEEN 20% AND 80%. Figure 8. CLK_OUT, MCLK Rise and Fall Time Applications Information Crystal Selection When using the MAX9485’s internal VCXO with an external crystal, connect the crystal to X1 and X2. Choose an AT-cut crystal that oscillates at 27MHz on its fundamental mode with ±30ppm. Use a crystal shunt capacitance less than 12pF, including board parasitic capacitance. Choose an oscillator with a load capacitance less than 14pF to achieve ±200ppm pullability. Note: Pulling range may vary depending on the crystal used. Refer to the MAX9485 Evaluation Kit for details. 12 SDA CLK_OUT1 OR CLK_OUT2 tFST tPO2 VTUN MCLK tPO1 tTUN Figure 9. VCXO and PLL Settling Time ______________________________________________________________________________________ Programmable Audio Clock Generator A specific frequency could be achieved through multiple settings (Table 1) such as different sampling rate and multiplication factors (256, 384, and 768). However, due to the difference of internal structure, the CLK outputs jitter may be different for each setting. Table 15 lists CLK output frequencies and jitter for the various settings. For best performance, the user should choose the setting that gives the lowest jitter at a specific frequency. Power-Supply Bypassing and Ground Management The MAX9485’s high oscillator frequency makes proper layout important to ensure stability. For best performance, place components as close as possible to the device. Digital or AC transient signals on GND can create noise at the clock output. Return GND to the highest-quality ground available. Bypass VDD and VDD_P with 0.1µF and 0.001µF capacitors, placed as close to the device as possible. Careful PC board ground layout minimizes crosstalk between the outputs and digital inputs. Table 15. Jitter Measurements of Output CLKs FOUT (MHz) SCALING FACTOR fS (kHz) TRJ(RMS) (ps) 73.728 768 96 21 67.7376 768 88.2 23.2 49.152 768 64 42.6 36.864 768 48 40 37 36.864 384 96 33.8688 768 44.1 44 33.8688 384 88.2 41.3 24.5760 768 32 66 24.5760 384 64 92 24.5760 256 96 50 22.5792 256 88.2 55.1 18.4320 384 48 59 16.9344 384 44.1 69 16.3840 256 64 134 12.2880 256 48 84.8 12.2880 384 32 170 11.2896 256 44.1 100 9.126 768 12 106 8.1920 256 32 250 4.608 384 12 198 3.072 256 12 324 ______________________________________________________________________________________ 13 MAX9485 Output CLK Frequency Setting with Low Jitter Programmable Audio Clock Generator MAX9485 Typical Application Circuit I2C INTERFACE TO SET AUDIO CLK RATE FILTERED PWM CONTROL VOLTAGE FOR VCXO TUN CLK_OUT1 AUDIO CLK: 256/384/768fS DUAL-CHANNEL AUDIO DAC FRONT AUDIO SIGNALS DUAL-CHANNEL AUDIO DAC SURROUND AUDIO SIGNALS DUAL-CHANNEL AUDIO DAC BACK AUDIO SIGNALS MAX9485 27MHz CRYSTAL AUDIO CLK GENERATOR CLK_OUT2 MCLK 27MHz AUDIO ENCODED DATA FROM DVD/HDD/BS-TUNER MPEG DECODER L CH AUDIO DATA R CH AUDIO DATA Chip Information TRANSISTOR COUNT: 9817 PROCESS: CMOS 14 ______________________________________________________________________________________ Programmable Audio Clock Generator TSSOP4.40mm.EPS ______________________________________________________________________________________ 15 MAX9485 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX9485 Programmable Audio Clock Generator PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.