TI ADS5481IRGCT

ADS5481
ADS5482, ADS5483
www.ti.com ...................................................................................................................................................................................................... SLAS565 – JUNE 2008
16-Bit, 80/105/135-MSPS Analog-to-Digital Converters
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
1
23
•
80/105/135-MSPS Sample Rates
16-Bit Resolution
SFDR = 95 dBc at 70 MHz and 135 MSPS
SNR = 78.6 dBFS at 70 MHz and 135 MSPS
Efficient DDR LVDS-Compatible Outputs
Internal Dither Available
Total Power Dissipation: 2.2 W
Powerdown Mode: 70 mW
On-Chip High Impedance Analog Buffer
QFN-64 PowerPAD™ Package
(9 mm × 9 mm footprint)
Industrial Temperature Range:
–40°C to +85°C
•
•
•
•
•
•
•
Wireless Infrastructure (Multi-Carrier GSM,
WCDMA, LTE)
Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Communication Instrumentation
Radar
Medical Imaging
DESCRIPTION
The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that
operate from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x
integrated analog input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing
the signal source while providing a high-impedance input. An internal reference generator is also provided to
simplify the system design.
Designed for highest total ENOB, the ADS548x family has outstanding low noise performance and spurious-free
dynamic range.
The ADS548x is available in an QFN-64 PowerPAD package. The device is built on Texas Instruments
complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to
+85°C).
SFDR
vs
INPUT FREQUENCY
SNR
vs
INPUT FREQUENCY
100
82
ADS5481
81
ADS5482
80
SNR − dBFS
SFDR − dBc
95
ADS5482
90
ADS5481
85
79
78
ADS5483
77
ADS5483
76
80
75
0
20
40
60
80
100
fI − Input Frequency − MHz
120
140
G068
0
20
40
60
80
100
120
140
fI − Input Frequency − MHz
G069
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ADS5481
ADS5482, ADS5483
SLAS565 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5481
QFN-64
RGC
–40°C to +85°C
AZ5481
ADS5482
QFN-64
RGC
–40°C to +85°C
AZ5482
ADS5483
QFN-64
RGC
–40°C to +85°C
AZ5483
(1)
2
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5481IRGCT
Tape and Reel, 250
ADS5481IRGCR
Tape and Reel, 2000
ADS5482IRGCT
Tape and Reel, 250
ADS5482IRGCR
Tape and Reel, 2000
ADS5483IRGCT
Tape and Reel, 250
ADS5483IRGCR
Tape and Reel, 2000
For the most current product and ordering information see the Package Option Addendum located at the end of this document, or see
the TI website at www.ti.com..
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ADS5482, ADS5483
www.ti.com ...................................................................................................................................................................................................... SLAS565 – JUNE 2008
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage
ADS5481, ADS5482, ADS5483
UNIT
AVDD5 to GND
6
V
AVDD3 to GND
5
V
DVDD3 to GND
Analog input to
GND
Valid when AVDD5 is within normal operating range. When AVDD5 is
off, analog inputs should be <0.5V. If not, the protection diode between
the inputs and AVDD5 will become forward-biased and could be
damaged or shorten device lifetime (see Figure 32). Short transient
conditions during power on/off are not a concern.
Clock input to GND Valid when AVDD3 is within normal operating range. When AVDD3 is
off, clock inputs should be <0.5V. If not, the protection diode between the
inputs and AVDD3 will become forward-biased and could be damaged or
shorten device lifetime (see Figure 39). Short transient conditions during
power on/off are not a concern.
5
V
–0.3 to (AVDD5 + 0.3)
V
–0.3 to (AVDD3 + 0.3)
V
CLKP to CLKM
Digital data output to GND
±2.5
V
–0.3 to (DVDD3 + 0.3)
V
±1
V
–40 to +85
°C
+150
°C
Digital data output Plus-to-Minus
Operating temperature range
Maximum junction temperature
Storage temperature range
ESD, human-body model (HBM)
(1)
–65 to +150
°C
2
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime are available upon
request.
THERMAL CHARACTERISTICS (1)
PARAMETER
RθJA
(1)
TEST CONDITIONS
TYP
UNIT
Soldered thermal pad, no airflow
20
Soldered thermal pad, 150-LFM airflow
16
RθJC
thermal resistance from the junction to the package case (top)
RθJP
thermal resistance from the junction to the thermal pad (bottom)
7
°C/W
0.2
Using 49 thermal vias ( 7 × 7 array). See PowerPAD Package in the Application Information section.
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RECOMMENDED OPERATING CONDITIONS
ADS5481, ADS5482,
ADS5483
MIN
UNIT
TYP
MAX
SUPPLIES
AVDD5
Analog supply voltage
4.75
5
5.25
V
AVDD3
Analog supply voltage
3.1
3.3
3.6
V
DVDD3
Output driver supply voltage
3
3.3
3.6
V
ANALOG INPUT
Differential input range
VCM
3
Input common mode
VPP
3.1
V
5
pF
100
Ω
DIGITAL OUTPUT (DRY, DATA)
Maximum differential output load (parasitic or intentional)
Differential Output Resistance
CLOCK INPUT (CLK)
CLK input sample rate (sine wave)
10
Max
Rated
Clock
Clock amplitude, differential sine wave (see Figure 41)
1.5
5
Clock duty cycle (see Figure 46)
TA
45
Operating free-air temperature
50
–40
MSPS
VPP
55
%
+85
°C
ELECTRICAL CHARACTERISTICS (ADS5481, ADS5482, ADS5483)
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,
sampling rate = Max Rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ADS5481
MIN
TYP
ADS5482
MAX
MIN
TYP
ADS5483
MAX
MIN
TYP
MAX
UNIT
Clock Rate
80
105
135
MSPS
Resolution
16
16
16
Bits
ANALOG INPUTS
Differential input range
3
3
3
3.1
3.1
3.1
Each input to VCM
1000
1000
1000
Ω
Each input to GND
(including package)
3.5
3.5
3.5
pF
125
125
485
MHz
65
65
65
dB
1.2
1.2
1.2
V
Analog input common-mode
voltage
Self-biased; see VCM
specification below
Input resistance (dc)
Input capacitance
Analog input bandwidth
(–3dB)
CMRR
Common-mode rejection ratio
Common-mode signal
70 MHz (see Figure 28)
VPP
V
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
VCM
Analog input common-mode
voltage reference output
With internal voltage
reference
VCM temperature coefficient
4
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3
3.15
3.35
3
3.15
-1
-1
3.35
3
3.15
-1
3.35
V
mV/°C
Copyright © 2008, Texas Instruments Incorporated
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ADS5482, ADS5483
www.ti.com ...................................................................................................................................................................................................... SLAS565 – JUNE 2008
ELECTRICAL CHARACTERISTICS (ADS5481, ADS5482, ADS5483) (continued)
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,
sampling rate = Max Rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ADS5481
ADS5482
ADS5483
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
-0.99
±0.5
1.0
-0.99
±0.5
1.0
-0.99
±0.5
1.0
LSB
-10
±3
+10
-10
±3
+10
-10
±3
+10
LSB
15
-15
15
-15
DYNAMIC ACCURACY
DNL
Differential linearity error
No Missing Codes,
fIN = 30 MHz
INL
Integral linearity error
fIN = 30 MHz
Offset error
-15
Offset temperature coefficient
-0.02
Gain error
-6
Gain temperature coefficient
±2
-0.02
6
-6
-0.01
±2
15
-0.02
6
-6
-0.01
±2
mV
mV/°C
6
-0.01
%FS
mV/°C
POWER SUPPLY
IAVDD5
5-V analog
IAVDD3
3.3-V analog
IDVDD3
3.3-V digital/LVDS
Total power dissipation
IAVDD5
5-V analog
IAVDD3
3.3-V analog
IDVDD3
3.3-V digital/LVDS
VIN = full-scale, fIN = 30
MHz,
fS = Max Rated, Normal
Operation
5-V analog
IAVDD3
3.3-V analog
IDVDD3
3.3-V digital/LVDS
Light Sleep Mode
(PDWNF=H, PDWNS=L)
PSRR
Deep Sleep Mode
(PDWNF=L, PDWNS=H)
TBD
317
330
mA
131
TBD
133
150
mA
60
TBD
60
TBD
60
65
mA
2.2
TBD
2.2
TBD
2.2
2.35
From PDWNF disabled
Slow Wakeup Time (Deep
Sleep)
From PDWNS disabled
AVDD5 supply
Power-supply rejection ratio,
Without 0.1-µF board supply
capacitors, with 1-MHz
supply noise (see
Figure 48)
98
mA
mA
35
35
35
0.07
0.07
TBD
605
TBD
W
98
0.07
605
mA
680
mW
13
13
13
mA
2
2
2
mA
0.07
0.07
0.07
70
Fast Wakeup Time (Light
Sleep)
DVDD3 supply
316
TBD
605
Total power dissipation
AVDD3 supply
TBD
131
98
Total power dissipation
IAVDD5
316
TBD
70
TBD
70
mA
100
mW
600
600
600
µS
6
6
6
mS
60
60
60
dB
80
80
80
dB
95
95
95
dB
DYNAMIC AC CHARACTERISTICS
SNR
Signal-to-noise ratio
fIN = 10 MHz
TBD
81
TBD
80.5
77
fIN = 30 MHz
TBD
80.6
TBD
80.5
77
Spurious-free dynamic range
80.1
79.8
78.6
fIN = 100 MHz
79.6
79.1
78.2
Second-harmonic
dBFS
77.8
fIN = 10 MHz
TBD
98
TBD
98
87
97
fIN = 30 MHz
TBD
97
TBD
97
87
97
fIN = 70 MHz
94
93
95
fIN = 100 MHz
92
93
88
fIN = 130 MHz
HD2
79
fIN = 70 MHz
fIN = 130 MHz
SFDR
79
dBc
85
fIN = 10 MHz
TBD
108
TBD
107
87
102
fIN = 30 MHz
TBD
101
TBD
105
87
99
fIN = 70 MHz
100
101
95
fIN = 100 MHz
99
100
92
fIN = 130 MHz
Copyright © 2008, Texas Instruments Incorporated
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dBc
85
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ELECTRICAL CHARACTERISTICS (ADS5481, ADS5482, ADS5483) (continued)
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,
sampling rate = Max Rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
PARAMETER
HD3
Third-harmonic
TEST CONDITIONS
ADS5481
MIN
TYP
fIN = 10 MHz
TBD
fIN = 30 MHz
TBD
ADS5482
MAX
MIN
TYP
103
TBD
100
TBD
ADS5483
MAX
MIN
TYP
96
87
110
98
87
100
fIN = 70 MHz
94
93
96
fIN = 100 MHz
92
93
88
fIN = 130 MHz
Worst harmonic/spur
(other than HD2 and HD3)
Total harmonic distortion
TBD
100
TBD
98
87
97
fIN = 30 MHz
TBD
98
TBD
98
87
97
fIN = 70 MHz
96
97
98
fIN = 100 MHz
96
94
97
Signal-to-noise and distortion
TBD
96
TBD
94
84
97
fIN = 30 MHz
TBD
94
TBD
93
84
94
fIN = 70 MHz
93
88
91
fIN = 100 MHz
88
92
86
Two-tone SFDR
Effective number of bits
ENOB
RMS idle-channel noise
dBc
dBc
83
fIN = 10 MHz
TBD
80
TBD
79.3
75
77.9
fIN = 30 MHz
TBD
79.5
TBD
79.3
75
77.8
fIN = 70 MHz
78.9
78.2
77.4
fIN = 100 MHz
77.8
78
76.6
fIN = 130 MHz
IMD
dBc
96
fIN = 10 MHz
fIN = 130 MHz
SINAD
UNIT
88
fIN = 10 MHz
fIN = 130 MHz
THD
MAX
dBc
76
fIN1 = 29.5 MHz, fIN2 = 30.5
MHz, each at –7 dBFS,
worst spur
103
101
100
dBFS
fIN1 = 102 MHz, fIN2 = 103
MHz, each at –7 dBFS,
worst spur
90
fIN = 10 MHz (from SINAD
in dBc)
TBD
13
TBD
12.9
12.16
12.6
fIN = 30 MHz (from SINAD
in dBc)
TBD
12.9
TBD
12.9
12.16
12.6
analog inputs shorted
together
1.8
1.8
Bits
2.2
LSBrms
LVDS DIGITAL OUTPUTS
VOD
Differential output voltage (±)
VOC
Common-mode output
voltage
Assumes a 100Ω differential
load on each LVDS pair and
LVDS bias = 3.5 mA
247
350
1.125
454
247
1.375
1.125
350
454
247
1.375
1.125
350
454
1.375
mV
V
DIGITAL INPUTS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
IIL
Low Level Input Current
2.0
PDWNF, PDWNS, DITHER
Input Capacitance
6
2.0
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-1
2.0
V
0.8
0.8
0.8
V
1
1
1
µA
-1
µA
-1
2
2
2
pF
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www.ti.com ...................................................................................................................................................................................................... SLAS565 – JUNE 2008
TIMING INFORMATION
Sample
N
N+5
N+3
ta
N+1
N+2
N+4
tCLKH
N+6
tCLKL
CLKM
CLK
Input
CLKP
Latency = 4.5 Clock Cycles
tDRY
DRY_P
CLK
Output
DRY_M
tDATA
Dx_y_P
Output
Data
E
O
E
O
O
E
O
E
O
E
O
E
E
O
O
Dx_y_M
N–5
N–4
N–3
N–2
N–1
N
N+1
E = Even Bits = B0, B2, B4, B6, B8, B10, B12, B14
O = Odd Bits = B1, B3, B5, B7, B9, B11, B13, B15
T0158-02
Figure 1. Timing Diagram
TIMING CHARACTERISTICS (1)
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,
sampling rate = Max Rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential
clock, unless otherwise noted.
PARAMETER
ta
TEST CONDITIONS
MIN
Aperture delay
MAX
UNIT
200
Aperture jitter, rms
Internal jitter of the ADC
Latency
tCLK
Clock period
tCLKH
Clock pulse duration, high
tCLKL
Clock pulse duration, low
tDRY
CLK to DRY delay (2)
(2)
tDATA
CLK to DATA delay
tSKEW
DATA to DRY skew
tRISE
DRY/DATA rise time
tFALL
DRY/DATA fall time
(1)
(2)
TYP
CLK = max rated clock for that part number
ps
80
fs
4.5
cycles
1e9/CLK
100
ns
0.5e9/CLK
50
ns
0.5e9/CLK
50
ns
Zero crossing, 5-pF parasitic to GND
tDATA – tDRY, 5-pF parasitic to GND
5-pF parasitic to GND
800
1250
1700
ps
700
1250
1800
ps
–600
0
600
ps
500
ps
500
ps
Timing parameters are assured by design or characterization, but not production tested.
DRY and DATA are updated on the rising edge of CLK input. The latency must be added to tDATA to determine the overall propagation
delay.
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PIN CONFIGURATION
D14_15_P
D14_15_M
D12_13_P
D12_13_M
D10_11_P
D10_11_M
D8_9_P
D8_9_M
DRY_P
DRY_M
DVDD3
DGND
63
62
61 60
59
58
57
56
55
54
53
52
51 50
D6_7_M
DVDD3
64
D6_7_P
DGND
ADS548x
RGC Package
(Top View)
49
48
D4_5_P
2
47
D4_5_M
AGND
3
46
D2_3_P
REF
4
45
D2_3_M
NC
5
44
D0_1_P
NC
6
43
D0_1_M
AGND
7
42
DVDD3
AVDD5
8
41
DGND
AVDD5
1
AVDD5
AGND
DITHER
AVDD5
14
35
PDWNF
AVDD3
15
34
PDWNS
16
17
18
19
20
21 22
23
24
25
26
27
28
29
30
33
31 32
LVDSB
AGND
VCM
AVDD3
AGND
AVDD5
NC
36
AGND
37
13
AVDD3
12
AVDD5
INM
AGND
NC
AVDD3
38
AVDD5
11
AGND
INP
CLKP
NC
CLKM
AGND
AGND
NC
39
AVDD3
40
10
AVDD5
9
AGND
AVDD3
P0056-08
8
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Table 1. TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
AVDD5
1, 2, 8, 14, 18,
24, 27, 30
5V Analog Supply
AVDD3
9, 15, 19, 25,
28, 31
3.3V Analog Supply
AGND
3, 7, 10, 13, 17,
20, 23, 26, 29, Analog Ground
32
DVDD3
42, 52, 63
3.3V Digital Supply
DGND
41, 51, 64
Digital Ground
NC
5, 6, 37-40
No Connects - leave floating
INP, INM
11, 12
Differential Analog Inputs (P = Plus = true, M = Minus = complement)
CLKM, CLKP
21, 22
Differential Clock Inputs (P = Plus = true, M = Minus = complement)
REF
4
Reference Voltage Input/Output (1.2V nominal). To use an external reference and to turn the internal
reference off, pull both PDWNF and PDWNS to logic HIGH (DVDD3).
VCM
16
Analog Input Common Mode, Output (3.1V), for use in applications that require use of the internally
generated common-mode. See the Applications section for more information on using VCM.
LVDSB
33
External Bias resistor for LVDS bias current, normally 10kΩ to GND to provide nominal 3.5mA LVDS
current
PDWNF
35
Light Sleep Power Down, Fast Wakeup, Logic HIGH (DVDD3) = light sleep enabled (bandgap reference
remains ON)
PDWNS
34
Deep Sleep Power Down, Slow Wakeup, Logic HIGH (DVDD3) = deep sleep enabled (bandgap
reference is OFF)
DITHER
36
Dither Enable, Logic High (DVDD3) = dither enabled
DRY_P,
DRY_M
54, 53
DataReady Signal (LVDS Clockout) (P = Plus = true, M = Minus = complement)
D14_15_P,
D14_15_M
62, 61
DDR LVDS output bits 14 then 15 (15 is MSB) (P = Plus = true, M = Minus = complement)
DE_O_P,
DE_O_M
43-50, 55-62
DDR LVDS output bits E (EVEN) then O (ODD) (P = Plus = true, M = Minus = complement)
D0_1_P,
D0_1_M
44, 43
PowerPAD
65
DDR LVDS output bits 0 then 1 (0 is LSB) (P = Plus = true, M = Minus = complement)
Analog Ground (exposed pad on bottom of package)
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TYPICAL CHARACTERISTICS
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5481 - 80 MSPS Typical Data
Plots in this section are with clock of 80MSPS unless otherwise specified.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
SFDR = 99 dBc
SINAD = 81 dBFS
SNR = 81.1 dBFS
THD = 96.5 dBc
0
10
20
30
f − Frequency − MHz
SFDR = 99 dBc
SINAD = 80.8 dBFS
SNR = 80.9 dBFS
THD = 94.2 dBc
0
10
20
G001
Spectral Performance
vs
FFT for 60 MHz INPUT SIGNAL
Spectral Performance
vs
FFT for 100 MHz INPUT SIGNAL
SFDR = 102 dBc
SINAD = 80.3 dBFS
SNR = 80.4 dBFS
THD = 97.7 dBc
10
20
30
40
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
SFDR = 94 dBc
SINAD = 79.6 dBFS
SNR = 79.8 dBFS
THD = 92.6 dBc
0
10
20
f − Frequency − MHz
G003
Figure 4.
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40
G002
Figure 3.
f − Frequency − MHz
10
30
f − Frequency − MHz
Figure 2.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
40
Amplitude − dB
Amplitude − dB
Spectral Performance
vs
FFT for 30 MHz INPUT SIGNAL
Amplitude − dB
Amplitude − dB
Spectral Performance
vs
FFT for 10 MHz INPUT SIGNAL
30
40
G004
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5482 - 105 MSPS Typical Data
Plots in this section are with clock of 105MSPS unless otherwise specified.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
Spectral Performance
vs
FFT for 30 MHz INPUT SIGNAL
SFDR = 101 dBc
SINAD = 80.8 dBFS
SNR = 80.8 dBFS
THD = 100.4 dBc
Amplitude − dB
Amplitude − dB
Spectral Performance
vs
FFT for 10 MHz INPUT SIGNAL
0
10
20
30
40
50
10
20
30
40
G005
G006
Figure 6.
Figure 7.
Spectral Performance
vs
FFT for 70 MHz INPUT SIGNAL
Spectral Performance
vs
FFT for 90 MHz INPUT SIGNAL
10
20
30
40
f − Frequency − MHz
50
50
f − Frequency − MHz
SFDR = 97 dBc
SINAD = 79.4 dBFS
SNR = 79.5 dBFS
THD = 93.8 dBc
0
SFDR = 100 dBc
SINAD = 80.2 dBFS
SNR = 80.3 dBFS
THD = 96.6 dBc
0
Amplitude − dB
Amplitude − dB
f − Frequency − MHz
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
SFDR = 90 dBc
SINAD = 78.8 dBFS
SNR = 79.3 dBFS
THD = 88.1 dBc
0
10
G007
Figure 8.
20
30
40
f − Frequency − MHz
50
G008
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5483 - 135 MSPS Typical Data
Plots in this section are with clock of 135MSPS unless otherwise specified.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0.0
SFDR = 97 dBc
SINAD = 78.9 dBFS
SNR = 78.9 dBFS
THD = 94.6 dBc
13.5
27.0
40.5
54.0
67.5
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0.0
SFDR = 97 dBc
SINAD = 78.8 dBFS
SNR = 78.9 dBFS
THD = 94.6 dBc
13.5
27.0
54.0
G037
Figure 11.
SPECTRAL PERFORMANCE
FFT FOR 70 MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 100 MHz INPUT SIGNAL
SFDR = 95 dBc
SINAD = 78.3 dBFS
SNR = 78.5 dBFS
THD = 91 dBc
13.5
27.0
40.5
54.0
67.5
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0.0
SFDR = 88 dBc
SINAD = 77.7 dBFS
SNR = 78.1 dBFS
THD = 86.6 dBc
13.5
27.0
40.5
f − Frequency − MHz
G039
Figure 12.
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67.5
G038
Figure 10.
f − Frequency − MHz
12
40.5
f − Frequency − MHz
Amplitude − dB
Amplitude − dB
f − Frequency − MHz
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0.0
SPECTRAL PERFORMANCE
FFT FOR 30 MHz INPUT SIGNAL
Amplitude − dB
Amplitude − dB
SPECTRAL PERFORMANCE
FFT FOR 10 MHz INPUT SIGNAL
54.0
67.5
G040
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
0.0
3
fIN1 = 39.5 MHz, –10 dBFS
fIN2 = 40.5 MHz, –10 dBFS
IMD3 = 103 dBFS
SFDR = 100 dBFS
SNR = 79 dBFS
ADS5483
0
Normalized Gain − dB
Amplitude − dB
TWO-TONE INTERMODULATION DISTORTION
(FFT for 39.5 MHz and 40.5 MHz at –10 dBFS)
−3
−6
ADS5481
−9
−12
ADS5482
−15
−18
−21
13.5
27.0
40.5
54.0
f − Frequency − MHz
−24
10M
67.5
100M
f − Frequency − Hz
G041
Figure 14.
G042
Figure 15.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
1.0
4
fS = 135 MSPS
fIN = 10 MHz, –1 dBFS
0.8
fS = 135 MSPS
fIN = 10 MHz, –1 dBFS
3
0.6
2
INL − LSB
0.4
DNL − LSB
1G
0.2
0.0
−0.2
−0.4
1
0
−1
−2
−0.6
−3
−0.8
−1.0
−4
0
16384
32768
49152
Code
65536
0
16384
G043
Figure 16.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5481 ADS5482, ADS5483
32768
49152
Code
65536
G044
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
AC PERFORMANCE
vs
INPUT AMPLITUDE (30 MHz Input Signal)
NOISE HISTOGRAM WITH INPUTS SHORTED
35
25
ADS5481/5482
ADS5483
AC Performance − dB
Percentage − %
30
fs = 80 MSPS for ADS5481
fs = 105 MSPS for ADS5482
fs = 135 MSPS for ADS5483
Analog Inputs Shorted to
VCM
20
15
10
5
32701
32702
32699
32700
32697
32698
32695
32696
32693
32694
32691
32692
32689
32690
AC Performance − dB
Input Amplitude − dBFS
Figure 18.
Figure 19.
AC PERFORMANCE
vs
INPUT AMPLITUDE (100 MHz Input Signal)
TWO-TONE PERFORMANCE
vs
INPUT AMPLITUDE (f1 = 39.5 MHz and f2 = 40.5 MHz)
180
SFDR (dBFS,
SNR (dBFS,
SFDR (dBc, SFDR (dBFS,
160
Dither OFF)
Dither OFF)
Dither ON)
Dither ON)
140
120
100
80
60
40
SNR (dBc,
20
Dither ON)
0
SNR (dBFS,
fS = 135 MSPS
−20
Dither ON)
fIN = 100 MHz
−40
AIN = −0.6 to −100 dBFS
SFDR (dBc,
SNR (dBc,
−60
Dither OFF)
Dither OFF)
512k Point FFT
−80
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
Input Amplitude − dBFS
−80
No Dither, Dominant Spur (dBFS)
−90
Dither, Dominant Spur (dBFS)
−100
−110
−120
−130
Dither, 2F1−F2 (dBFS)
−140
Dither, 2F2−F1 (dBFS)
−150
−90
−80
−70
−60
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−50
−40
−30
Input Amplitude − dBFS
G065
Figure 20.
14
G046
G045
Output Code
Performance − dBFS
32687
32688
0
180
SFDR (dBFS,
SNR (dBFS,
SFDR (dBc, SFDR (dBFS,
160
Dither OFF)
Dither OFF)
Dither ON)
Dither ON)
140
120
100
80
60
40
SNR (dBc,
20
Dither ON)
0
SNR (dBFS,
fS = 135 MSPS
−20
Dither ON)
fIN = 30 MHz
−40
AIN = −0.8 to −100 dBFS
SFDR (dBc,
SNR (dBc,
−60
Dither OFF)
Dither OFF)
512k Point FFT
−80
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
−20
−10
0
G047
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SFDR
vs
AVDD5 OVER TEMPERATURE
SNR
vs
AVDD5 OVER TEMPERATURE
100
80
fS = 135 MSPS
fIN = 70 MHz
TA = 100°C
TA = 85°C
TA = −40°C
79
SNR − dBFS
SFDR − dBc
95
90
TA = 0°C
85
TA = −40°C
TA = 55°C
4.8
4.9
TA = 0°C
TA = 55°C
TA = 25°C
TA = 100°C
TA = 85°C
fS = 135 MSPS
fIN = 70 MHz
5.0
5.1
5.2
75
4.7
5.3
4.8
4.9
5.0
5.1
G048
5.3
G049
Figure 22.
Figure 23.
SFDR
vs
AVDD3 OVER TEMPERATURE
SNR
vs
AVDD3 OVER TEMPERATURE
80
fS = 135 MSPS
fIN = 70 MHz
79
SNR − dBFS
90
TA = −20°C
78
77
TA = 25°C
TA = 0°C
TA = 55°C
TA = 25°C
TA = 55°C
TA = −40°C
TA = 0°C
TA = 85°C
76
fS = 135 MSPS
fIN = 70 MHz
3.0
3.1
3.2
3.3
TA = −20°C
TA = −40°C
TA = 100°C
TA = 85°C
95
80
2.9
5.2
AVDD5 − Supply Voltage − V
100
SFDR − dBc
77
76
AVDD5 − Supply Voltage − V
85
78
TA = 25°C
TA = −20°C
80
4.7
TA = −20°C
3.4
3.5
AVDD3 − Supply Voltage − V
3.6
3.7
G050
75
2.9
3.0
3.1
TA = 100°C
3.2
3.3
3.4
3.5
3.6
AVDD3 − Supply Voltage − V
Figure 24.
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3.7
G051
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SFDR
vs
DVDD3 OVER TEMPERATURE
SNR
vs
DVDD3 OVER TEMPERATURE
100
80
fS = 135 MSPS
fIN = 70 MHz
TA = 100°C
TA = 85°C
SNR − dBFS
SFDR − dBc
TA = −40°C
TA = 25°C
TA = 85°C
79
95
90
TA = −40°C
85
TA = −20°C
TA = 0°C
77
TA = 55°C
TA = 0°C
TA = −20°C
78
TA = 55°C
TA = 100°C
TA = 25°C
76
fS = 135 MSPS
fIN = 70 MHz
80
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
DVDD3 − Supply Voltage − V
75
2.9
3.7
3.0
3.1
3.2
G052
Figure 26.
90
−10
80
−20
70
SNR − dBFS
CMRR − dB
3.5
3.6
3.7
G053
ADC WAKEUP TIME
0
−30
−40
−50
PDWNF
60
PDWNS
50
40
30
−60
fS = 135 MSPS
fIN = 10 MHz
PDWNF and PDWNS Tested Independently
PDWNx Disabled at 0 ms
PDWNx Enabled at ≈ 8 ms
20
−70
10
0
1
10
100
fIN − Input Frequency − Hz
1k
0
1
2
3
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4
5
6
t − time − ms
G054
Figure 28.
16
3.4
Figure 27.
CMRR
vs
COMMON-MODE INPUT FREQUENCY
−80
0.1
3.3
DVDD3 − Supply Voltage − V
7
8
9
10
G066
Figure 29.
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ADS5482, ADS5483
www.ti.com ...................................................................................................................................................................................................... SLAS565 – JUNE 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = Max Rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY (ADS5483)
135
130
78.5
76
fS - Sampling Frequency - MSPS
120
110
78
75
77
74
79
100
90
78.5
79
78
76
77
74
75
80
70
60
78.5
78
50
40
10
50
72
150
100
73
74
75
76
77
200
250
300
fIN - Input Frequency - MHz
70
71
73
72
74
75
76
77
78
79
80
SNR - dBFS
M0048-02
Figure 30.
SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY (ADS5483)
135
130
fS - Sampling Frequency - MSPS
120
75
80
95
70
85
90
65
110
100
70
75
90
95
85
90
80
65
80
70
60
40
10
85
95
50
70
80
75
90
50
150
100
65
200
250
300
fIN - Input Frequency - MHz
60
65
70
75
80
85
SFDR - dBc
90
95
M0049-02
Figure 31.
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APPLICATIONS INFORMATION
Theory of Operation
The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit, 80-135MSPS family of monolithic pipeline ADCs. The
bipolar analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide
LVDS-compatible outputs. Prior to the track-and-hold, the analog input signal passes through a high-performance
bipolar buffer. The buffer presents a high and consistent impedance to the analog inputs. The buffer isolates the
board circuitry external to the ADC from the sampling glitches caused by the track-and-hold in the ADC. The
conversion process is initiated by the falling edge of the external input clock. At that instant, the differential input
signal is captured by the input track-and-hold, and the input sample is converted sequentially by a series of lower
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in
a data latency of 4.5 clock cycles, after which the output data are available as a 16-bit parallel word, coded in
offset binary format.
Input Configuration
The analog input for the ADS548x consists of an analog pseudo-differential buffer followed by a bipolar transistor
T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents
a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input.
The input common-mode is set internally through a 1000-Ω resistor connected from 3.1 V to each of the inputs.
This configuration results in a differential input impedance of 2 kΩ at 0 Hz.
ADS548x
Bipolar
Transistor
Buffer
AVDD5
~ 2 nH Bond Wire
10 W
INP
~ 200 fF
Package
Analog
Inputs
~ 200 fF
Bond Pad
3 pF
1000 W
AGND
1000 W
~ 2 nH Bond Wire
Track and Hold,
VCM
AVDD5
st
1 Pipeline Stage
3 pF
AGND
INM
~ 200 fF
Package
~ 200 fF
Bond Pad
10 W
AGND
Bipolar
Transistor
Buffer
S0293-02
Figure 32. Analog Input Circuit
For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings
symmetrically between (3.1 V + 0.75 V) and (3.1 V – 0.75 V). This range means that each input has a maximum
signal swing of 1.5 VPP for a total differential input signal swing of 3 VPP. Operation below 3 VPP is allowable, with
the characteristics of performance versus input amplitude demonstrated in Figure 19 through Figure 21. For
instance, for performance at 2 VPP rather than 3 VPP, refer to the SNR and SFDR at –3.5 dBFS (0 dBFS =
3 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for
any external circuitry for this purpose. The primary degradation visible if the max amplitude is kept to 2 VPP is
~3 dBc of SNR compared to using 3 VPP, while SFDR will be the same or even improved. The smaller input
signal will also likely help any components in the signal chain prior to the ADC to be more linear and provide
better distortion.
18
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The ADS548x performs optimally when the analog inputs are driven differentially. The circuit in Figure 33 shows
one possible configuration using an RF transformer with termination either on the primary or on the secondary of
the transformer. If voltage gain is required, a step-up transformer can be used.
Z0
50 W
R0
50 W
INP
R
200 W
AC Signal
Source
n = 2:1
ADS548x
INM
S0176-04
Figure 33. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
Dither
The ADS548x family of devices contain a dither option that is enabled via the DITHEREN pin. Dither is a
technique applied to convert small static errors in the converter to dynamic errors, which will look similar to white
noise in the output. In virtually all cases tested, the harmonic performance is equal or better when dither is
enabled versus disabled. It improves the harmonics that are a function of the static errors. The dither is very low
level and will only be indicated in the output waveform as wideband noise that may slightly degrade the SNR
(<0.5dB). It is recommended that it be enabled, but users should allow the capability to disable it in the event
they suspect it may be degrading their specific application, or to compare the results during their evaluation.
Figure 19 through Figure 21 show the minor differences of dither ON/OFF when carefully studied.
External Voltage Reference
For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an
external reference. The dependency on the signal amplitude to the value of the external reference voltage is
characterized typically by Figure 34 (VREF = 1.2 V is normalized to 0 dB as this is the internal reference
voltage). As can be seen in the linear fit, this equates to approximately ~1 dB of signal adjustment per 100 mV of
reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied to
the inputs and the desired spectral performance, as can be seen in the performance versus external reference
graphs in Figure 35 and Figure 36.
For dc-coupled applications that use the VCM pin of the ADS548x as the common mode of the signal in the
analog signal gain path prior to the ADC inputs, Figure 38 indicates very little change in VCM output as VREF is
externally adjusted.
The method for disabling the internal reference for use with an external reference is described in Table 4 .
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100
fS = 135 MSPS
fIN = 30 MHz
AIN = < −1 dBFS
Normalized to 1.2 VREF
8
6
AIN = −2 dBFS
95
SFDR − dBc
Normalized Gain Adjustment − dB
10
Linear Fit: y = −9.8x + 11.8
4
2
AIN = −1 dBFS
90
AIN = −10 dBFS
85
AIN = −4 dBFS
AIN = −6 dBFS
80
0
fS = 135 MSPS
fIN = 30 MHz
Dither Enabled
Signal Amplitude Relative
to Adjusted Fullscale
AIN = −3 dBFS
−2
75
−4
0.5
70
0.5
AIN = −7 dBFS
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
Applied External VREF − V
G057
76
1.0
1.1
1.2
1.3
1.4
G058
fS = 135 MSPS
fIN = 30 MHz
Signal Adjusted to −1 dBFS
AIN = −1 dBFS
2.2
AIN = −6 dBFS
P − Power − W
SNR − dBc
0.9
2.3
AIN = −3 dBFS
AIN = −2 dBFS
AIN = −4 dBFS
78
AIN = −7 dBFS
70
68
66
64
62
60
0.5
0.8
Figure 35. SFDR versus External VREF and AIN
80
72
0.7
Applied External VREF − V
Figure 34. Signal Gain Adjustment versus External
Reference (VREF)
74
0.6
AIN = −10 dBFS
0.6
0.7
0.8
0.9
fS = 135 MSPS
fIN = 30 MHz
Dither Enabled
Signal Amplitude Relative
to Adjusted Fullscale
1.0
1.1
1.2
1.3
2.1
2.0
1.9
1.8
1.7
0.5
1.4
Applied External VREF − V
0.6
0.7
0.8
0.9
1.0
1.1
Applied External VREF − V
G059
Figure 36. SNR versus External VREF and AIN
1.2
1.3
1.4
G060
Figure 37. Total Power Consumption versus External
VREF
3.20
VCM Pin Output Voltage − V
3.19
3.18
3.17
3.16
3.15
3.14
3.13
3.12
3.11
3.10
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
Applied External VREF − V
G061
Figure 38. VCM Pin Output versus External VREF
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Clock Inputs
The ADS548x equivalent clock input circuit is shown in Figure 39. The clock inputs can be driven with either a
differential clock signal or a single-ended clock input, but differential is highly recommended. The characterization
of the ADS548x is typically performed with a 3-VPP differential clock, but the ADC performs well with a differential
clock amplitude down to ~1 VPP, as shown in Figure 41 and Figure 42 . The clock amplitude becomes more of a
factor in performance as the analog input frequency increases. When single-ended clocking is a necessity, it is
best to connect CLKM to ground with a 0.01-µF capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to
the clock source, as shown in Figure 42.
Figure 39. Clock Input Circuit
Square Wave or
Sine Wave
CLKP
0.01 mF
ADS548x
CLKM
0.01 mF
S0168-08
Figure 40. Single-Ended Clock
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SFDR
vs
CLOCK AMPLITUDE
SNR
vs
CLOCK AMPLITUDE
80
100
fIN = 9.97 MHz
78
76
90
fIN = 69.59 MHz
SNR − dBFS
SFDR − dBc
95
fIN = 30.13 MHz
85
fIN = 100.33 MHz
80
72
fIN = 69.59 MHz
70
fIN = 30.13 MHz
68
66
64
75
62
fS = 135 MSPS
70
0.0
fIN = 100.33 MHz
fIN = 9.97 MHz
74
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Clock Amplitude − VPP
4.5
5.0
fS = 135 MSPS
60
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Clock Amplitude − VPP
G055
Figure 41.
4.0
4.5
5.0
G056
Figure 42.
For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications
because the board level clock jitter is superior.
The sampling process will be more sensitive to jitter using high analog input frequencies or slow clock
frequencies. Large clock amplitude levels are recommended when possible to reduce the indecision (jitter) in the
ADC clock input buffer. Whenever possible, the ideal combination is a differential clock with large signal swing
(~1-3Vpp). Figure 43 demonstrates a recommended method for converting a single-ended clock source into a
differential clock; it is similar to the configuration found on the evaluation board and was used for much of the
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.
0.1 mF
Clock
Source
CLKP
ADS548x
CLKM
S0194-03
Figure 43. Differential Clock
The common-mode voltage of the clock inputs is set internally to ~2 V using internal 0.5-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS548x features good tolerance to
clock common-mode variation (as shown in Figure 44 and Figure 45). The internal ADC core uses both edges of
the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Performance
degradation as a result of duty cycle can be seen in Figure 46.
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100
81
79
77
10 MHz
80
SNR − dBFS
SFDR − dBc
90
30 MHz
70 MHz
70
100 MHz
60
75
70 MHz
10 MHz
73
100 MHz
71
30 MHz
69
231 MHz
67
50
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Clock Common Mode Voltage − V
231 MHz
65
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Clock Common Mode Voltage − V
G062
Figure 44. SFDR versus Clock Common Mode
G063
Figure 45. SNR versus Clock Common Mode
100
fS = 135 MSPS
AIN = −1 dBFS
Clock Input = 3 Vpp
10 MHz
SFDR − dBc
90
70 MHz
80
30 MHz
70
231 MHz
60
100 MHz
50
0
10
20
30
40
50
60
70
80
90
100
Clock Duty Cycle − %
G064
Figure 46. SFDR vs Clock Duty Cycle
The ADS5483 is capable of achieving 78.2 dBFS SNR at 100 MHz of analog input frequency. In order to achieve
the SNR at 100 MHz the clock source rms jitter (at the ADC clock input pins) must be at most 205 fsec in order
for the total rms jitter to be 220 fsec due to internal ADC aperture jitter of ~80 fsec. A summary of maximum
recommended rms clock jitter as a function of analog input frequency for the ADS5483 is provided in Table 2.
The equations used to create the table are presented and can be used to estimate required clock jitter for
virtually any pipeline ADC.
Table 2. Recommended Approximate RMS Clock Jitter for ADS5483
ANALOG INPUT FREQUENCY
(MHz)
MEASURED SNR
(dBc)
TOTAL JITTER
(fsec rms)
MAXIMUM CLOCK JITTER
(fsec rms)
1
78.2
19581
19581
10
78
2004
2002
70
77.8
300
289
100
77.2
220
205
130
76
177
158
170
75.8
152
129
230
75.1
122
92
300
73.2
116
84
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Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 ´ LOG10 (2 ´ p ´ fIN ´ jTOTAL)
(1)
jTOTAL = (jADC2 + jCLOCK2)1/2
(2)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI
CDCE72010 and CDCM7005. Depending on the jitter requirements, a band pass filter (BPF) is sometimes
required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too
low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed
between the CDC and the BPF, as its harmonics and wide-band noise will be reduced by the BPF.
Figure 47 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCE72010
with the clock signal path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult
to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCE72010 output depends largely on the phase
noise of the VCXO/VCO selected, as well as from the CDCE72010 itself.
Board Master
Reference Clock
(High or Low Jitter)
10 MHz
AMP and/or BPF Optional
REF
LVCMOS
100 MHz
AMP
BPF
XFMR
CLKP
CLKM
ADC
TI ADS548x
400 MHz (To Transmit DAC)
100 MHz (To DSP)
LVPECL
or
LVCMOS
Low Jitter Oscillator
100 MHz (To FPGA)
400 MHz
VCO/
VCXO
CDC
(Clock Distribution Chip)
Ex: TI CDCE72010
To Other
B0268-01
Consult the CDCE72010 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 47. Optimum Jitter Clock Circuit
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Digital Outputs
The ADC provides eight LVDS-compatible, offset binary, DDR data outputs (2 bits per LVDS output driver) and a
data-ready LVDS signal (DRY). It is recommended to use the DRY signal to capture the output data of the
ADS548x (use as a Clock Output). DRY is source-synchronous to the DATA outputs and operates at the same
frequency, creating a full-rate DDR interface that updates data on both the rising and falling edges of DRY. It is
recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance shortens the
data-valid timing window. The values given for timing (see Figure 1) were obtained with a 5-pF parasitic board
capacitance to ground on each LVDS line. When setting the time relationship between DRY and DATA at the
receiving device, it is generally recommended that setup time be maximized, but this partially depends on the
setup and hold times of the device receiving the digital data. Since DRY and DATA are coincident, it will likely be
necessary to delay either DRY such that DATA setup time is maximized.
The LVDS outputs all require an external 100-Ω load between each output pair in order to meet the expected
LVDS voltage levels. For long trace lengths, it may be necessary to place a 100-Ω load on each digital output as
close to the ADS548x as possible and another 100-Ω differential load at the end of the LVDS transmission line to
terminate the transmission line and avoid signal reflections. The effective load in this case reduces the LVDS
voltage levels by half. The current of all LVDS drivers is set externally with a resistor connected between the
LVDSB (LVDS Bias) pin and ground. Normal LVDS current is 3.5mA per LVDS pair, set with a 10kΩ external
resistor. For systems with excessive load capacitance on the LVDS lines, reducing the resistor value in order to
increase the LVDS Bias current is allowed to create a stronger LVDS drive capability. For systems with short
traces and minimal loading, increasing the resistor in order to decrease the LVDS current is allowable in order to
save power. Table 3 provides a sampling of LVDSB resistor values should deviation from the recommended
LVDS output current of 3.5mA be considered. It is not recommended to exceed the range listed in the table. If
the LVDS bias current is adjusted, the differential load resistance should also be adjusted to maintain voltage
levels within the specification for the LVDS outputs. The signal integrity of the LVDS lines on the board layout
should be scrutinized to ensure proper LVDS signal integrity exists.
Table 3. Setting the LVDS Current Drive
LVDSB RESISTOR TO GND, Ω
LVDS NOMINAL CURRENT, mA
6k
5.6
8k
4.3
10k (value for normal recommended operation)
3.5
12k
2.8
14k
2.3
16k
2.0
18k
1.7
20k
1.5
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Power Supplies and Sleep Modes
The ADS548x uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies generate more noise that can be coupled to the ADS548x. However, the PSRR value and plot shown in
Figure 48 were obtained without bulk supply decoupling capacitors. When bulk (0.1 µF) decoupling capacitors
are used near the supply pins, the board-level PSRR is much higher than the stated value for the ADC. The user
may be able to supply power to the device with a less-than-ideal supply and still achieve very good performance.
It is not possible to make a single recommendation for every type of supply and level of decoupling for all
systems. If the noise characteristics of the available supplies are understood, a study of the PSRR data for the
ADS548x may provide the user with enough information to select noisy supplies if the performance is still
acceptable within the frequency range of interest. The power consumption of the ADS548x does not change
substantially over clock rate or input frequency.
0
PSRR − dB
−20
−40
AVDD3V
−60
AVDD5V
−80
−100
DVDD3V
−120
0.1
1
10
100
1k
fIN − Input Frequency − MHz
G067
Figure 48. PSRR versus Supply Injected Frequency
Two separate sleep modes are offered. They are differentiated by the amount of power consumed and the time it
takes for the ADC to wakeup from sleep. The light sleep mode consumes 605mW and can be used when
wakeup of less than 600us is required. Deep sleep consumes 70mW and requires 6ms to wakeup. See the
wakeup characteristic at Figure 29. For directions on enabling these modes, see Table 4. The input clock can be
in either state when the power down modes are enabled. The device can enter powerdown mode whether using
internal or external reference. However, the wakeup time from light sleep enabled to external reference mode is
dependent on the external reference voltage and is not necessarily 0.6 ms, but should be noticeably faster than
deep sleep wakeup. No specific power sequences are required.
Table 4. Power Down and Reference Modes
MODE
26
PDWNF PIN
PDWNS PIN
POWER CONSUMPTION
WAKEUP TIME
on
ADC ON - Internal Reference
LOW
LOW
2.2 W
ADC ON - External Reference
HIGH
HIGH
2.2 W
on
Light Sleep
HIGH
LOW
605 mW when Enabled
0.6 ms
Deep Sleep
LOW
HIGH
70 mW when Enabled
6 ms
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Layout Information
The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the
maximum performance from the ADS548x. Follow general design rules, such as the use of multilayer boards, a
single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The analog input
traces should be isolated from any external source of interference or noise, including the digital outputs as well
as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications
such as high IF sampling where low jitter is required. Besides performance-oriented rules, care must be taken
when considering the heat dissipation of the device. The thermal heatsink included on the bottom of the package
should be soldered to the board as described in the PowerPad Package section. See the ADS548x EVM User
Guide on the TI web site for the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally-enhanced, standard-size IC package designed to eliminate the use of
bulky heatsink and slugs traditionally used in thermal packages. This package can be easily mounted using
standard PCB assembly techniques, and can be removed and replaced using standard repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This pad design provides an extremely low thermal resistance path between the die and the exterior of
the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB
as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section (at the end of this data sheet).
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils (0.013 in or
0.3302 mm) in diameter. The small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25 mil (0.025 in or 0.635 mm) diameter holes under the
package, but outside the thermal pad area, to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002), both available for download at www.ti.com.
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value.
The injected frequency level is translated into dBFS,
the spur in the output FFT is measured in dBFS, and
the difference is the PSRR in dB. The measurement
calibrates out the benefit of the board supply
decoupling capacitors.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
P
SNR + 10log 10 S
PN
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed
as a percentage.
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
PS
SINAD + 10log 10
PN ) PD
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are
presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated
into dBFS, the spur in the output FFT is measured in
dBFS, and the difference is the CMRR in dB.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of converter
performance as compared to the theoretical limit
based on quantization noise:
ENOB = (SINAD – 1.76)/6.02
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range.
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input
value is the difference between the actual transfer
function and this best-fit line, measured in units of
LSB.
Offset Error
Offset error is the deviation of output code from
mid-code when
both
inputs are tied
to
common-mode.
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of the ability to reject frequencies
present on the power supply.
28
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(4)
(5)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Temperature Drift
Temperature drift (with respect to gain error and
offset error) specifies the change from the value at
the nominal temperature to the value at TMIN or TMAX.
It is computed as the maximum variation the
parameters over the whole temperature range divided
by TMIN – TMAX.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
P
THD + 10log 10 S
PD
(6)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
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PACKAGE OPTION ADDENDUM
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11-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS5481IRGCR
PREVIEW
VQFN
RGC
64
2000
TBD
Call TI
Call TI
ADS5481IRGCT
PREVIEW
VQFN
RGC
64
250
TBD
Call TI
Call TI
ADS5482IRGCR
PREVIEW
VQFN
RGC
64
2000
TBD
Call TI
Call TI
ADS5482IRGCT
PREVIEW
VQFN
RGC
64
250
TBD
Call TI
Call TI
ADS5483IRGCR
ACTIVE
VQFN
RGC
64
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5483IRGCRG4
ACTIVE
VQFN
RGC
64
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5483IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5483IRGCTG4
ACTIVE
VQFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS5483IRGCR
VQFN
RGC
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS5483IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5483IRGCR
VQFN
RGC
64
2500
333.2
345.9
28.6
ADS5483IRGCT
VQFN
RGC
64
250
333.2
345.9
28.6
Pack Materials-Page 2
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