LF43891 LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter 9 x 9-bit Digital Filter DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ DESCRIPTION 30 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or 9-bit Two’s Complement Data/Coefficients ❑ 26-bit Data Outputs ❑ Shift-and-Add Output Stage for Combining Filter Outputs ❑ Expandable Data Size, Coefficient Size, and Filter Length ❑ User-Selectable 2:1, 3:1, or 4:1 Decimation ❑ Replaces Harris HSP43891 ❑ 84-pin PLCC, J-Lead The LF43891 is a video-speed digital filter that contains eight filter cells (taps) cascaded internally and a shiftand-add output stage. A 9 x 9 multiplier, three decimation registers, and a 26-bit accumulator are contained in each filter cell. The output stage of the LF43891 contains a 26-bit accumulator which can add the contents of any filter stage to the output stage accumulator shifted right by 8 bits. 8-bit unsigned or 9-bit two’s complement format for data and coefficients can be independently selected. Expanded coefficients and word sizes can be processed by cascading multiple LF43891s to implement larger filter lengths without affecting the sample rate. By reducing the sample rate, a single LF43891 can process larger filter lengths by using multiple passes. The sampling rate can range from 0 to 40 MHz. Over 1000 taps may be processed without overflows due to the architecture of the device. The output sample rate can be reduced to one-half, one-third, or onefourth the input sample rate by using the three decimation registers contained in every filter cell. Matrix multiplication, N x N spatial correlations/convolutions, and other 2-D operations for image processing can also be achieved using these registers. LF43891 BLOCK DIAGRAM DIENB, CIENB, ERASE, DCM1-0 DIN8-0 9 CIN8-0 ADR2-0 9 FILTER CELL 0 9 FILTER CELL 1 9 FILTER CELL 2 9 5 FILTER CELL 3 9 FILTER CELL 4 9 FILTER CELL 5 9 FILTER CELL 6 9 FILTER CELL 7 3 9 COUT8-0 COENB 26 26 26 26 26 26 26 26 MUX 26 SHADD OUTPUT STAGE SENBL SENBH RESET 26 TO ALL CELLS CLK TO ALL REGISTERS SUM25-0 Video Imaging Products 1 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter FIGURE 1. FILTER CELL DIAGRAM CIENB.D DCM0.D C REG D1 REG 1 LD LD D2 REG D3 REG TRI-STATE BUFFER ON FILTER CELL 7 ONLY 1 MUX CIN8-0 LD C8-0 MUX LD DCM1.D D8-0 0 COUT8-0 COENB 0 C8-0 DIENB.D LD DIN8-0 X8-0 X REG M REG0 DCM1 DCM1.D DCM0 DCM0.D RESET.D RESET DIENB.D DIENB CIENB M REG1 LATCHES SIGN EXTENSION 25-18 CIENB.D ADR0 ADR0.D ADR1 ADR1.D ADR2 ADR2.D ACC25-0 ERASE.D ERASE 17-0 RESET.D ERASE.D ACCUMULATOR CELL n ADR0 ADR1 DECODER ADR2 CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 CELL n ACC.D25-0 D Q LD T REG AOUT25-0 CLK RESET.D TO ALL REGISTERS TO ALL REGISTERS (EXCEPT ACCUMULATOR AND T-REGISTER) Video Imaging Products 2 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED CIENB enables the C and D registers for coefficient loading. The registers are loaded on the rising edge of CLK when CIENB is LOW. CIENB is latched and delayed internally which enables the registers for loading one clock cycle after CIENB goes active (loading takes place on the second rising edge of CLK after CIENB goes LOW). Therefore, CIENB must be LOW one clock cycle before the coefficients are placed on the CIN8-0 inputs. The coefficients are held when CIENB is HIGH. DIENB enables the X register for the loading of data. The X register is loaded on the rising edge of CLK when DIENB is LOW. DIENB is latched and delayed internally (loading takes place on the second rising edge of CLK after DIENB goes LOW). Therefore, DIENB must be LOW one clock cycle before the data is placed on the DIN8-0 inputs. The X register is loaded with all zeros when DIENB is HIGH. The output of the C register (C8-0) and X register (X8-0) provide the inputs of the 9 x 9 multiplier. The multiplier is followed by two pipeline registers, FIGURE 2. OUTPUT STAGE DIAGRAM SHADD ADR2-0.D 26 26 26 26 26 26 26 26 D CELL RESULT MUX Q 26 0 0 18 ZERO MUX 9-bit coefficients are loaded into the C register (CIN8-0 ) and are output as COUT8-0 (the COENB signal enables the COUT8-0 outputs). The path taken by the coefficients varies according to the decimation mode chosen. With no decimation, the coefficients move directly from the C register, bypassing all decimation registers, and are available at the output on the following clock cycle. When decimation is chosen, the coefficient output is delayed by 1, 2, or 3 clock cycles depending on how many decimation registers the coefficients pass through (D1, D2, or D3). The number of decimation registers the coefficients pass through is determined by DCM1-0 . Refer to Table 1 for choosing a decimation mode. SIGN EXTENSION 25-18 17-0 17-0 1 FILTER CELL DESCRIPTION 9 x 9-bit Digital Filter 26 OUTPUT BUFFER 25-8 26 1 OUTPUT MUX 0 26 D Q SENBL SENBH 2 CLK TO ALL REGISTERS RESET.D TO ALL REGISTERS M REG0 and M REG1. The output of the multiplier is sign extended and is used as one of the inputs to the 26-bit adder. The output of the 26-bit accumulator provides the second input to the adder. Both the accumulator and T register are loaded simultaneously with the output of the adder. The accumulator is loaded with the output of the adder on every clock cycle unless cleared. Clearing the accumulator can be achieved using two methods. The first method, when both RESET and ERASE are LOW, causes all accumulators and all TRI-STATE BUFFER 26 registers in the device to be cleared together. RESET and ERASE are latched and delayed internally causing the clearing to occur on the second clock cycle after RESET and ERASE go active. The second method, when only ERASE is LOW, clears a single accumulator of a selected cell. The cell is selected using the ADR2-0 inputs (decoded to Cell n). ERASE is latched and delayed internally causing the clearing to occur on the second clock cycle after ERASE goes active. Refer to Table 2 for clearing registers and accumulators. Video Imaging Products 3 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED TABLE 1. 9 x 9-bit Digital Filter SIGNAL DEFINITIONS DECIMATION MODE SELECTION Decimation Function Power 0 Decimation registers not used VCC and GND 0 1 One decimation register used (decimation by one-half) 1 0 Two decimation registers used (decimation by one-third) +5 V power supply. All pins must be connected. 1 1 Three decimation registers used (decimation by one-fourth) DCM1 DCM0 0 Clock TABLE 2. REGISTER AND ACCUMULATOR CLEARING CLK — Master Clock ERASE RESET Clearing Effect 0 0 All accumulators and all registers are cleared 0 1 Only the accumulator addressed by ADR2-0 is cleared 1 0 All registers are cleared (accumulators are not cleared) 1 1 No clearing occurs, internal state remains the same OUTPUT STAGE DESCRIPTION The 26-bit adder contained in the output stage can add the contents of any filter cell accumulator (selected by ADR2-0) with the 18 most significant bits of the output buffer. The result is stored back into the output buffer. The complete operation takes only one clock cycle. The eight least significant bits of the output buffer are lost. The Zero multiplexer is controlled by the SHADD input signal. This allows selection of either the 18 most significant bits of the output buffer or all zeros for the adder input. When SHADD is LOW, all zeros will be selected. When SHADD is HIGH, the 18 most significant bits of the output buffer are selected enabling the shiftand-add operation. SHADD is latched and delayed internally by one clock cycle. The output multiplexer is also controlled by the SHADD input signal. This allows selection of either a filter cell accumulator, selected by ADR2-0, or the output buffer to be output to the SUM25-0 bus. Only the 26 least significant bits from either a filter cell accumulator or the output buffer are output on SUM25-0. If SHADD is LOW during two consecutive clock cycles (low during the current and previous clock cycle), the output multiplexer selects the contents of a filter cell accumulator addressed by ADR2-0. Otherwise, the output multiplexer selects the contents of the output buffer. If the same address remains on the ADR2-0 inputs for more than one clock cycle, SUM25-0 will not change to reflect any updates to the addressed cell accumulator. Only the result from the first selection of the cell (first clock cycle) will be output. This allows the interface of slow memory devices where the output needs to be active for more than one clock cycle. Normal FIR operation is not affected because ADR2-0 is changed sequentially. NUMBER SYSTEMS Data and coefficients can be represented as either 8-bit unsigned or 9-bit two's complement numbers. All values are represented as 9-bit two's complement numbers internally. If the most significant or sign bit is a zero, the multiplier can multiply 8-bit unsigned numbers. The rising edge of CLK strobes all registers. All timing specifications are referenced to the rising edge of CLK. Inputs DIN8-0 — Data Input 9-bit data is latched into the X register of each filter cell simultaneously. The DIENB signal enables loading of the data. CIN8-0 — Coefficient Input 9-bit coefficients are latched into the C register of Filter Cell 0. The CIENB signal enables loading of the coefficients. Outputs SUM25-0 — Data Output The 26-bit result from an individual filter cell will appear when ADR2-0 is used to select the filter cell result. SHADD in conjunction with ADR2-0 is used to select the output from the shift-and-add output stage. COUT8-0 — Coefficient Output The 9-bit coefficient output from Filter Cell 7 can be connected to the CIN8-0 coefficient input of the same LF43891 to recirculate the coefficients. COUT8-0 can also be connected to the CIN8-0 of another LF43891 to cascade the devices. The COENB signal enables the output of the coefficients. Video Imaging Products 4 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter Controls DCM1-0 — Decimation Control SENBH — MSB Output Enable DIENB — Data Input Enable The DCM1-0 inputs select the number of decimation registers to use (Table 1). Coefficients are passed from one cell to another at a rate determined by DCM1-0 . When no decimation registers are selected, the coefficients are passed from cell to cell on every rising edge of CLK (no decimation). When one decimation register is selected, the coefficients are passed from cell to cell on every other rising edge of CLK (2:1 decimation). When two decimation registers are selected, the coefficients are passed from cell to cell on every third rising edge of CLK (3:1 decimation) and so on. DCM1-0 is latched and delayed internally. When SENBH is LOW, SUM25-16 is enabled. When SENBH is HIGH, SUM25-16 is placed in a high-impedance state. The DIENB input enables the X register of every filter cell. While DIENB is LOW, the X registers are loaded with the data present at the DIN8-0 inputs on the rising edge of CLK. While DIENB is HIGH, all bits of DIN8-0 are forced to zero and a rising edge of CLK will load the X register of every filter cell with all zeros. DIENB must be low one clock cycle prior to presenting the input data on the DIN8-0 input since it is latched and delayed internally. CIENB — Coefficient Input Enable The CIENB input enables the C and D registers of every filter cell. While CIENB is LOW, the C and appropriate D registers are loaded with the coefficient data on the rising edge of CLK. While CIENB is HIGH, the contents of the C and D registers are held and the CLK signal is ignored. By using CIENB in its active state, coefficient data can be shifted from cell to cell. CIENB must be low one clock cycle prior to presenting the coefficient data on the CIN8-0 input since it is latched and delayed internally. COENB — Coefficient Output Enable The COENB input enables the COUT8-0 output. When COENB is LOW, the outputs are enabled. When COENB is HIGH, the outputs are placed in a high-impedance state. ADR2-0 — Cell Accumulator Select The ADR2-0 inputs select which cell’s accumulator will available at the SUM25-0 output or added to the output stage accumulator. In both cases, ADR2-0 is latched and delayed by one clock cycle. If the same address remains on the ADR2-0 inputs for more than one clock cycle, SUM25-0 will not change if the contents of the accumulator changes. Only the result from the first selection of the cell (first clock cycle) by ADR2-0 will be available. ADR2-0 is also used to select which accumulator to clear when ERASE is LOW. SENBL — LSB Output Enable When SENBL is LOW, SUM15-0 is enabled. When SENBL is HIGH, SUM15-0 is placed in a high-impedance state. RESET — Register Reset Control When RESET is LOW, all registers are cleared simultaneously except the cell accumulators. RESET can be used with ERASE to clear all cell accumulators. RESET is latched and delayed internally. Refer to Table 2. ERASE — Accumulator Erase Control When ERASE is LOW, the cell accumulator specified by ADR2-0 is cleared. When RESET is LOW in conjunction with ERASE, all cell accumulators are cleared. Refer to Table 2. Video Imaging Products 5 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –400 µA VOL Output Low Voltage VCC = Min., IOL = 2.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max 2.6 Unit V 0.4 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±10 µA Output Leakage Current (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 160 mA ICC2 VCC Current, Quiescent (Note 7) 750 µA CIN Input Capacitance TA = 25°C, f = 1 MHz 10 pF COUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF Video Imaging Products 6 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol 1234567890123 1234567890123 1234567890123 50* 1234567890123 1234567890123 1234567890123 Min Max 1234567890123 1234567890123 50 1234567890123 1234567890123 1234567890123 20 1234567890123 1234567890123 1234567890123 1234567890123 16 1234567890123 1234567890123 1234567890123 0 1234567890123 1234567890123 1234567890123 24 1234567890123 1234567890123 1234567890123 27 1234567890123 1234567890123 1234567890123 20 1234567890123 1234567890123 1234567890123 20 1234567890123 Parameter tCYC Cycle Time tPW Clock Pulse Width tS Input Setup Time tH Input Hold Time tODC Coefficient Output Delay tODS Sum Output Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) LF43891– 40 Min 33 Max Min 39 33 16 13 14 13 0 0 Max 20 18 25 21 15 15 15 15 1234567890123 1234567890123 1234567890123 25* 1234567890123 1234567890123 1234567890123 Min Max 1234567890123 1234567890123 25 1234567890123 1234567890123 1234567890123 10 1234567890123 1234567890123 1234567890123 1234567890123 10 1234567890123 1234567890123 1234567890123 0 1234567890123 1234567890123 1234567890123 16 1234567890123 1234567890123 1234567890123 18 1234567890123 1234567890123 1234567890123 12 1234567890123 1234567890123 1234567890123 12 1234567890123 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol LF43891– 1234567890123456789012345678901212345 1234567890123456789012345678901212345 * 1234567890123456789012345678901212345 50 40* 33* 1234567890123456789012345678901212345 1234567890123456789012345678901212345 Min Max Min Max Min Max 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 50 39 33 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 20 16 13 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 20 17 13 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 0 0 0 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 24 20 18 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 31 25 21 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 20 15 15 1234567890123456789012345678901212345 1234567890123456789012345678901212345 1234567890123456789012345678901212345 20 15 15 1234567890123456789012345678901212345 Parameter tCYC Cycle Time tPW Clock Pulse Width tS Input Setup Time tH Input Hold Time tODC Coefficient Output Delay tODS Sum Output Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) SWITCHING WAVEFORMS tPW CLK tS tH tPW DIN8-0 CIN8-0 CONTROLS* HIGH IMPEDANCE OUTPUTS† tODC tODS tDIS tENA OUTPUT ENABLES‡ *includes DIENB, CIENB, ERASE, RESET, SHADD, DCM1-0, and ADR2-0. †includes SUM25-0 and COUT8-0. ‡includes SENBL, SENBH, and COENB. 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE Video Imaging Products 7 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. where 4 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 20 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. Video Imaging Products 8 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter ORDERING INFORMATION GND SUM24 DCM1 SUM25 SENBH VCC ADR0 ADR1 GND DCM0 ADR2 CLK SHADD COUT0 COUT1 GND COUT2 COUT3 COUT4 COUT5 VCC 84-pin 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 21 22 23 Top View 65 64 63 24 62 25 61 26 60 27 59 28 58 29 57 30 56 31 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 COUT6 COUT7 GND COUT8 COENB VCC ERASE RESET DIENB DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB CIN8 VCC SUM6 GND SUM5 SUM4 VCC SUM3 SUM2 SUM1 SUM0 GND SENBL CIN0 CIN1 VCC CIN2 CIN3 CIN4 CIN5 GND CIN6 CIN7 SUM23 SUM22 VCC SUM21 SUM20 SUM19 SUM18 GND SUM17 SUM16 VCC SUM15 SUM14 SUM13 SUM12 GND SUM11 SUM10 SUM9 SUM8 SUM7 Plastic J-Lead Chip Carrier (J3) Speed 0°C to +70°C — COMMERCIAL SCREENING 40 ns 33 ns LF43891JC40 LF43891JC33 Video Imaging Products 9 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter GND GND SUM5 SUM4 VCC SUM3 SUM2 SUM1 SUM0 GND GND SENBL CIN0 CIN1 VCC CIN2 CIN3 CIN4 CIN5 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 SUM25 SENBH VCC VCC ADR0 ADR1 GND GND DCM0 ADR2 CLK SHADD VCC VCC COUT0 COUT1 GND GND COUT2 COUT3 ORDERING INFORMATION 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 100-pin 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 80 DCM1 COUT4 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 79 SUM24 COUT5 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 78 GND VCC 3 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 77 VCC GND 4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 76 SUM23 COUT6 5 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 75 SUM22 COUT7 6 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 74 VCC GND 7 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 73 VCC GND 8 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 72 SUM21 COUT8 9 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 71 SUM20 COENB 10 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 70 SUM19 VCC 11 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 69 SUM 18 VCC 12 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 68 GND ERASE 13 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 67 GND RESET 14 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Top 66 SUM17 DIENB 15 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 65 DIN8 SUM16 16 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 View 64 VCC DIN7 17 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 63 VCC DIN6 18 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 62 SUM15 DIN5 19 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 61 SUM14 DIN4 20 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 60 SUM13 DIN3 21 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 59 SUM12 DIN2 22 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 58 GND DIN1 23 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 57 DIN0 SUM11 24 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 56 SUM10 CIENB 25 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 55 SUM9 CIN8 26 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 54 SUM8 VCC 27 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 53 SUM7 CIN7 28 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 52 NC CIN6 29 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 51 SUM6 GND 30 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Discontinued Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Plastic Quad Flatpack (Q2) Speed 0°C to +70°C — COMMERCIAL SCREENING Video Imaging Products 10 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter ORDERING INFORMATION 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 84-pin 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 2 3 4 5 6 7 8 9 10 11 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 A 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 GND COENB VCC RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC GND 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 B 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 VCC COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 DIENB DIN5 DIN4 CIN5 CIN3 COUT5 COUT6 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 CIN2 VCC COUT3 COUT4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 E 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Top View 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 CIN1 CIN0 SENBL COUT1 GND COUT2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Through Package F 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 SUM0 VCC GND GND COUT0 SHADD 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 (i.e., Component Side Pinout) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 G 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 SUM1 SUM3 SUM2 ADR2 DCM0 CLK 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 H 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 SUM5 SUM4 ADR1 ADR0 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 J 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 SUM20 SUM17 SUM16 SUM7 GND VCC SUM25 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 K 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 SENBH SUM24 GND VCC SUM19 GND SUM15 SUM12 SUM10 SUM8 SUM6 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 L 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 GND SUM11 SUM9 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Discontinued Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Ceramic Pin Grid Array (G3) Speed 0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Video Imaging Products 11 08/16/2000–LDS.43891-J