HSP43891 Data Sheet May 1999 Digital Filter Features The HSP43891 is a video-speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 9x9 two’s complement multiplier, three decimation registers and a 26-bit accumulator. The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8-bits. The HSP43891 has a maximum sample rate of 30MHz. The effective multiply-accumulate (mac) rate is 240MHz. • Eight Filter Cells File Number 2785.5 • 0MHz to 30MHz Sample Rate • 9-Bit Coefficients and Signal Data • 26-Bit Accumulator per Stage • Filter Lengths Over 1000 Taps • Expandable Coefficient Size, Data Size and Filter Length • Decimation by 2, 3 or 4 Applications • 1-D and 2-D FIR Filters • Radar/Sonar The HSP43891 DF can be configured to process expanded coefficient and word sizes. Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process larger filter lengths at less than 30MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The DF provides for 8-bit unsigned or 9-bit two’s complement arithmetic, independently selectable for coefficients and signal data. • Digital Video • Adaptive Filters • Echo Cancellation • Complex Multiply-Add - Sample Rate Converters Ordering Information Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/2, 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as matrix multiplication and NxN spatial correlations/convolutions for image processing applications. PART NUMBER TEMP. RANGE (oC) HSP43891VC-20 0 to 70 100 Lead MQFP Q100.14x20 HSP43891VC-25 0 to 70 100 Lead MQFP Q100.14x20 HSP43891VC-30 0 to 70 100 Lead MQFP Q100.14x20 HSP43891JC-20 0 to 70 84 Lead PLCC N84.1.15 HSP43891JC-25 0 to 70 84 Lead PLCC N84.1.15 HSP43891JC-30 0 to 70 84 Lead PLCC N84.1.15 HSP43891GC-20 0 to 70 85 Pin CPGA G85.A HSP43891GC-25 0 to 70 85 Pin CPGA G85.A HSP43891GC-30 0 to 70 85 Pin CPGA G85.A PACKAGE PKG. NO. Block Diagram VCC DIENB CIENB DCM0 - 1 ERASE CIN0 - 8 RESET CLK ADRO - 2 VSS DIN0 - DIN8 9 5 DF FILTER CELL 0 9 5 9 DF FILTER CELL 1 26 5 26 9 DF FILTER CELL 2 9 DF FILTER CELL 3 26 9 26 DF FILTER CELL 4 26 9 DF FILTER CELL 5 26 9 DF FILTER CELL 6 26 9 DF FILTER 9 CELL 7 26 COUT0 - 8 COENB 3 MUX RESET CLK SHADD SENBL SENBH 26 ADR0, ADR1, ADR2 2 OUTPUT STAGE 2 SUM0 - 25 1 26 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HSP43891 Pinout 85 PIN GRID ARRAY (PGA) 1 2 3 4 5 6 7 8 9 10 11 DIN0 1 A VSS COENB VCC RESET DIN7 DIN6 DIN3 CIN8 VCC VSS L B VCC DIN1 DIN2 CIENB CIN7 CIN6 CIN4 K COUT7 COUT8 ERASE DIN8 VSS DIENB DIN5 DIN4 CIN5 CIN2 COUT2 CIN3 J VCC H CIN1 CIN0 SENBL SUM0 VCC HSP43891 F G H J COUT0 SHADD ADR2 DCM0 TOP VIEW PINS DOWN CLK VSS SUM1 SUM3 SUM2 ADR1 ADR0 VCC SUM5 SUM4 SUM25 SUM20 SUM17 SUM16 VCC SUM19 6 VSS DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 8 9 10 11 SUM7 VSS VSS SUM11 SUM9 ADR2 DCM0 HSP43891 CLK F SUM1 SUM3 SUM2 BOTTOM VIEW PINS UP VSS COUT0 SHADD VSS SUM0 VCC CIN1 CIN0 SENBL E COUT1 VSS COUT2 D CIN2 VCC DIN4 CIN5 CIN3 COUT3 COUT4 C COUT5COUT6 ALIGN PIN DIENB DIN5 VCC COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4 VSS COENB VCC RESET DIN7 DIN6 DIN3 CIN8 VCC VSS A VSS SUM24 DCM1 SUM25 SENBH VCC ADDR0 ADDR1 VSS DCM0 ADDR2 CLK SHADD COUT0 COUT1 VSS COUT2 COUT3 COUT4 COUT5 VCC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS SUM5 SUM4 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 SUM23 SUM22 VCC SUM21 SUM20 SUM19 SUM18 VSS SUM17 SUM16 VCC SUM15 SUM14 SUM13 SUM12 VSS SUM11 SUM10 SUM9 SUM8 SUM7 SUM7 ADR1 ADR0 G SUM15 SUM12 SUM10 SUM8 SUM6 VCC SUM13 VSS SUM15 SUM12 SUM10 SUM8 SUM6 84 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) HSP43891 TOP VIEW 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 2 7 SUM20 SUM17 SUM16 SUM6 VSS SUM5 SUM4 VCC SUM3 SUM2 SUM1 SUM0 VSS SENBL CIN0 CIN1 VCC CIN2 CIN3 CIN4 CIN5 VSS CIN6 CIN7 L VSS 5 VCC SUM19 VCC SUM25 B K SENBH SUM24 4 DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 D COUT3 COUT4 VSS 3 SENBH SUM24 VSS ALIGN C COUT5 COUT6 PIN E COUT1 2 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 COUT6 COUT7 VSS COUT8 COENB VCC ERASE RESET DIENB DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB CIN8 VCC DIN0 HSP43891 (Continued) SENBH VCC VCC ADDR0 ADDR1 VSS VSS DCM0 ADDR2 CLK SHADD VCC VCC COUT0 COUT1 VSS VSS COUT2 COUT3 SUM25 100 LEAD MQFP TOP VIEW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DCM1 SUM24 VSS VSS SUM23 SUM22 VCC VCC SUM21 SUM20 SUM19 SUM18 VSS VSS SUM17 SUM16 VCC VCC SUM15 SUM14 SUM13 SUM12 VSS SUM11 SUM10 SUM9 SUM8 SUM7 NC SUM6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3 SUM5 SUM4 VCC SUM3 SUM2 SUM1 SUM0 VSS VSS SENBL CIN0 CIN1 VCC CIN2 CIN3 CIN4 CIN5 VSS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS VSS Pinout COUT4 COUT5 VCC VCC COUT6 COUT7 VSS VSS COUT8 COENB VCC VCC ERASE RESET DIENB DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB CIN8 VCC CIN7 CIN6 VSS HSP43891 Pin Description SYMBOL PIN NUMBER TYPE NAME AND FUNCTION VCC B1, J1, A3, K4, L7, A10, F10, D11 +5 power supply input. VSS A1, F1, E2, K3, K6, L9, A11, F11, J11 Power supply ground input. CLK G3 I The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz. DIN0-8 A5-8, B5-7, C6, C7 I These nine inputs are the data sample input bus. Nine-bit data samples are synchronously loaded through these pins to the X register of each filter cell of the DF simultaneously. The DIENB signal enables loading, which is synchronous on the rising edge of the clock signal. The data samples can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s complement values, DIN8 is the sign bit. For 8-bit unsigned values, DIN8 must be held at logical zero. DIENB C5 I A low on this input enables the data sample input bus (DIN0-8) to all the filter cells. A rising edge of the CLK signal occurring while DIENB is low will load the X register of every filter cell with the 9-bit value present on DIN0-8. A high on this input forces all the bits of the data sample input bus to zero; a rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This signal is latched inside the device, delaying its effect by one clock internal to the device. Therefore it must be low during the clock cycle immediately preceding presentation of the desired data on the DIN0-8 inputs. Detailed operation is shown in later timing diagrams. CIN0-8 A9, B9-11, C10, C11, D10, E9, E10 I These nine inputs are used to input the 9-bit coefficients. The coefficients are synchronously loaded into the C register of filter CELL0 if a rising edge of CLK occurs while CIENB is low. The CIENB signal is delayed by one clock as discussed below. The coefficients can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s complement values, CIN8 is the sign bit. For 8-bit unsigned values, CIN8 must be held at logical zero. ALIGN PIN C3 Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect in circuit. CIENB B8 I A low on this input enables the C register of every filter cell and the D (decimation) registers of every filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while CIENB is low will load the C register and appropriate D registers with the coefficient data present at their inputs. This provides the mechanism for shifting coefficients from cell to cell through the device. A high on this input freezes the contents of the C register and the D registers, ignoring the CLK signal. This signal is latched and delayed by one clock internal to the DF. Therefore it must be low during the clock cycle immediately preceding presentation of the desired coefficient on the CIN0-8 inputs. Detailed operation is shown in later timing diagrams. COUT0-8 B2, B3, C1, D1, E1, C2, D2, F2, E3 O These nine three-state outputs are used to output the 9-bit coefficients from filter CELL7. These outputs are enabled by the COENB signal low. These outputs may be tied to the CIN0-8 inputs of the same DF to recirculate to coefficients, or they may be tied to the CIN0-8 inputs of another DF to cascade DFs for longer filter lengths. COENB A2 I A low on the COENB input enables the COUT0-8 outputs. A high on this input places all these outputs in their high impedance state. DCM0-1 L1, G2 I These two inputs determine the use of the internal decimation registers as follows: DCM1 DCM0 0 0 Decimation registers not used DECIMATION FUNCTION 0 1 One decimation register is used 1 0 Two decimation registers are used 1 1 Three decimation registers are used The coefficients pass from cell to cell at a rate determined by the number of decimation registers used. When no decimation registers are used, coefficients move from cell to cell on each clock. When one decimation register is used, coefficients move from cell to cell on every other clock, etc. These signals are latched and delayed by one clock internal to the device. 4 HSP43891 Pin Description SYMBOL (Continued) PIN NUMBER TYPE NAME AND FUNCTION SUM0-25 F9, G9-G11, H10, H11, J2, J5-J7, J10, K2, K5, K7-K11, L2-L6, L8, L10, L11 O These 26 three-state outputs are used to output the results of the internal filter cell computations. Individual filter cell results or the result of the shift and add output stage can be output. If an individual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines whether the selected filter cell result or the output stage adder result is output. The signals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However individual enables are provided to facilitate use with a 16-bit bus. SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high impedance state. SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high impedance state. ADR0-2 G1, H1, H2 I These three inputs select the one cell whose accumulator will be read through the output bus (SUM025) or added to the output stage accumulator. They also determine which accumulator will be cleared when ERASE is low. These inputs are latched in the DF and delayed by one clock internal to the device. If ADR0-2 remains at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock, when ADR0-2 selects the cell, will be output. This does not hinder normal operation since the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. SHADD F3 I The SHADD input controls the activation of the shift and add operation in the output stage. This signal is latched on chip and delayed by one clock internal to the device. Detailed explanation is given in the DF Output Stage section. RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators It can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF and delayed by one clock internal to the device. ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. If RESET is also low simultaneously, all cell accumulators are cleared. Functional Description The Digital Filter Processor (DF) is composed of eight filter cells cascaded together and an output stage for combining or selecting filter cell outputs (See Block Diagram). Each filter cell contains a multiplier-accumulator and several registers (Figure 1). Each 9-bit coefficient is multiplied by a 9-bit data sample, with the result added to the 26-bit accumulator contents. The coefficient output of each cell is cascaded to the coefficient input of the next cell to its right. DF Filter Cell A 9-bit coefficient (CIN0-8) enters each cell through the C register on the left and exits the cell on the right as signals COUT0-8. With no decimation, the coefficient moves directly from the C register to the output, and is valid on the clock following its entrance. When decimation is selected the coefficient exit is delayed by 1, 2 or 3 clocks by passing through one or more decimation registers (D1, D2 or D3). The combination of D registers through which the coefficient passes is determined by the state of DCM0 and DCM1. The output signals (COUT0-8) are connected to the CIN0-8 inputs of the next cell to its right. The COENB input signal enables the COUT0-8 outputs of the right most cell to the COUT0-8 pins of the device. 5 The C and D registers are enabled for loading by CIENB. Loading is synchronous with CLK when CIENB is low. Note that CIENB is latched internally. It enables the register for loading after the next CLK following the onset of CIENB low. Actual loading occurs on the second CLK following the onset of CIENB low. Therefore CIENB must be low during the clock cycle immediately preceding presentation of the coefficient on the CIN0-8 inputs. In most basic FIR operations, CIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When CIENB is high, the coefficients are frozen. The C and D registers are cleared synchronously under control of RESET, which is latched and delayed exactly like CIENB. The output of the C register (C0-8) is one input to 9 x 9 multiplier. The other input to the 9 x 9 multiplier comes from the output of the X register. This register is loaded with a data sample from the device input signals DIN0-8 discussed above. The X register is enabled for loading by DIENB. Loading is synchronous with CLK when DIENB is low. Note that DIENB is latched internally. It enables the register for loading after the next CLK following the onset of DIENB low. Actual loading occurs on the second CLK following the onset of DIENB low; therefore, DIENB must be low during the clock HSP43891 cycle immediately preceding presentation of the data sample on the DIN0-8 inputs. In most basic FIR operations, DIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When DIENB is high, the X register is loaded with all zeros. The multiplier is pipelined and is modeled as a multiplier core followed by two pipeline registers, MREG0 and MREG1 (Figure 1). The multiplier output is sign extended and input as one operand of the 26-bit adder. The other adder operand is the output of the 26-bit accumulator. The adder output is loaded synchronously into both the accumulator and the TREG. The TREG loading is disabled by the cell select signal, CELLn, where n is the cell number. The cell select is decoded from the ADR0-2 signals to generate the TREG load enable. The cell select is inverted and applied as the load enable to the TREG. Operation is such that the TREG is loaded whenever the cell is not selected. Therefore, TREG is loaded every clock except the clock following cell selection. The purpose of the TREG is to hold the result of a sum-ofproducts calculation during the clock when the accumulator is cleared to prepare for the next sum-of-products calculation. This allows continuous accumulation without wasting clocks. The accumulator is loaded with the adder output every clock unless it is cleared. It is cleared synchronously in two ways. When RESET and ERASE are both low, the accumulator is cleared along with all other registers on the device. Since ERASE and RESET are latched and delayed one clock internally, clearing occurs on the second CLK following the onset of both ERASE and RESET low. The second accumulator clearing mechanism clears a single accumulator in a selected cell. The cell select signal, CELLn, decoded from ADR0-2 and the ERASE signal enable clearing of the accumulator on the next CLK. The ERASE and RESET signals clear the DF internal registers and states as follows: ERASE RESET CLEARING EFFECT 1 1 No clearing occurs, internal state remains same. 1 0 RESET only active, all registers except accumulators are cleared, including the internal pipeline registers. 0 1 ERASE only active, the accumulator whose address is given by the ADR0-2 inputs is cleared. 0 0 Both RESET and ERASE active, all accumulators as well as all other registers are cleared. The DF Output Stage The output stage consists of a 26-bit adder, 26-bit register, feedback multiplexer from the register to the adder, an output multiplexer and a 26-bit three-state driver stage (Figure 2). The 26-bit output adder can add any filter cell accumulator result to the 18 most significant bits of the output buffer. This result is stored back in the output buffer. This operation takes place in one clock period. The eight LSBs of the output buffer are lost. The filter cell accumulator is selected by the ADR0-2 inputs. The 18 MSBs of the output buffer actually pass through the zero mux on their way to the output adder input. The zero mux is controlled by the SHADD input signal and selects either the output buffer 18 MSBs or all zeros for the adder input. A low on the SHADD input selects zero. A high on the SHADD input selects the output buffer MSBs, thus, activating the shift-and-add operation. The SHADD signal is latched and delayed by one clock internally. 6 HSP43891 DCM1.D DCM0.D RESET.D CIENB.D LD CLR LD CLR C REG D1 REG C0-8 CIN0-8 1 LD CLR LD CLR D2 REG D3 REG THREE-STATE BUFFERS ON CELL 7 ONLY 1 MUX MUX COUT0-8 CLK CLK CLK D0-8 0 0 C0-8 RESET.D COENB DIENB.D LD CLR X REG C MULTIX PLIER CORE P0-17 X0-8 DIN0-8 CLK MREG0 RESET.D CLR CLK LATCHES DCM1 DCM1.D DCM0 DCM0.D RESET RESET.D DIENB DIENB.D CIENB CIENB.D ADR0 ADR0.D ADR1 ADR1.D ADR2 ADR2.D MREG1 CLR 0-17 SIGN EXTENSION ACC.D0-25 ERASE.D ERASE ADDER CLK ACC0-25 ACC ERASE.D CLR CELLn CELL 0 CELL 1 ADR0 ADR1 DECODER CELL 7 ADR2 T REG D CELLn Q LD CLK AOUT0-25 FIGURE 1. HSP43891 DF FILTER CELL 7 CLK HSP43891 0 1 6 7 CELL RESULTS 26 26 3 ADR0.D - ADR2.D 26 26 CELL RESULT MUX 0-18 18 SIGN EXT 18-25 DF Arithmetic 8 26 18 (LSBs) 0-17 RESET.D + 26 SHADD.D CLR Q D SHADD ZERO MUX 0 CLK 1 OUTPUT BUFFER RESET.D 26 CLK 0-17 18 8-25 0’s 18 MSBs SHIFTED 8 BITS TO RIGHT 26 26 1 0 OUTPUT MUX RESET.D 26 CLR Q D SENBL SENBH 2 The SUM0-25 output bus is controlled by the SENBH and SENBL signals. A low on SENBL enables bits SUM0-15. A low on SENBH enables bits SUM16-25. Thus, all 26 bits can be output simultaneously if the external system has a 26-bit or larger bus. If the external system bus is only 16 bits, the bits can be enabled in two groups of 16 and 10 bits (sign extended). 3-STATE BUFFER 26 CLK Both data samples and coefficients can be represented as either 8-bit unsigned or 9-bit two’s complement numbers. The 9x9 bit multiplier in each cell expects 9-bit two’s complement operands. The binary format of 8-bit two’s complement is shown below. Note that if the most significant or sign bit is held at logical zero, the 9-bit two’s complement multiplier can multiply 8-bit unsigned operands. Only the upper (positive) half of the two’s complement binary range is used. The multiplier output is 18 bits and the accumulator is 26 bits. The accumulator width determines the maximum possible number of terms in the sum of products without overflow. The maximum number of terms depends also on the number system and the distribution of the coefficient and data values. Then maximum numbers of terms in the sum products are: MAXIMUM # OF TERMS NUMBER SYSTEM Two Unsigned Vectors 8-BIT 9-BIT 1032 N/A 2080 1032 Two Two’s Complement Vectors SUM0-25 FIGURE 2. HSP43891 DFP OUTPUT STAGE The 26 least significant bits (LSBs) from either a cell accumulator or the output buffer are output on the SUM0-25 bus. The output mux determines whether the cell accumulator selected by ADR0-2 or the output buffer is output to the bus. This mux is controlled by the SHADD input signal. Control is based on the state of the SHADD during two successive clocks; in other words, the output mux selection contains memory. If SHADD is low during a clock cycle and was low during the previous clock, the output mux selects the contents of the filter cell accumulator addressed by ADR0-2. Otherwise the output mux selects the contents of the output buffer. If the ADR0-2 lines remain at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock when ADR0-2 selects the cell will be output. This does not hinder normal FIR operation since the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. 8 • Two Positive Vectors • Negative Vectors 2047 1024 • One Positive and One Negative Vector 2064 1028 One Unsigned 8-Bit Vector and One Two’s Complement Vector • Positive Two’s Complement Vector 1036 1032 • Negative Two’s Complement Vector 1028 1028 For practical FIR filters, the coefficients are never all near maximum value, so even larger vectors are possible in practice. Basic FIR Operation A simple, 30MHz 8-tap filter example serves to illustrate more clearly the operation of the DF. The sequence table (Table 1) shows the results of the multiply accumulate in each cell after each clock. The coefficient sequence, CN, enters the DF on the left and moves from left to right through the cells. The data sample sequence, XN, enters the DF from the top, with each cell receiving the same sample simultaneously. Each cell accumulates the sum of products for one output point. Eight sums of products are calculated simultaneously, but staggered in time so that a new output is available every system clock. HSP43891 TABLE 1. HSP43891 30MHz, 8-TAP FIR FILTER SEQUENCE X15 . . . X9, X8, X7 . . . X1, X0 . . . Y15, Y14 . . . Y8, Y7 HSP43891 C0 . . . C6, C7, C0 . . . C6, C7 CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR 0 C7 x X0 0 0 0 - - - - - 1 +C6 x X1 C7 x X1 0 0 - - - - - 2 +C5 x X2 +C6 x X2 C7 x X2 0 - - - - - 3 +C4 x X3 +C5 x X3 +C6 x X3 C7 x X 3 - - - - - 4 +C3 x X4 +C4 x X4 +C5 x X4 +C6 x X4 C7 x X 4 - - - - 5 +C2 x X5 +C3 x X5 +C4 x X5 +C5 x X5 +C6 x X5 C7 x X5 - - - 6 +C1 x X6 +C2 x X6 +C3 x X6 +C4 x X6 +C5 x X6 +C6 x X6 C7 x X6 - - 7 +C0 x X7 +C1 x X7 +C2 x X7 +C3 x X7 +C4 x X7 +C5 x X7 +C6 x X7 C7 x X7 Cell 0 (Y7) 8 C7 x X8 +C0 x X8 +C1 x X8 +C2 x X8 +C3 x X8 +C4 x X8 +C5 x X8 +C6 x X8 Cell 1 (Y8) 9 +C6 x X9 C7 x X9 +C0 x X9 +C1 x X9 +C2 x X9 +C3 x X9 +C4 x X9 +C5 x X9 Cell 2 (Y9) 10 +C5 x X10 +C6 x X10 C7 x X10 +C0 x X10 +C1 x X10 +C2 x X10 +C3 x X10 +C4 x X10 Cell 3 (Y10) 11 +C4 x X11 +C5 x X11 +C6 x X11 C7 x X11 +C0 x X11 +C1 x X11 +C2 x X11 +C3 x X11 Cell 4 (Y11) 12 +C3 x X12 +C4 x X12 +C5 x X12 +C6 x X12 C7 x X12 +C0 x X12 +C1 x X12 +C2 x X12 Cell 5 (Y12) 13 +C2 x X13 +C3 x X13 +C4 x X13 +C5 x X13 +C6 x X13 C7 x X13 +C0 x X13 +C1 x X13 Cell 6 (Y13) 14 +C1 x X14 +C2 x X14 +C3 x X14 +C4 x X14 +C5 x X14 +C6 x X14 +C7 x X14 +C0 x X14 Cell 7 (Y14) 15 +C0 x X15 +C1 x X15 +C2 x X15 +C3 x X15 +C4 x X15 +C5 x X15 +C6 x X15 C7 x X15 Cell 0 (Y15) SAMPLE DATA IN (XN) 3-BIT COUNTER 30MHz CLOCK Y2 Y1 +5V Y0 9 ADR2 ADR1 ADR0 VCC SHADD SENBH SENBL DIN0-8 26 SUM0-25 SUM OUT (YN) DIENB CLK A2 A1 A0 HSP43891 D0-D8 9 x 8 COEFF. RAM/ROM 9 9 CIN0-8 COUT0-8 CIENB DCM1 DCM0 RESET ERASE VSS COENB SYSTEM RESET ERASE FIGURE 3. HSP43891 30MHz, 8-TAP FIR FILTER APPLICATION SCHEMATIC 9 NC HSP43891 length and Td = 4, the internal pipeline delay of the DF. After the pipeline has filled, a new output sample is available every clock. The delay to last sample output from last sample input is Td. The output sums, YN, shown in the timing diagram are derived from the sum-of-products equation. Detailed operation of the DF to perform a basic 8-tap, 9-bit coefficient, 9-bit data, 30MHz FIR filter is best understood by observing the schematic (Figure 3) and timing diagram (Figure 4). The internal pipeline length of the DF is four (4) clock cycles, corresponding to the register levels CREG (or XREG), MREG0, MREG1, and TREG (Figures 1 and 2). Therefore, the delay from presentation of data and coefficients at the DIN0-8 and CIN0-8 inputs to a sum appearing at the SUM0-25 output is: k + Td, where k = filter 0 1 2 3 4 5 6 7 8 YN = 9 10 11 7 Σ CK XN –K K = 0 12 13 14 15 16 17 18 19 20 CLK RESET ERASE DIN0-8 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 0 1 2 3 4 5 6 7 0 Y7 Y8 Y9 DIENB CIN0-8 CIENB ADR0-2 SUM0-25 Y10 Y11 Y12 Y13 Y14 SHADD SENBL SENBH DCM0-1 0 FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING SAMPLE DATA IN (XN) 30MHz CLOCK D Q C Q +5V ADR1 ADR2 ADR0 9 +5V SHADD SENBL SENBH VCC ADR1 26 SUM0-25 DIN0-8 DIENB CLK CLK Y0 4-BIT Y1 CTR Y2 Y3 9x16 COEFF RAM/ROM A0 D0-D8 A 1 A2 A3 9 VCC SHADD SENBL SENBH 26 SUM0-25 DIN0-8 DIENB CLK HSP43891 DF0 HSP43891 DF1 9 9 CIN0-8 COUT0-8 RESET DCM1 VSS CIENB DCM0 ERASE COENB RESET ADR2 ADR0 9 CIN0-8 NC COUT0-8 RESET DCM1 VSS CIENB DCM0 ERASE COENB SUM OUT (YN) SYSTEM RESET FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC 10 HSP43891 Extended FIR Filter Length Filter Cascade Configuration lengths greater that eight taps can be created by either cascading together multiple DF devices or “reusing” a single device. Using multiple devices, an FIR filter of over 1000 taps can be constructed to operate at a 30MHz sample rate. Using a single device clocked at 30MHz, an FIR filter of over 500 taps can be constructed to operate at less than a 30MHz sample rate. Combinations of these two techniques are also possible. To design a filter length L>8, L/8 DFs are cascaded by connecting the COUT0-8 outputs of the (i)th DF to the CIN08 inputs of the (i+1)th DF. The DIN0-8fs inputs and SUM0-25 outputs of all the DFs are also tied together. A specific example of two cascaded DFs illustrates the technique (Figure 5). Timing (Figure 6) is similar to the simple 8-tap FIR, except the ERASE and SENBL/SENBH signals must be enabled independently for the two DFs in order to clear the correct accumulators and enable the SUM0-25 output signals at the proper times. TABLE 2. DATA SEQUENCE INPUT X30 . . . X9, X8, X22 . . . X1, X0 COEFFICIENT SEQUENCE INPUT C0 . . . C14, C15, 0 . . . C0 . . . C14, C15 HSP43891 . . . 0, Y30 . . . Y23, 0. . . 0, Y22 . . . Y15, 0. . . 0 CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C15 x X0 +C14 x X1 +C13 x X2 +C12 x X3 +C11 x X4 +C10 x X5 +C9 x X6 +C8 x X7 +C7 x X8 +C6 x X9 +C5 x X10 +C4 x X11 +C3 x X12 +C2 x X13 +C1 x X14 +C0 x X15 0 0 0 0 0 0 0 C15 x X8 +C14 x X9 +C13 x X10 +C12 x X11 +C11 x X12 +C10 x X13 +C9 x X14 +C8 x X15 +C7 x X16 +C6 x X17 +C5 x X18 +C4 x X19 +C3 x X20 +C2 x X21 +C1 x X22 +C0 x X23 0 0 0 0 0 C15 x X1 0 0 C15 x X2 0 0 0 C15 x X3 +C14 x X4 +C13 x X5 +C12 x X6 +C11 x X7 +C10 x X8 +C9 x X9 +C8 x X10 +C7 x X11 +C6 x X12 +C5 x X13 +C4 x X14 +C3 x X15 +C2 x X16 +C1 x X17 +C0 x X18 0 0 0 0 0 0 0 +C15 x X11 C15 x X4 C15 x X5 C15 x X6 C15 x X7 +C14 x X8 +C13 x X9 +C12 x X10 +C11 x X11 +C10 x X12 +C9 x X13 +C8 x X14 +C7 x X15 +C6 x X16 +C5 x X17 +C4 x X18 +C3 x X19 +C2 x X20 +C1 x X21 +C0 x X22 0 0 0 0 0 0 0 C15 x X15 +C14 x X16 +C13 x X17 +C12 x X18 +C11 x X19 +C10 x X20 +C9 x X21 +C8 x X22 +C7 x X23 +C6 x X24 +C5 x X25 +C4 x X26 +C3 x X27 Cell 0 (Y15) Cell 1 (Y16) Cell 2 (Y17) Cell 3 (Y18) Cell 4 (Y19) Cell 5 (Y20) Cell 6 (Y21) Cell 7 (Y22) Cell 0 (Y23) Cell 1 (Y24) Cell 2 (Y25) Cell 3 (Y26) Cell 4 (Y27) C0 x X16 0 0 0 0 0 0 0 +C15 x X9 C0 x X17 0 0 0 0 0 0 0 +C15 x X10 C0 x X23 0 0 0 11 C0 x X25 0 0 C0 x X26 0 C0 x X19 0 0 0 0 0 0 0 +C15 x X12 C0 x X27 C0 x X20 0 0 0 0 0 0 0 +C15 x X12 C0 x X21 0 0 0 0 0 0 0 +C15 x X14 HSP43891 Single DF Configuration Decimation/Resampling Using a single DF, a filter of length L>8 can be constructed by processing in L/8 passes, as illustrated in Table 2, for a 16-tap FIR. Each pass is composed of Tp = 7 + L cycles and computes eight output samples. In pass i, the sample with indices i*8 to i*8 +(L-1) enter the DIN0-8 inputs. The coefficients C0 - CL - 1 enter the CIN0-8 inputs, followed by seven zeros. As these zeros are entered, the result samples are output and the accumulators reset. Initial filing of the pipeline is not shown in this sequence table. Filter outputs can be put through a FIFO to even out the sample rate. The HSP43891 DF provides a mechanism for decimating by factors of 2, 3, or 4. From the DF filter cell block diagram (Figure 1), note the three D registers and two multiplexers in the coefficient path through the cell. These allow the coefficients to be delayed by 1, 2, or 3 clocks through the cell. The sequence table (Table 3) for a decimate-by-two filter illustrates the technique (internal cell pipelining ignored for simplicity). Detailed timing for a 30MHz input sample rate, 15MHz output sample rate (i.e., decimate-by-two), 16-tap FIR filter, including pipelining, is shown in Figure 7. This filter requires only a single HSP43891 DF. Extended Coefficient and Data Sample Word Size The sample and coefficient word size can be extended by utilizing several DFs in parallel to get the maximum sample rate or a single DF with resulting lower sample rates. The technique is to compute partial products of 9 x 9 and combine these partial products by shifting and adding to obtain the final result. The shifting and adding can be accomplished with external adders (at full speed) or with the DF’s shift-and-add mechanism contained in its output stage (at reduced speed). 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLK RESET DF0 ERASE DF1 ERASE 13 DIN0-8 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 CIN0-8 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 CIENB 0 ADR0-2 DF0 SUM0-25 1 2 3 4 5 6 7 0 1 2 4 5 6 7 0 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 SHADD DF0 SENBL/H DF1 SENBL/H 0 15 ∑ 2 3 Y31 Y32 Y33 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 YN = 1 CK XN –K K=0 FIGURE 6. HSP43891 16-TAP 30MHz FILTER TIMING USING TWO CASCADED HSP43891s HSP43891 DF1 SUM0-25 DCM0-1 3 HSP43891 TABLE 3. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT DATA SEQUENCE INPUT . . . X2, X1, X0 COEFFICIENT SEQUENCE INPUT . . . C15, C0 . . . C13, C14, C15 HSP43891 . . . Y19, - ,Y17, - , Y15 CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR 6 C15 x X0 0 0 0 0 0 0 0 - 7 +C14 x X1 0 0 0 0 0 0 0 - 8 +C13 x X2 C15 x X2 0 0 0 0 0 0 - 9 +C12 x X3 +C14 x X3 0 0 0 0 0 0 - 10 +C11 x X4 +C13 x X4 C15 x X4 0 0 0 0 0 - 11 +C10 x X5 +C12 x X5 +C14 x X5 0 0 0 0 0 - 12 +C9 x X6 +C11 x X6 +C13 x X6 C15 x X6 0 0 0 0 - 13 +C8 x X7 +C10 x X7 +C12 x X7 +C14 x X7 0 0 0 0 - 14 +C7 x X8 +C9 x X8 +C11 x X8 +C13 x X8 C15 x X8 0 0 0 - 15 +C6 x X9 +C8 x X9 +C10 x X9 +C12 x X9 +C14 x X9 0 0 0 - 16 +C5 x X10 +C7 x X10 +C9 x X10 +C11 x X10 +C13 x X10 C15 x X10 0 0 - 17 +C4 x X11 +C6 x X11 +C8 x X11 +C10 x X11 +C12 x X11 +C14 x X11 0 0 - 18 +C3 x X12 +C5 x X12 +C7 x X12 +C9 x X12 +C11 x X12 +C13 x X12 C15 x X12 0 - 19 +C2 x X13 +C4 x X13 +C6 x X13 +C8 x X13 +C10 x X13 +C12 x X13 +C14 x X13 0 - 20 +C1 x X14 +C3 x X14 +C5 x X14 +C7 x X14 +C9 x X14 +C11 x X14 +C13 x X14 C15 x X14 - 21 +C0 x X15 +C2 x X15 +C4 x X15 +C6 x X15 +C8 x X15 +C10 x X15 +C12 x X15 +C14 x X15 Cell0 (Y15) 22 C15 x X16 +C1 x X16 +C3 x X16 +C5 x X16 +C7 x X16 +C9 x X16 +C11 x X16 +C13 x X16 - 23 +C14 x X17 +C0 x X17 +C2 x X17 +C4 x X17 +C6 x X17 +C8 x X17 +C10 x X17 +C12 x X17 Cell1 (Y17) 24 +C13 x X18 C15 x X18 +C1 x X18 +C3 x X18 +C5 x X18 +C7 x X18 +C9 x X18 +C11 x X18 - 25 +C12 x X19 +C14 x X19 +C0 x X19 +C2 x X19 +C4 x X19 +C6 x X19 +C8 x X19 +C10 x X19 Cell2 (Y19) 26 +C11 x X20 +C13 x X20 C15 x X20 +C1 x X20 +C3 x X20 +C5 x X20 +C7 x X20 +C9 x X20 - 27 +C10 x X21 +C12 x X21 +C14 x X21 +C0 x X21 +C2 x X21 +C4 x X21 +C6 x X21 +C8 x X21 Cell3 (Y21) 28 +C9 x X22 +C11 x X22 +C13 x X22 C15 x X22 +C1 x X22 +C3 x X22 +C5 x X22 +C7 x X22 - 29 +C8 x X23 +C10 x X23 +C12 x X23 +C14 x X23 +C0 x X23 +C2 x X23 +C4 x X23 +C6 x X23 Cell4 (Y23) 30 +C7 x X24 +C9 x X24 +C11 x X24 +C13 x X24 +C15 x X24 +C1 x X24 +C3 x X24 +C5 x X24 - 31 +C6 x X25 +C8 x X25 +C10 x X25 +C12 x X25 +C14 x X25 +C0 x X25 +C2 x X25 +C4 x X25 Cell5 (Y25) 32 +C5 x X26 +C7 x X26 +C9 x X26 +C11 x X26 +C13 x X26 +C15 x X26 +C1 x X26 +C3 x X26 - 33 +C4 x X27 +C6 x X27 +C8 x X27 +C10 x X27 +C12 x X27 +C14 x X27 +C0 x X27 +C2 x X27 Cell6 (Y27) 34 +C3 x X28 +C5 x X28 +C7 x X28 +C9 x X28 +C11 x X28 +C13 x X28 +C15 x X28 +C1 x X28 - 35 +C2 x X29 +C4 x X29 +C6 x X29 +C8 x X29 +C10 x X29 +C12 x X29 +C14 x X29 +C0 x X29 Cell7 (Y29) 36 +C1 x X30 +C3 x X30 +C5 x X30 +C7 x X30 +C9 x X30 +C11 x X30 +C13 x X30 C15 x X30 - 37 +C0 x X31 +C2 x X31 +C4 x X31 +C6 x X31 +C8 x X31 +C10 x X31 +C12 x X31 +C14 x X31 Cell8 (Y31) 14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLK RESET ERASE 15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 DIN0-8 DIENB C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 CIN0-8 CIENB 0 ADR0-2 DF0 SUM0-25 Y15 1 Y17 2 Y19 3 Y21 4 Y23 Y25 6 Y27 7 Y29 0 Y31 1 Y33 HSP43891 SHADD SENBL SENBH DCM0-1 5 1 FIGURE 7. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz IN, 15MHz OUT HSP43891 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to VCC +0.5V Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Junction Temperature PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Thermal Resistance (Typical, Note 1) θJA (oC/W)θJC (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . 47 N/A PLCC Package. . . . . . . . . . . . . . . . . . . . . 37 N/A CPGA Package . . . . . . . . . . . . . . . . . . . . 34.66 7.78 Typical Package Power Dissipation at 70oC MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7W PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2W CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.88W Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17763 (PLCC MQFP Lead Tips Only) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5 Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current ICCOP VCC = Max, CLK Frequency 20MHz (Notes 2, 4) - 140 mA Standby Power Supply Current ICCSB VCC = Max (Note 4) - 500 µA Input Leakage Current II VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 10 µA Logical One Input Voltage VIH VCC = Max 2.0 - V Logical Zero Input Voltage VIL VCC = Min - 0.8 V Logical One Output Voltage VOH IOH = -400µA, VCC = Min 2.6 - V Logical Zero Output Voltage VOL IOL = 2mA, VCC = Min - 0.4 V Clock Input High VIHC VCC = Max 3.0 - V Clock Input Low VILC VCC = Min - 0.8 V CIN CLK Frequency 1MHz All measurements referenced to GND, TA = 25oC (Note 3) - 10 pF - 15 pF - 10 pF - 15 pF Input Capacitance PLCC CPGA Output Capacitance PLCC COUT CPGA NOTES: 2. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz. 3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 4. Output load per test load circuit and CL = 40pF. 16 HSP43891 AC Electrical Specifications PARAMETER VCC = 5V, ±5%, TA = 0oC to 70oC -20 (20MHz) TEST CONDITIONS SYMBOL -25 (25.6MHz) -30 (30MHz) MIN MAX MIN MAX MIN MAX UNITS Clock Period tCP 50 - 39 - 33 - ns Clock Low tCL 20 - 16 - 13 - ns Clock High tCH 20 - 16 - 13 - ns Input Setup tIS 16 - 14 - 13 - ns Input Hold tIH 0 - 0 - 0 - ns CLK to Coefficient Output Delay tODC - 24 - 20 - 18 ns Output Enable Delay tOED - 20 - 15 - 15 ns Output Disable Delay tODD - 20 - 15 - 15 ns CLK to SUM Output Delay tODS - 27 - 25 - 21 ns Output Rise tOR Note 5 - 6 - 6 - 6 ns Output Fall tOF Note 5 - 6 - 6 - 6 ns Note 5 NOTE: 5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. Test Load Circuit S1 DUT † CL IOH ± 1.5V (NOTE) INCLUDES STRAY AND JIG CAPACITANCE EQUIVALENT CIRCUIT NOTE: Switch S1 Open for ICCSB and ICCOP Tests. 17 IOL HSP43891 Waveforms 4.0V 2.0V tCH 2.0V 0.0V CLK tCP tIS tCL 2.0V 3.0V INPUT† 0.0V 2.0V CLK tIH 1.5V 1.5V NOTE: Input includes:DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RESET, DCM0-1, ADR0-1, TCS, TCCI, SHADD FIGURE 9. INPUT SETUP AND HOLD FIGURE 8. CLOCK AC PARAMETERS 2.0 0.8 2.0V CLK tODC, tODS 1.5V OUTPUT FIGURE 10. SUM0-25, COUT0-8, OUTPUT DELAYS ENABLE tOF tOR SUM0-25 COUT0-8 1.5V FIGURE 11. RISE AND FALL TIMES 3.0V INPUT 0.0V 1.5V tOED 1.5V DEVICE UNDER TEST 1.5V tODD 1.7V OUTPUT 1.5V 1.3V NOTE: AC Testing: Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are made at 1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and measured at 2.0V. FIGURE 12. OUTPUT ENABLE, DISABLE TIMING FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 18 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029

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