LOGIC LF2250QC20

LF2250
LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
12 x 10-bit Matrix Multiplier
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 50 MHz Data and Computation
Rate
❑ Nine Multiplier Array with 12-bit
Data and 10-bit Coefficient Inputs
❑ Separate 16-bit Cascade Input and
Output Ports
❑ On-board Coefficient Storage
❑ Four User-Selectable Filtering and
Transformation Functions:
• 3 x 3 Matrix Multiplier
• Cascadable 9-Tap FIR Filter
• Cascadable 3 x 3 Convolver
• Cascadable 4 x 2 Convolver
❑ Replaces TRW/Raytheon/
Fairchild TMC2250
❑ 120-pin PQFP
The LF2250 is a high-speed matrix
multiplier consisting of an array of
nine 12 x 10-bit multipliers. Internal
summing adders are also included to
provide the configurations needed to
implement matrix multiplications,
cascadable FIR filters, and pixel
convolvers.
The 3 x 3 matrix multiplier (triple dot
product) configuration of the LF2250
allows users to easily perform threedimensional perspective translations or
video format conversions at real-time
video rates. By using the LF2250 in
this configuration, conversions can be
made from the RGB (color component)
format to the YIQ (quadrature encoded
chrominance) or YUV (color difference) formats and vice versa (YIQ or
YUV to RGB).
In addition to color space conversions,
the LF2250 offers a range of selectable
configurations designed for filtering
applications. When configured as a
9-tap FIR filter, the LF2250 automatically
selects the necessary internal bus
structure and inserts the appropriate
data path delay elements. In addition,
a 16-bit cascade input port allows for
the creation of larger filters without a
reduction in throughput.
Real-time video image filtering using
the convolver modes of the LF2250 can
provide edge detection, texture
enhancement, and detail smoothing.
Both pixel convolver configurations,
3 x 3 and 4 x 2, deliver high-speed data
manipulation in a single chip solution.
By using the 16-bit cascade input port
to cascade two devices, cubic convolutions (4 x 4-pixel) can be easily accommodated with no decrease in throughput rates.
All inputs and outputs, as well as all
control lines, are registered on the
rising edge of clock. The LF2250
operates at clock rates up to 50 MHz
over the full commercial temperature
and supply voltage ranges.
LF2250 BLOCK DIAGRAM
CLK
MODE1-0
12
DATA
INPUTS
{
A11-0
B11-0
C11-0
12
4
12
4
12
4
12
COEFFICIENT
INPUTS
{
KA9-0
KB9-0
KC9-0
DATA
OUTPUTS
CASCADE
PORTS
PIN
NAME
X11-0
CASIN15-4
Y11-8
CASIN3-0
{
2
{
{
CWE1-0
2
XC11-0
YC11-8
Y7-4
Y7-4
Y3-0
CASOUT3-0
YC3-0
Z11-0
CASOUT15-4
ZC11-0
10
10
9-MULTIPLIER
ARRAY
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
TABLE 1. MODE SELECTION
MODE1-0
OPERATING MODE
00
3 x 3 Matrix Multiplier
01
9-Tap FIR Filter
10
3 x 3 Convolver
11
4 x 2 Convolver
OPERATING MODES
The LF2250 can realize four different
user-selectable digital filtering architectures as determined by the state of the
mode (MODE1-0) inputs. Upon
selection of the desired function, the
LF2250 automatically chooses the
appropriate internal data paths and
input/output bus structure. Table 1
details the modes of operation.
DATA FORMATTING
The coefficient input ports (KA, KB,
KC) are 10-bit fractional two’s complement format regardless of the operating
mode. The data input ports (A, B, C)
are 12-bit integer two’s complement
format regardless of the operating
mode.
In the matrix multiplier mode (Mode
00), the data output ports (X, Y, Z) are
12-bit integer two’s complement
format. In the FIR filter and convolver
modes (Modes 01, 10, 11), the X, Y, and
Z ports are configured as the cascade-in
(CASIN15-0) and cascade-out
(CASOUT15-0) ports. These ports
assume 16-bit (12-bit integer, 4-bit
fractional) two’s complement data on
both the inputs and outputs. Table 2
shows the data port formatting for
each of the four operating modes.
TABLE 2.
BIT WEIGHTING
SIGNAL DEFINITIONS
The internal sum of products of the
LF2250 can grow to 23 bits. However,
in order to keep the output format of
the matrix multiply mode (Mode 00)
identical to the input format, the X, Y,
and Z outputs are truncated to 12-bit
integer words. In the filter modes
(Modes 01, 10, 11), the cascade output
is always half-LSB rounded to 16 bits
(12 integer bits and 4 fractional bits).
The user may half-LSB round the
output to any size less than 16 bits by
simply forcing a “1” into the bit
position of the cascade input immediately below the desired LSB. For
example, if half-LSB rounding to 12
bits is desired, then a “1” must be
forced into the CASIN3 bit position
(CASOUT4 would then be the LSB).
Power
In all four modes, the user may adjust
the bit weighting, by applying an
identical scaling correction factor to
both the input and output data
streams. If the coefficients are rescaled, then the relative weightings of
the cascade-in and cascade-out ports
will differ accordingly. Figure 1
illustrates the input and output bit
weightings for all four modes.
DATA OVERFLOW
Because the LF2250’s matched input
and output data formats accommodate
unity gain (0 dB), input conditions that
could lead to numeric overflow may
exist. To ensure that no overflow
conditions occur, the user must be
aware of the maximum input data and
coefficient word sizes allowable for
each specific algorithm being performed.
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers. All timing specifications are referenced to the rising
edge of CLK.
Inputs
A11-0, B11-0, C11-0 — Data Inputs
A, B, and C are the 12-bit registered
data input ports. Data presented to
these ports is latched into the multiplier input registers for the current
operating mode (Table 1). In the filter
modes (Modes 01, 10, 11), the rising
edge of CLK internally right-shifts
new data to the next filter tap.
KA9-0, KB9-0, KC9-0 — Coefficient Inputs
KA, KB, and KC are the 10-bit registered coefficient input ports. Data
presented to these ports is latched
into the corresponding internal
coefficient register set defined by
CWE1-0 (Table 4) on the next rising
edge of CLK. Table 3 shows which
coefficient registers are available for
each coefficient input port.
DATA PORT FORMATTING
PIN NAMES
MODE1-0
A11-0
B11-0
C11-0
KA9-0
KB9-0
KC9-0
XC11-0
YC11-8
Y7-4
YC3-0
ZC11-0
00
A11-0
B11-0
C11-0
KA9-0
KB9-0
KC9-0
X11-0
Y11-8
Y7-4
Y3-0
Z11-0
01
A11-0
A11-0
NC
KA9-0
KB9-0
KC9-0
CASIN15-4
CASIN3-0
NC
CASOUT3-0
CASOUT15-4
10
A11-0
B11-0
C11-0
KA9-0
KB9-0
KC9-0
CASIN15-4
CASIN3-0
NC
CASOUT3-0
CASOUT15-4
11
A11-0
B11-0
NC
KA9-0
KB9-0
KC9-0
CASIN15-4
CASIN3-0
NC
CASOUT3-0
CASOUT15-4
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DEVICES INCORPORATED
FIGURE 1A.
12 x 10-bit Matrix Multiplier
CASOUT15-0 — Cascade Output
INPUT FORMATS
Data Input (All Modes)
11 10 9 8 7
–211 210 29 28 27
6 5 4 3 2 1 0
26 25 24 23 22 21 20
(Sign)
Coefficient Input (All Modes)
9 8 7 6 5 4 3 2 1 0
–20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9
(Sign)
Cascade Input (Modes 01, 10, 11)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–211 210 29 28 27 26 25 24 23 22 21 20 2–1 2–2 2–3 2–4
In the filter modes (Modes 01, 10, 11),
the 12-bit Z port and four bits of the Y
port are internally reconfigured as the
16-bit registered cascade output port.
NOTE: The X, Y, and Z ports are
automatically reconfigured by the LF2250
as the cascade-in and cascade-out ports as
required for each operating mode.
Because both the X and Z ports are used
for the cascade ports, all X port pins and
all Z port pins are labelled as XC and
ZC, respectively. All Y port pins that are
used for the cascade ports are labelled as
YC. Those Y port pins which are not
used for the cascade ports are labelled as
Y.
(Sign)
Controls
Internal Sum (All Modes)
20 19 18 17
–211 210 29 28
MODE1-0 — Mode Select
3 2 1 0
2–6 2–7 2–8 2–9
(Sign)
FIGURE 1B.
OUTPUT FORMATS
Result (Mode 00)
11 10 9 8 7
–211 210 29 28 27
6 5 4 3 2 1 0
26 25 24 23 22 21 20
(Sign)
The registered mode select inputs
determine the operating mode of the
LF2250 (Table 1) for data being input
on the next clock cycle. When switching between modes, the internal
pipeline latencies of the device must
be observed. After switching operating modes, the user must allow
enough clock cycles to pass to flush
the internal registers before valid data
will appear on the outputs.
CWE1-0 — Coefficient Write Enable
Cascade Out (Modes 01, 10, 11)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–211 210 29 28 27 26 25 24 23 22 21 20 2–1 2–2 2–3 2–4
(Sign)
CASIN15-0 — Cascade Input
Outputs
In the filter modes (Modes 01, 10, 11),
the 12-bit X port and four bits of the Y
port are internally reconfigured as the
16-bit registered cascade input port.
Data presented to this port will be
added to the internal sum of products.
X11-0, Y11-0, Z11-0 — Data Outputs
The registered coefficient write enable
inputs determine which internal
coefficient register set to update
(Table 4) on the next clock cycle.
TABLE 3.
X, Y, and Z are the 12-bit registered
output ports for the matrix multiply
mode (Mode 00). These ports are
automatically reconfigured for the
filter modes (Modes 01, 10, 11) as the
cascade-in and cascade-out ports.
COEFFICIENT INPUTS
INPUT PORT
REG. AVAILABLE
KA
KA1, KA2, KA3
KB
KB1, KB2, KB3
KC
KC1, KC2, KC3
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LF2250
DEVICES INCORPORATED
TABLE 4.
CWE1-0
COEFF. REG. UPDATE
COEFFICIENT SET
00
Hold All Registers
01
KA1, KB1, KC1
10
KA2, KB2, KC2
11
KA3, KB3, KC3
DETAILS OF OPERATION
3 x 3 Matrix Multiplier — Mode 00
In this mode, all three input ports (A,
B, C) and all three output ports (X, Y,
Z) are utilized to implement a 3 x 3
matrix multiplication (triple dot
product). Each rounded 12-bit output
is the sum of all three input words
multiplied by the appropriate coefficients (Table 5). The pipeline latency
for this mode is five clock cycles.
Therefore, the sum of products will
be output five clock cycles after the
input data has been latched. New
output data is subsequently available
every clock cycle thereafter.
12 x 10-bit Matrix Multiplier
(comprising of the summation of the
multiplications of the last nine data
inputs with their related coefficients)
becomes available (Table 5). The
CASIN term is also added to each
new output. The internal bus structure and pipeline delays allow new
input data to be added every cycle
while maintaining the structure of the
filtering operation. This addition of
new data every cycle produces the
effect of the convolution window
moving to the next pixel column.
TABLE 5.
4 x 2-Pixel Convolver — Mode 11
Using the A and B ports, input data is
loaded and multiplied by the onboard coefficients. These products
are then summed with the CASIN
data and rounded to create the 16-bit
output. The cascade ports allow
multiple devices to be used together
for use with larger kernels. As with
Mode 10, each cycle results in a 16-bit
output created from the products and
summations performed.
LATENCY EQUATIONS
3 x 3 Matrix Multiplier — Mode 00
X(n+4) = A(n)KA1(n) + B(n)KB1(n)
+ C(n)KC1(n)
Y(n+4) = A(n)KA2(n) + B(n)KB2(n)
+ C(n)KC2(n)
Z(n+4)
+ C(n)KC3(n)
= A(n)KA3(n) + B(n)KB3(n)
9-Tap FIR Filter — Mode 01
CASOUT(n+12)
= A(n+8)KA3(n+8) + A(n+7)KA2(n+7) + A(n+6)KA1(n+6)
+ B(n+5)KB3(n+8) + B(n+4)KB2(n+7) + B(n+3)KB1(n+6)
9-Tap FIR Filter — Mode 01
+ B(n+2)KC3(n+8) + B(n+1)KC2(n+7) + B(n)KC1(n+6)
This mode utilizes the 12-bit A and B
data input ports as well as the 16-bit
CASIN port. The input data should
be presented to the A and B ports
simultaneously. The resulting 9sample response, which is half-LSB
rounded to 16 bits, begins after five
clock cycles and ends after 13 clock
cycles (Table 5). The pipeline latency
from the input of an impulse response
to the center of the output response is
nine clock cycles. The latency from
the CASIN port to the CASOUT port
is four clock cycles. New output data
is available every clock cycle.
+ CASIN(n+9)
3 x 3-Pixel Convolver — Mode 10
CASOUT(n+6)
= A(n+2)KA3(n+2) + A(n+1)KA2(n+1) + A(n)KA1(n)
+ B(n+2)KB3(n+2) + B(n+1)KB2(n+1) + B(n)KB1(n)
+ C(n+2)KC3(n+2) + C(n+1)KC2(n+1) + C(n)KC1(n)
+ CASIN(n+3)
4 x 2-Pixel Convolver — Mode 11
CASOUT(n+7)
= A(n+3)KA3(n+3) + A(n+2)KA2(n+2) + A(n+1)KA1(n+1)
+ A(n)KC3(n+3)
+ B(n+3)KB3(n+3) + B(n+2)KB2(n+2)
3 x 3-Pixel Convolver — Mode 10
+ B(n+1)KB1(n+1) + B(n)KC1(n+1)
When configured in this mode, line
delayed data is loaded through the A,
B, and C input ports. During each
cycle, a new rounded 16-bit output
+ CASIN(n+4)
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
FIGURE 2. 3 X 3 MATRIX MULTIPLIER — MODE 00
A
12
KA1
KA
KA2
KA3
10
21
B
21
12
KB1
KB
KB2
21
21
12
KC1
KC
KB3
10
21
C
21
KC2
KC3
10
21
21
12 (MSB)
21
12 (MSB)
X
12 (MSB)
Y
Z
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DEVICES INCORPORATED
FIGURE 3.
12 x 10-bit Matrix Multiplier
9-TAP FIR FILTER — MODE 01
A
12
KA1
KA
KA2
21
B
12
21
21
4
KB1
KB
KA3
10
KB2
KB3
10
3
21
21
KC1
KC
KC2
KC3
10
21
CASIN
21
16
16
21
21
21
21
5
100002
(HALF-LSB ROUNDING)
16 (MSB)
NOTE: NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS
CASOUT
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
FIGURE 4. 3 X 3-PIXEL CONVOLVER — MODE 10
A
12
KA1
KA
KA2
21
B
21
KB2
21
KC2
KC3
10
21
CASIN
21
12
KC1
KC
KB3
10
21
C
21
12
KB1
KB
KA3
10
16
16
21
21
21
21
5
100002
(HALF-LSB ROUNDING)
16 (MSB)
CASOUT
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LF2250
DEVICES INCORPORATED
FIGURE 5.
A
12 x 10-bit Matrix Multiplier
4 X 2-PIXEL CONVOLVER — MODE 11
12
3
KA1
KA
KA2
21
B
21
21
12
KB1
KB
KA3
10
KB2
KB3
10
21
21
21
0
KC1
KC
KC2
21
CASIN
KC3
10
16
16
21
21
21
21
5
100002
(HALF-LSB ROUNDING)
16 (MSB)
NOTE: NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS
CASOUT
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
–55°C to +125°C
4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
Vcc = Min., IOH = –2.0 mA
VOL
Output Low Voltage
Vcc = Min., IOL = 4.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
2.4
Unit
V
0.4
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±10
µA
Output Leakage Current
(Note 12)
±40
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
160
mA
ICC2
VCC Current, Quiescent
(Note 7)
12
mA
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
10
pF
COUT
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
Parameter
tCYC
Cycle Time
tPWL
Clock Pulse Width Low
tPWH
Clock Pulse Width High
tS
Input Setup Time
tH
Input Hold Time
tD
Output Delay
LF2250–
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*
33
25
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Min
Max
Min
Max
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33
25
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15
10
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10
10
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8
6
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0
0
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18
16
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20
Min
Max
20
6
8
6
0
15
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
Symbol
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LF2250–
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*
33
25*
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Min
Max
Min
Max
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33
25
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15
10
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10
10
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12
9
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2
2
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25
20
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Parameter
tCYC
Cycle Time
tPWL
Clock Pulse Width Low
tPWH
Clock Pulse Width High
tS
Input Setup Time
tH
Input Hold Time
tD
Output Delay
123456789012345678901234
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*DISCONTINUED SPEED GRADE
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
SWITCHING WAVEFORMS:
3 X 3 MATRIX MULTIPLIER — MODE 00
1
2
3
4
6
5
7
8
CLK
01
CWE1-0
tPWL
tPWH
tS
10
11
Kx1
Kx2
Kx3
0
0
1.0
00
tH
KA, KB, KC
A, B, C
0
0
0
00
MODE1-0
tD
X11-0
KA1 + KB1 + KC1
Y11-0
KA2 + KB2 + KC2
Z11-0
KA3 + KB3 + KC3
SWITCHING WAVEFORMS: 9-TAP FIR FILTER — MODE 01
1
2
12
3
13
14
16
15
17
CLK
CWE1-0
tPWL
tPWH
tS
01
10
11
Kx1
Kx2
Kx3
0
0
1.0
tH
KA, KB, KC
A, B
MODE1-0
0
0
0
0
0
01
Q13
CASIN15-0
tD
KB1
CASOUT15-0
KC3
KC2
KC1
Q13
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
SWITCHING WAVEFORMS: 3 X 3-PIXEL CONVOLVER — MODE 10
1
2
3
7
6
8
9
10
11
CLK
CWE1-0
tPWL
tPWH
tS
01
10
11
Kx1
Kx2
Kx3
0
0
1.0
tH
KA, KB, KC
A, B, C
0
0
0
0
0
0
10
MODE1-0
Q7
CASIN15-0
tD
Q7
CASOUT15-0
KA3 + KB3 + KC3
KA2 + KB2 + KC2
KA1 + KB1 + KC1
SWITCHING WAVEFORMS: 4 X 2-PIXEL CONVOLVER — MODE 11
1
2
3
7
6
8
9
10
11
CLK
CWE1-0
tPWL
tPWH
tS
01
10
11
Kx1
Kx2
Kx3
0
0
1.0
tH
KA, KB, KC
A, B
0
0
0
0
0
0
11
MODE1-0
Q8
CASIN15-0
tD
Q8
CASOUT15-0
KA3 + KB3
KA2 + KB3
KA1 + KB1
KC1 + KC3
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LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of I OH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Never- used. Parasitic capacitance is 30 pF
theless, conventional precautions minimum, and may be distributed.
should be observed during storage,
handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current
electrical stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping testing of this device. The following
of transient undershoot and overshoot. measures are recommended:
Input levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary b. Ground and VCC supply planes
from those designated but operation is must be brought directly to the DUT
guaranteed as specified.
socket or contactor fingers.
5. Supply current for a given application can be accurately approximated
by:
NCV2 F
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.0V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
4
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
N = total number of device outputs
of view of the external system driving
C = capacitive load per output
the chip. Setup time, for example, is
V = supply voltage
specified as a minimum since the exterF = clock frequency
nal system must supply at least that
6. Tested with all outputs changing ev- much time to meet the worst-case reery cycle and no load, at a 20 MHz clock quirements of all parts. Responses
from the internal circuitry are specified
rate.
from the point of view of the device.
7. Tested with all inputs within 0.1 V of Output delay, for example, is specified
VCC or Ground, no load.
as a maximum since worst-case opera8. These parameters are guaranteed tion of any device always provides data
within that time.
but not 100% tested.
where
Video Imaging Products
13
08/16/2000–LDS.2250-L
LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
ORDERING INFORMATION
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
XC7
XC8
VCC
XC9
XC10
XC11
GND
MODE0
MODE1
C11
C10
C9
C8
C7
GND
C6
C5
C4
VCC
C3
C2
C1
C0
B11
B10
B9
B8
B7
B6
B5
120-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Top
View
B4
B3
CLK
B2
B1
B0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
CWE0
CWE1
KA9
KA8
KA7
KA6
KA5
KA4
KA3
KA2
KA1
ZC6
ZC7
ZC8
GND
ZC9
ZC10
ZC11
KC0
KC1
KC2
KC3
GND
KC4
KC5
KC6
VCC
KC7
KC8
KC9
KB0
KB1
KB2
KB3
KB4
KB5
KB6
KB7
KB8
KB9
KA0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
XC6
XC5
XC4
XC3
XC2
XC1
XC0
GND
YC11
YC10
YC9
VCC
YC8
Y7
Y6
GND
Y5
Y4
YC0
VCC
YC1
YC2
YC3
GND
ZC0
ZC1
ZC2
ZC3
ZC4
ZC5
Plastic Quad Flatpack
(Q1)
Speed
0°C
OMMERCIAL
SCREENING
0°Ctoto+70°C
+70°C——CC
OMMERCIAL
SCREENING
LF2250QC25
LF2250QC20
25 ns
20 ns
–55°C
—CCOMMERCIAL
OMMERCIALSS
CREENING
–40°C to
to +125°C
+85°C —
CREENING
–55°C
–55°C to
to +125°C
+125°C —
— MIL-STD-883
MIL-STD-883 C
COMPLIANT
OMPLIANT
Video Imaging Products
14
08/16/2000–LDS.2250-L
LF2250
DEVICES INCORPORATED
12 x 10-bit Matrix Multiplier
ORDERING INFORMATION
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1
2
3
4
5
6
7
8
9
10
11
12
13
120-pin
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
A
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
C8
C7
C5
C3
XC7 XC9 XC10 MODE0 C11
C1
B10
B7
B4
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
B
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
C6
C4
C2
XC4 XC5 XC8 XC11 MODE1 C9
B11
B9
B6
B2
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
C
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
XC1 XC2 XC6 VCC GND C10 GND VCC C0
B8
B5
B3
B1
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
D
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
CLK B0
A10
YC11 XC0 XC3
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
KEY
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
E
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
A11
A9
A8
YC9 YC10 GND
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
F
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Top View
Y7 YC8 VCC
A7
A6
A5
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Through
Package
G
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Y5
Y6 GND
A3
A2
A4
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
(i.e., Component Side Pinout)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
H
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Y4 YC0 VCC
GND A0
A1
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
J
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
KA8 CWE1 CWE0
YC1 YC2 GND
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
K
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
YC3 ZC0 ZC3
KA4 KA7 KA9
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
L
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
ZC1 ZC4 ZC6 GND KC0 GND VCC KB0 KB4 KB8 KA1 KA5 KA6
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
M
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
ZC2 ZC7 ZC9 ZC11 KC2 KC4 KC6 KC9 KB2 KB5 KB9 KA2 KA3
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
N
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
ZC5 ZC8 ZC10 KC1 KC3 KC5 KC7 KC8 KB1 KB3 KB6 KB7 KA0
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Discontinued Package
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Ceramic Pin Grid Array
(G4)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Video Imaging Products
15
08/16/2000–LDS.2250-L