32C408B 4 Megabit (512K x 8-Bit) SRAM A13 A0 A1 1 36 NC A18 A17 A2 CS A16 A15 OE I/O1 I/O2 I/O8 I/O7 A3 A4 32C408B Vcc I/O4 I/O5 WE A5 A14 A13 A6 A12 A7 A8 A11 A10 19 MEMORY MATRIX 1024 ROWS x 4096 COLUMNS A7 A6 A5 A4 DQ0 COLUMN I/O INPUT DATA CONTROL COLUMN DECODER DQ7 A18 A17 A16 A15 A14 A3 A2 A1 A0 DQ0 CS WE OE Memory Vcc I/O6 18 ROW DECODER Vss Vss I/O3 A9 A12 A11 A10 A9 A8 DQ7 NC Logic Diagram FEATURES: DESCRIPTION: • 512k x 8-bit CMOS architecture • RAD-PAK® technology hardened against natural space radiation • Total dose hardness: - > 100 krad (Si), depending upon space mission • Single event effect: - SELTH: > 68 MeV/mg/cm2 - SEUTH: < 3MeV/mg/cm2 - SEU saturated cross section: 6E-9 cm2/bit • Package: -36 pin RAD-PAK® flat pack • Fast propagation time: -20, 25, 30 ns maximum access time • Single 5V + 10% power supply • Low power dissipation: - Standby: 60mA (TTL); 10mA (CMOS) - Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30 ns) • TTL compatible inputs and outputs • Fully static operation - No clock or refresh required • Three state outputs Maxwell Technologies’ 32C408B high-speed 4 Megabit SRAM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. Using RAD-PAK® packaging technology, the 32C408B realizes higher density, higher performance and lower power consumption, and is well suited for high-speed system application. Its fully static design eliminates the need for external clocks, while the CMOS circuitry reduces power consumption and provides higher reliability. The 32C408B is equipped with eight common input/ output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. Maxwell Technologies' patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. In a GEO orbit, RAD-PAK can provides true greater than 100 krad (Si) total radiation dose tolerance; dependent upon space mission. The patented radiation-hardened RAD-PAK technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. This product is available with packaging and screening up to Class S. 05.02.02 Rev 7 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com All data sheets are subject to change without notice 1 ©2002 Maxwell Technologies All rights reserved. 32C408B 4 Megabit (512K x 8-Bit) SRAM TABLE 1. 32C408B ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNIT VIN, VOUT -0.5 VCC+0.5 V Voltage on VCC supply relative to VSS VCC -0.5 7.0 V Power Dissipation PD -- 1.0 W Storage Temperature TS -65 +150 °C Operating Temperature TA -55 +125 °C Voltage on any pin relative to VSS TABLE 2. 32C408B RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Ground SYMBOL MIN MAX UNIT VCC 4.5 5.5 V 0 0 V Input High Voltage VIH 2.2 VCC+0.5 V Input Low Voltage 2 VIL -0.5 0.8 V -- 0.63 °C/W ΘJC Thermal Impedance Memory VSS 1 1. VIH(max) = VCC + 2.0V ac(pulse width < 10ns) for I < 20mA. 2. VIL (min) = -2.0V ac(pulse width < 10ns) for I < 20mA. TABLE 3. 32C408B DC ELECTRICAL CHARACTERISTICS (VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED PARAMETER CONDITION SYMBOL SUBGROUPS MIN TYP MAX UNIT Input Leakage Current VIN = VSS to VCC ILI 1, 2, 3 -2 -- 2 µA Output Leakage Current CS=VIH or OE=VIH or WE=VIL, VOUT =VSS to VCC ILO 1, 2, 3 -2 -- 2 µA Output Low Voltage IOL = 8mA VOL 1, 2, 3 -- -- 0.4 V Output High Voltage IOH = -4mA VOH 1, 2, 3 2.4 -- V Average Operating Cur- Min cycle, 100% Duty, CS=VIL, IOUT=0mA, VIN = VIH or VIL rent -20 -25 -30 ICC 1, 2, 3 Standby Power Supply Current CS = VIH ISB 1, 2, 3 -- -- 60 f = 0MHz, CS > VCC - 02V, VIN > VCC - 0.2V or VIN < 0.2V ISB1 1, 2, 3 -- -- 10 VIN = 0V, f = 1MHz, TA = 25 °C. CIN 1, 2, 3 -- -- 7 pF VI/O = 0V CI/O 1, 2, 3 -- -- 8 pF Input Capacitance1 Output Capacitance1 1. Guaranteed by Design 05.02.02 Rev 7 mA -180 170 160 ---- All data sheets are subject to change without notice mA 2 ©2002 Maxwell Technologies All rights reserved. 32C408B 4 Megabit (512K x 8-Bit) SRAM TABLE 4. 32C408B AC CHARACTERISTICS FOR READ CYCLE (VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED PARAMETER SYMBOL SUBGROUPS Read Cycle Time -20 -25 -30 tRC 9, 10, 11 Address Access Time -20 -25 -30 tAA Chip Select Access Time -20 -25 -30 tCO Output Enable to Output Valid -20 -25 -30 tOE Chip Select to Output in Low-Z -20 -25 -30 tLZ Output Enable to Output in Low-Z -20 -25 -30 tOLZ Chip Deselect to Output in High-Z -20 -25 -30 tHZ Output Disable to Output in High-Z -20 -25 -30 tOHZ Output Hold from Address Change -20 -25 -30 tOH Chip Select to Power Up Time -20 -25 -30 tPU Chip Select to Power Down Time -20 -25 -30 tPD MIN TYP MAX 20 25 30 ---- ---- ---- ---- 20 25 30 ---- ---- 20 25 30 ---- ---- 10 12 14 ---- 3 3 3 ---- ---- 0 0 0 ---- ---- 5 6 8 ---- ---- 5 6 8 ---- 3 5 5 ---- ---- ---- 0 0 0 ---- ---- 10 15 20 ---- UNIT ns ns 9, 10, 11 ns 9, 10, 11 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 All data sheets are subject to change without notice 3 ©2002 Maxwell Technologies All rights reserved. Memory ns 9, 10, 11 05.02.02 Rev 7 ns 32C408B 4 Megabit (512K x 8-Bit) SRAM TABLE 5. 32408B FUNCTIONAL DESCRIPTION 1 CS WE OE MODE I/O PIN SUPPLY CURRENT H X X Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC 1. X = don’t care. TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE (VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED PARAMETER SUBGROUPS Write Cycle Time -20 -25 -30 tWC 9, 10, 11 Chip Select to End of Write -20 -25 -30 tCW Address Setup Time -20 -25 -30 tAS Address Valid to End of Write -20 -25 -30 tAW Write Pulse Width (OE High) -20 -25 -30 tWP Write Recovery Time -20 -25 -30 tWR Write to Output in High-Z -20 -25 -30 tWHZ MIN TYP MAX 20 25 30 ---- ---- 14 15 17 ---- ---- 0 0 0 ---- ---- 14 15 17 ---- ---- 14 15 17 ---- ---- 0 0 0 ---- ---- ---- 5 5 6 ---- ns ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 05.02.02 Rev 7 UNIT All data sheets are subject to change without notice 4 ©2002 Maxwell Technologies All rights reserved. Memory SYMBOL 32C408B 4 Megabit (512K x 8-Bit) SRAM TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE (VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED PARAMETER SYMBOL SUBGROUPS Write Pulse Width(OE Low) -20 -25 -30 tWP1 9, 10, 11 Data to Write Time Overlap -20 -25 -30 tDW End Write to Output Low-Z 1 -20 -25 -30 tOW tDH TYP MAX ---- 20 25 30 ---- 9 10 11 ---- ---- ---- 6 7 8 ---- 0 0 0 ---- ---- UNIT ns ns 9, 10, 11 ns 9, 10, 11 9, 10, 11 ns Memory Data Hold from Write Time -20 -25 -30 MIN FIGURE 1. TIMING WAVEFORM OF WRITE CYCLE(1) (OE CLOCK) 05.02.02 Rev 7 All data sheets are subject to change without notice 5 ©2002 Maxwell Technologies All rights reserved. 32C408B 4 Megabit (512K x 8-Bit) SRAM FIGURE 2. TIMING WAVEFORM OF WRITE CYCLE (OE LOW FIXED) 1. All write cycle timing is referenced from the last valid address to the first transition address. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10.When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FIGURE 3. TIMING WAVEFORM OF READ CYCLE(1) (ADDRESS CONTROLLED, CS = OE = VIL, WE = VIH) 05.02.02 Rev 7 All data sheets are subject to change without notice 6 ©2002 Maxwell Technologies All rights reserved. Memory 2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low: A write ends at the earliest transition among CS going high or WE going high. tWP is measured from beginning of write to end of write. 32C408B 4 Megabit (512K x 8-Bit) SRAM FIGURE 4. TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. Memory 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and from device to device. 5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention is necessary during read and write cycle. FIGURE 5. SRAM HEAVY ION CROSS SECTION 05.02.02 Rev 7 All data sheets are subject to change without notice 7 ©2002 Maxwell Technologies All rights reserved. 32C408B 4 Megabit (512K x 8-Bit) SRAM FIGURE 6. SRAM PROTON SEU CROSS SECTION STATIC Memory 05.02.02 Rev 7 All data sheets are subject to change without notice 8 ©2002 Maxwell Technologies All rights reserved. 32C408B 4 Megabit (512K x 8-Bit) SRAM Memory 36 PIN FLAT RAD-PAK® PACKAGE DIMENSION SYMBOL MIN NOM MAX A 0.122 0.135 0.148 b 0.015 0.017 0.019 c 0.008 0.010 0.012 D -- 0.930 0.940 E 0.638 0.645 0.652 E1 -- -- 0.690 E2 0.560 0.565 -- E3 0.005 0.040 -- e 0.050 BSC L 0.390 0.400 0.410 Q 0.088 0.098 0.108 S1 0.005 0.032 -- N 36 F36-01 Note: All dimensions in inches 05.02.02 Rev 7 All data sheets are subject to change without notice 9 ©2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM 32C408B Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 05.02.02 Rev 7 All data sheets are subject to change without notice 10 ©2002 Maxwell Technologies All rights reserved. 32C408B 4 Megabit (512K x 8-Bit) SRAM Product Ordering Options Model Number 32C408B XX F X -XX Option Details Feature 20 = 20 ns 25 = 25 ns 30 = 30 ns Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25°C) I = Industrial (testing @ -55°C, +25°C, +125°C) Package F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature CMOS 512kword x 8-bit Static RAM 05.02.02 Rev 7 All data sheets are subject to change without notice Memory Access Time 11 ©2002 Maxwell Technologies All rights reserved.