SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 D D D D Compatible With IEEE Std 1194.1-1991 (BTL) LVTTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage D D D D D High-Impedance State During Power Up and Power Down Selectable Clock Delay TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal Packaged in Plastic High-Power Low-Profile Quad Flatpack 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1AI5 1AO5 1AI4 1AO4 GND 1AI3 1AO3 1AI2 1AO2 GND 1AI1 1AO1 VCC (5 V) 1OEA 1OEA 1LEBA 1CLKBA 1CLKAB 1LEAB 1OEB 1OEB VREF BG V CC BG GND/GND 1B1 PCA PACKAGE (TOP VIEW) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1B2 GND 1B3 1B4 GND 1B5 1B6 GND 1B7 1B8 GND 1B9 2SEL2 2CLKAB GND 2B2 2B3 GND 2B4 2B5 GND 2B6 2B7 GND 2B8 2AO5 2AI5 2AO6 2AI6 GND 2AO7 2AI7 2AO8 2AI8 GND 2AO9 2AI9 V CC (5 V) 2OEA 2OEA 2LEBA 2CLKBA 2CLKAB 2LEAB 2OEB 2OEB BIAS V CC 2SEL1 GND 2B9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC(3.3 V) VCC(5 V) GND 1AO6 1AI6 1AO7 1AI7 GND 1AO8 1AI8 1AO9 1AI9 GND 2CLK VCC(3.3 V) 2AO2 2AI2 GND 2AO3 2AI3 2AO4 2AI4 GND VCC(5 V) VCC(3.3 V) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 description The SN74FB1653 device contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. It is specifically designed to be compatible with IEEE Std 1194.1-1991 (BTL). The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) is typically less than 2.5 V, the A outputs are in the high-impedance state. The B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC(5 V) is typically less than 2.5 V, the B port is turned off. The clock-select inputs (2SEL1 and 2SEL2) are used to configure the TTL-to-BTL clock paths and delays. Refer to the Mux-Mode Delay table. BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected. BG VCC and BG GND are the supply inputs for the bias generator. VREF is used to bypass the internal threshold reference voltage of the device. It is recommended that this pin be decoupled with a 0.1-µF capacitor. Enhanced heat-dissipation techniques should be used when operating this device from: (a) AI to A0 at frequencies greater than 50 MHz, or (b) AI to B, or B to A0 at frequencies greater than 100 MHz. The SN74FB1653 is characterized for operation from 0°C to 70°C. Function Tables TRANSCEIVER INPUTS FUNCTION OEA OEA OEB OEB X X H L L H X X B data to A bus L H H L A data to B bus, B data to A bus X X L X X X X H H X X X X L X X A data to B bus B bus isolation B-bus A bus isolation A-bus STORAGE MODE INPUTS 2 FUNCTION LE CLK H X Transparent L ↑ Store data L L Storage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 functional block diagram 1OEB 1OEB 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEA 1OEA 1AI1 81 80 83 82 85 84 87 86 90 1D C2 76 1B1 C1 1D 1AO1 89 C2 C1 To Eight Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 functional block diagram (continued) 2OEB 2OEB 2CLKAB 2LEAB 2LEBA 2CLKBA 2OEA 2OEA 45 46 43 44 41 42 39 Delay3 40 M U 2SEL2 2SEL1 2CLK 2AI2 63 Delay2 X 14 M U X 17 Delay1 1D 60 C1 1D 16 C2 C1 To Seven Other Channels MUX-MODE DELAY DELAY PATH† INPUTS 2SEL1 2SEL2 2CLKAB TO 2CLKAB 2CLKAB TO 2CLK L L No delay No delay L H No delay Delay1 H L Delay2 Delay1 H H Delay3 Delay1 † Refer to delay1 through delay3 in the functional block diagram. 4 2CLKAB 48 C2 2AO2 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2B2 SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range: VCC(5 V), BIAS VCC, BG VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V VCC(3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Voltage range applied to any B output in the disabled or power-off state . . . . . . . . . . . . . . . . . . –0.5 V to 3.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Current applied to any single output in the low state: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 2) VCC, BG VCC, BIAS VCC VCC(3.3 V) MIN NOM MAX Supply voltage 4.5 5 5.5 V Supply voltage 3 3.3 3.6 V VIH High level input voltage High-level VIL Low level input voltage Low-level IIK IOH Input clamp current IOL B port Except B port B port Except B port High-level output current Low level output current Low-level 1.62 2.3 2 0.75 1.47 0.8 UNIT V V –18 mA AO port –3 mA AO port 24 B port 100 mA TA Operating free-air temperature 0 70 °C NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: control inputs to VCC(5 V) or GND, A inputs to VCC(5 V) only, and B inputs to GND only. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP† UNIT –1.2 V –0.5 V VCC(5 ( V)) = 4.5 V,, VCC(3.3 V) = 3.3 V AO port VCC(5 ( V)) = 4.5 V,, VCC(3.3 V) = 3 V IOH = –1 mA IOH = –3 mA AO port VCC(5 V) = 4.5 V, VCC(3.3 V) = 3 V IOL = 24 mA B port VCC(5 ( V)) = 4.5 V,, VCC(3.3 V) = 3 V IOL = 80 mA IOL = 100 mA II Except B port VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.6 V VI = 5.5 V 50 µA IIH‡ Except B port VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.6 V VI = 2.7 V 50 µA Except B port VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.6 V VI = 0.5 V –50 B port VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.6 V VI = 0.75 V –100 IOH B port VCC(5 V) = 0 to 5.5 V, VCC(3.3 V) = 3.6 V VO = 2.1 V 100 µA IOZH AO port VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.6 V VO = 2.7 V 50 µA IOZL AO port VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.6 V VO = 0.5 V –50 µA IOZPU IOZPD AO port VCC = 0 to 2.1 V, VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V VO = 0.5 V to 2.7 V –50 µA –50 µA VCC(5 V) = 5.5 5 5 V, V VCC(3.3 (3 3 V) = 3.3 33V IO = 0 VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.3 V IO = 0 VOH Except B port VOL IIL‡ AO port V 2.5 0.35 0.75 B port to AO port Outputs disabled 0.5 1.1 V 1.15 µA AI port to B port ICC(5 V) 145 ICC(3.3 V) B port to AO port Ci Control and AI inputs Co AO port VI = 0.5 V or 2.5 V VO = 0.5 V or 2.5 V Cio B port per IEEE Std 1194.1-1991 VCC(5 V) = 0 to 5.5 V, VCC(3.3 V) = 3.3 V POST OFFICE BOX 655303 130 mA 120 † All typical values are at VCC(5 V) = 5 V and VCC(3.3 V) = 3.3 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. 6 MAX II = –18 mA II = –40 mA VIK B port • DALLAS, TEXAS 75265 1 mA 6.5 pF 3.5 pF 6.5 pF SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) VO IO B port B port TEST CONDITIONS VCC(5 V) = 0 to 4.5 V, VCC(3.3 V) = 3.3 V MAX UNIT 450 VCC(5 V) = 4.5 V to 5.5 V, VCC(3.3 V) = 3.3 V V VB = 0 to 2 V, µA 5 V to 5 5V VI (BIAS VCC) = 4 4.5 5.5 10 VCC(5 V) = 0, VCC(3.3 V)= 0 V VI (BIAS VCC) = 5 V VCC(5 V) = 0, VCC(3.3 V) = 0 V VB = 1 V, VCC(5 V) = 0 to 5.5 V, VCC(3.3 V) = 3.3 V VCC(5 V) = 0 to 2.2 V, VCC(3.3 V) = 3.3 V MIN 1.62 2.1 V OEB = 0 to 0.8 V 100 µA OEB = 0 to 5 V 100 VI (BIAS VCC) = 4.5 V to 5.5 V –1 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) MIN fclock Clock frequency tw Pulse duration tsu Setup time th Hold time LE high 3 CLK high or low 3 AI or B before LE↓ 3.5 AI or B before CLK↑ 3.5 AI or B after LE↓ AI or B after CLK↑ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 0.7 MAX UNIT 90 MHz ns ns ns 7 SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 switching characteristics over recommended operating free-air temperature range, VCC(5 V) = 5 V ± 0.5 V and VCC(3.3 V) = 3.3 V (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(p)† FROM (INPUT) TO (OUTPUT) MAX 90 AI B LEAB B CLKAB B 2CLKAB (no delay) 2CLKAB 2CLKAB (delay2) 2CLKAB 2CLKAB (delay3) 2CLKAB B AO LEBA AO CLKBA AO 2CLKAB (delay1) 2CLK 2CLKAB (no delay) 2CLK OEB or OEB B OEA or OEA AO OEA or OEA AO 6.2 2.9 6.6 2.7 6.9 3.5 7.3 2.3 6.4 2.9 6.7 2.3 6 2.9 6.7 4.5 9.5 4.5 9.5 9.3 15.4 9.3 15.4 2 6.5 2 6.5 1.8 6.3 1.8 6.3 1.8 6.3 1.8 6.3 5.7 12.3 5.7 12.3 2 6.5 2 6.5 2.6 7 2.6 7 1.4 5.5 1.4 5.5 1.4 6.5 1.4 5.8 Pulse skew, AI to B or B to AO 1.6 Pulse skew, 2CLKAB to 2CLK 1.8 Pulse skew, CLKAB to B or CLKBA to AO 1.5 Pulse skew, CLKAB to 2CLKAB 1.4 tsk(HL), tsk(LH)† Pulse skew, AI to B or B to AO 1 Pulse skew, non-delayed mode for 2CLKAB, CLKAB to AO 1 Pulse skew, non-delayed mode for 2CLKAB, CLKAB to B and 2CLKAB 1 tsk(o)‡ tt Pulse skew, non-delayed mode for 2CLKAB, CLKAB to B and 2CLKAB 1.5 Transition time, B outputs (1.3 V to 1.8 V) 0.5 4.6 Transition time, AO outputs (10% to 90%) 0.4 4.2 tPR B-port input pulse rejection † Skew values are applicable for through mode only, with single-output switching. ‡ Skew values are applicable for CLK mode only, with all outputs simultaneously switching high-to-low or low-to-high. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 UNIT MHz 1.8 tsk(p) tsk(o)‡ 8 MIN ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 2.1 V 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 16.5 Ω From Output Under Test 500 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS LOAD CIRCUIT FOR B OUTPUTS tw 3V 1.5 V Input 3V 1.5 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th 3V 1.5 V Data Input 1.5 V 3V 1.5 V Input 0V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 0V tPHL tPLH VOH 1.55 V Output 1.55 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A to B) 3V Output Control (see Note B) 1.5 V 0V tPZL 2V Input 1.55 V 1.55 V 1V tPHL Output Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B to A) tPLZ 3V 1.5 V tPZH tPLH VOH 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: TTL inputs – PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. BTL inputs – PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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