SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999 D D D D D D Compatible With IEEE Std 1194.1-1991 (BTL) TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA Isolated Logic-Ground and Bus-Ground Pins Reduce Noise High-Impedance State During Power Up and Power Down D D D BIAS VCC Minimizes Signal Distortion During Live Insertion or Withdrawal B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage TTL-Input Structures Incorporate Active Clamping to Aid in Line Termination Packaged in Plastic Quad Flatpack 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 GND B2 GND B3 GND B4 GND B5 GND B6 GND B7 GND B8 B9 GND BG GND SEL0 TDO TDI VCC 14 15 16 17 18 19 20 21 22 23 24 25 26 A9 SEL1 LCB BG VCC LCA GND A3 GND A4 GND A5 GND A6 GND A7 GND A8 GND TMS GND B1 A2 GND A1 VCC BIAS VCC OEA OEB OEB TCK VCC RC PACKAGE (TOP VIEW) description The SN74FB2031 device is a 9-bit transceiver designed to translate signals between TTL and backplane transceiver logic (BTL) environments. It is specifically designed to be compatible with IEEE Std 1194.1-1991. The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC is less than 2.1 V, the B port is turned off. The A port operates at TTL signal levels. The A outputs reflect the inverse of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or VCC is less than 2.1 V, the A outputs are in the high-impedance state. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999 description (continued) Pins are allocated for the 4-wire IEEE Std 1149.1 (JTAG) test bus. TMS and TCK are not connected and TDI is shorted to TDO. BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected. BG VCC and BG GND are the supply inputs for the bias generator. The SN74FB2031 is characterized for operation from 0°C to 70°C. Function Tables TRANSCEIVER INPUTS OEA OEB OEB L H L FUNCTION A data to B bus H L X H X H H H L L L X L X H b s B data to A bus A data to B bus, B data to A bus Isolation STORAGE MODE RESULT LCA, LCB 0 Transparent 1 Latches latched ↑ Flip-flops triggered SELECT 2 SEL1 SEL0 MUX A→B MUX B→A 0 0 Latch Latch 0 1 Through Through 1 0 Flip-flop Flip-flop 1 1 Flip-flop Latch POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999 functional block diagram 18 LCA 20 SEL0 15 SEL1 16 LCB OEB OEB OEA 46 45 47 1D C1 40 1D C1 A1 MUX B1 50 MUX 1D C1 1D C1 To Eight Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V Voltage range applied to any B output in the disabled or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 3.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Current applied to any single output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999 recommended operating conditions (see Note 2) VCC, BIAS VCC, BG VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level IOH High-level output current IOL Low level output current Low-level B port Except B port B port MIN NOM MAX 4.5 5 5.5 1.62 2.3 2 0.75 1.47 Except B port 0.8 A port –3 A port 24 B port 100 UNIT V V V mA mA TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH B port TEST CONDITIONS IIL‡ A port VCC = 4 4.5 5V IOH = –1 mA IOH = –3 mA A port 5V VCC = 4 4.5 IOL = 20 mA IOL = 24 mA B port VCC = 4 4.5 5V IOL = 80 mA IOL = 100 mA Except B port VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V VI = 2.7 V 50 µA 50 µA 5V VCC = 5 5.5 VI = 0.5 V VI = 0.75 V –50 VCC = 2.1 V to 5.5 V, VCC = 2.1 V to 5.5 V, VO = 2.7 V VO = 0.5 V VCC = 0 to 2.1 V, VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V VO = 0.5 V to 2.7 V VCC = 0 to 5.5 V, VCC = 5.5 V, VO = 2.1 V VO = 0 VCC = 5 5.5 5 V, V IO = 0 Except B port Except B port B port IOZPU IOZPD A port IOH IOS§ B port A port A port A port A port to B port B port to A port Ci A port VI = 0.5 V or 2.5 V VO = 0.5 V or 2.5 V B port per IEEE Std 1194.1-1991 VCC = 0 to 5.5 V –1.2 –0.5 2.5 0.35 0.75 V V 3.3 0.5 1.1 V 1.15 –100 –30 µA 50 µA –50 µA 50 µA –50 µA 100 µA –150 mA 78 78 4.5 mA pF 8.5 pF 6 † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. 4 UNIT II = –18 mA II = –40 mA A port Cio MAX VCC = 4.5 V, VCC = 4.5 V, IOZH IOZL ICC TYP† Except B port VOL II IIH‡ MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999 live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) TEST CONDITIONS VCC = 0 to 4.5 V VCC = 4.5 V to 5.5 V V VB = 0 to 2 V, MIN 450 5 V to 5 5V VI (BIAS VCC) = 4 4.5 5.5 VO B port VCC = 0, VCC = 0, VI (BIAS VCC) = 5 V VB = 1 V, IO B port VCC = 0 to 5.5 V, VCC = 0 to 2.2 V, MAX 10 1.62 UNIT µA 2.1 V OEB = 0 to 0.8 V 100 µA OEB = 0 to 5 V 100 VI (BIAS VCC) = 4.5 V to 5.5 V –1 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) MIN fclock tw Clock frequency Pulse duration Clock mode tsu Setup time Latch mode Clock mode th Hold time Latch mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 LCA or LCB 3.3 Data before LCA↑ 1.4 Data before LCB↑ 2.8 Data before LCA↑ 1.1 Data before LCB↑ 2.4 Data after LCA↑ 0.6 Data after LCB↑ 0 Data after LCA↑ 0.9 Data after LCB↑ 0 MAX UNIT 150 MHz ns ns ns 5 SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(p) k( ) Pulse skew tsk(o) k( ) Pulse skew tt FROM (INPUT) TO (OUTPUT) MIN TYP MIN MAX 150 MHz 3.7 4.5 5.9 3.2 6.6 2.9 4 5.7 2.6 5.9 4.1 5 6.5 3.6 7.3 3.3 4.5 6.1 3 6.5 4.5 5.4 7 3.9 7.8 4 5.1 6.7 3.4 7.4 2.8 3.7 4.7 1.9 6 2.5 3.4 4.9 1.8 5.5 2.5 3.8 5.3 1.9 6.3 2.2 3.5 5.1 1.6 5.6 4.1 5.3 6.9 3.7 7.8 3.7 5.2 6.9 3.3 7.7 3.1 4 5.6 2.2 7.1 2.6 3.4 4.9 1.4 5.7 3.3 4.2 5.9 2.4 7.6 2.8 3.9 5.5 1.8 6.3 3.7 4.6 6.1 3.2 6.7 2.9 4.3 5.8 2.5 6.4 2.3 3.1 4.5 1.6 5 1.9 2.7 4.1 1.6 4.4 2.2 3.1 4.5 1.5 5.2 2.5 3.3 4.9 2 5.2 A (through mode) B A (transparent) B LCA B LCB A SEL1 or SEL0 A SEL1 or SEL0 B B (through mode) A B (transparent) A OEB or OEB B OEA A OEA A A B 0.5 B A 0.3 A B 0.2 B A 0.3 0.6 2 2.8 0.4 2.9 0.5 3.5 4.7 0 5.4 • DALLAS, TEXAS 75265 ns ns ns ns ns ns ns ns ns ns ns Transition time, A outputs (10% to 90%) POST OFFICE BOX 655303 ns ns Transition time, B outputs (1.3 V to 1.8 V) 1 UNIT MAX 150 B-port input pulse rejection 6 VCC = 5 V, TA = 25°C 1 ns ns SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR B OUTPUTS tw 3V Input 1.5 V 1.5 V 3V 1.5 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th 3V 3V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V tPHL tPLH 1.55 V 1.55 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOH Output VOL 3V Output Control tPZL 2V Input 1.55 V 1.55 V 1V tPHL 1.5 V Output Waveform 1 S1 at 7 V (see Note B) 1.5 V tPLZ 3.5 V 1.5 V tPZH tPLH VOH Output 1.5 V 0V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A TO B) 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B TO A) Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A PORT) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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