SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 D D D D D Compatible With IEEE Std 1194.1-1991 (BTL) TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion During Live Insertion or Withdrawal D D D High-Impedance State During Power Up and Power Down B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination Packaged in Plastic Quad Flatpack TMS GND B1 GND A1 VCC BIAS VCC OEA OEB OEB TCK VCC A2 RC PACKAGE (TOP VIEW) 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 27 13 GND B2 GND B3 GND B4 GND B5 GND B6 GND B7 GND B8 BP GND COMPETE TDO TDI VCC 14 15 16 17 18 19 20 21 22 23 24 25 26 AP GND WIN BG VCC LE BG GND GND A3 GND A4 GND A5 GND A6 GND A7 GND A8 GND description The SN74FB2032 device is a 9-bit transceiver designed to translate signals between TTL and backplane transceiver logic (BTL) environments and to perform bus arbitration. It is designed specifically to be compatible with IEEE Std 1194.1-1991. The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA and have minimum output edge rates of 2 ns. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC is less than 2.1 V, the B port is turned off. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 description (continued) The A port operates at TTL-signal levels. The A outputs reflect the inverse of the data at the B port when the A-port output enable, OEA, is high. When OEA is low or when VCC is less than 2.1 V, the A outputs are in the high-impedance state. The A-port data is latched when the latch enable (LE) is high. When LE is low, the latches are transparent. The Futurebus protocol logic can be activated by taking COMPETE low. The module (device) then compares its A data (arbitration number) against the A data of another identical module also connected to the B arbitration bus, and sets WIN high if the A data is greater than the A data of the other module (i.e., has higher priority). A8 and B8 are the most-significant bits, and A1 and B1 are the least-significant bits. If OEB is high and OEB is low during this operation, and the A bus of the first module wins priority, the A bus asserts its arbitration number on the B-arbitration bus. AP and BP are the bus-parity bits. The winning module can assert BP low if its parity bit (AP) is high. In a typical operating sequence, a Futurebus arbitration controller latches its arbitration number into the A port and waits for the results of a competition. When the competition is complete, and if the controller’s arbitration number did not win, the controller reads back the current value of the B bus (by taking OEA high) and determines the winning arbitration number. This allows the module to change its arbitration number for the next competition cycle, if desired. Pins are allocated for the four-wire IEEE Std 1149.1 (JTAG) test bus. TMS and TCK are not connected and TDI is shorted to TDO. BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected. BG VCC and BG GND are the supply inputs for the bias generator. The SN74FB2032 is characterized for operation from 0°C to 70°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 Function Tables TRANSCEIVER INPUTS OEA OEB FUNCTION OEB L H L H L X H X H H H L L L X L X H A data to B bus B data to A bus b s A data to B bus, B data to A bus Isolation WIN INPUTS COMPETE DATA A1, A2† WIN H X X L L H X L H L L A1 < A2 L H L L A2 ≤ A1 H OEB OEB H H † A1 refers to the A data of Module 1 and A2 refers to the A data of Module 2. If LE = L, A = current A data. If LE = H, A = the value of A8–A1 prior to the most recent low-to-high transition of LE. BP INPUTS OEB OEB WIN AP‡ BP H L X X X X H X X H H L L X H H L H L H H L H H L ‡ If LE = L, AP = current AP data. If LE = H, AP = the level of AP prior to the most recent low-to-high transition of LE. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 functional block diagram OEB OEB OEA AP A8 A7 A6 A5 A4 A3 A2 A1 LE COMPETE 4 46 45 47 14 12 10 8 6 4 2 52 50 24 D C1 26 D C1 28 D C1 30 D C1 32 D C1 34 D C1 36 D C1 38 D C1 40 D C1 BP B8 B7 B6 B5 B4 B3 B2 B1 18 16 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 WIN SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except BP, B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V BP, B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V Voltage range applied to any B output in the disabled or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 3.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Current applied to any single output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 2) MIN VCC, BIAS VCC, BG VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level IIK IOH Input clamp current IOL Low level output current Low-level 4.5 BP, B port Except B port BP, B port Except B port High-level output current AP, WIN, A port AP, WIN, A port BP, B port 1.62 NOM MAX 5 5.5 2.3 2 0.75 1.47 0.8 UNIT V V V –18 mA –3 mA 24 100 mA TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH BP, B port TEST CONDITIONS IIL‡ MAX Except BP, B port AP WIN, AP, WIN A port VCC = 4 4.5 5V IOH = – 1 mA IOH = –3 mA AP WIN, AP, WIN A port VCC = 4 4.5 5V IOL = 20 mA IOL = 24 mA BP B port BP, VCC = 4 4.5 5V IOL = 80 mA IOL = 100 mA Except BP, B port VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VI = 0.75 V –100 VCC = 2.1 V to 5.5 V, VCC = 2.1 V to 5.5 V, VO = 2.7 V VO = 0.5 V 50 mA –50 mA VCC = 0 V to 2.1 V, VCC = 2.1 V to 0 V, VO = 0.5 V to 2.7 V VO = 0.5 V to 2.7 V 50 mA –50 mA VCC = 0 to 5.5 V, VCC = 5.5 V, VO = 2.1 V VO = 0 100 µA –150 mA Except BP, B port Except BP, B port BP, B port AP, WIN, A port IOZPU IOZPD AP, WIN, A port IOH IOS§ BP, B port AP, WIN, A port AP, WIN, A port AP, WIN, A port A port to B port B port to A port VCC = 5 5.5 5 V, V –1.2 UNIT II = –18 mA II = –40 mA IOZH IOZL ICC TYP† VCC = 4.5 V, VCC = 4.5 V, VOL II IIH‡ MIN –0.5 2.5 V 3.3 0.35 0.75 V 0.5 1.1 V 1.15 50 µA 50 µA –50 –30 55 IO = 0 65 µA mA Ci Control Inputs pF WIN port VI = 0.5 V or 2.5 V VO = 0.5 V or 2.5 V 4 Co 8 pF A port VO = 0.5 V to 2.5 V 7 B port per IEEE Std 1194.1-1991 VCC = 0 V to 5.5 V Cio pF 5 † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) VO IO 6 B port B port TEST CONDITIONS VCC = 0 to 4.5 V VCC = 4.5 V to 5.5 V VB = 0 to 2 V, V VI (BIAS VCC) = 4.5 4 5 V to 5.5 55V VCC = 0, VCC = 0 , VI (BIAS VCC) = 5 V VB = 1 V, VI (BIAS VCC) = 4.5 V to 5.5 V VCC = 0 to 5.5 V, VCC = 0 to 2.2 V, MIN MAX 450 10 µA 2.1 V OEB = 0 to 0.8 V 100 µA OEB = 0 to 5 V 100 POST OFFICE BOX 655303 1.62 UNIT • DALLAS, TEXAS 75265 –1 SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN tw tsu th Pulse duration Setup time Hold time MIN LE high or low 3.3 3.3 Data high before LE↑ (A to B) 1.5 1.5 Data low before LE↑ 1.4 1.4 Data high before LE↑ (A to WIN) 1.9 1.9 Data low before LE↑ 1.7 1.7 Data high before LE↑ (A to B) 1.7 1.7 Data low after LE↑ 1.3 1.3 Data high before LE↑ (A to WIN) 1.6 1.6 Data low after LE↑ 0.9 0.9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT MAX ns ns ns 7 SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C FROM (INPUT) TO (OUTPUT) tPLH tPHL A or AP B or BP tPLH tPHL A Bn – 1 tPLH tPHL A BP tPLH tPHL B Bn – 1 tPLH tPHL LE B or BP tPLH tPHL B or BP A or AP tPLH tPHL B WIN tPLH tPHL A WIN tPLH tPHL LE WIN tPLH tPHL COMPETE WIN tPLH tPHL OEB WIN tPLH tPHL COMPETE B tPLH tPHL COMPETE BP tPLH tPHL OEB B tPLH tPHL OEB B tPZH tPZL OEA A tPHZ tPLZ OEA A A B 0.8 B A 0.5 A B 0.8 B A 0.6 PARAMETER MIN MAX 6.5 2.7 7 4.9 6.3 2.8 6.6 3.1 5.6 7.4 2.5 8.4 3.4 5.6 7.4 3.2 9 4.5 6.6 8.1 4 8.9 4.1 6.3 7.7 3.8 8.4 5.5 8.4 10.8 4.8 11.4 5.5 7.4 8.9 4.9 10 3.7 5.6 6.8 3.4 7.3 3.5 5.1 6.1 3.1 6.8 MIN TYP MAX 2.9 5.2 3 3 5.3 7 2.9 7.2 2.8 4.6 5.9 2 6.1 4 6 7.2 3.4 8.2 4.2 6.6 8.6 3.9 8.9 1.9 4.1 5.4 1.7 5.9 1.9 4 5.3 1.6 6 2.4 4.4 5.7 2.1 6.4 1.9 3.5 4.5 1.6 4.9 1.6 3.4 4.5 1.3 5 1.7 3.4 4.4 1.5 4.9 1.7 3.5 4.7 1.4 5.4 2.2 3.8 4.7 2 5 3.2 5.2 6.6 2.7 7.3 3.8 5.6 6.7 3.5 7.3 3.9 6.2 7.6 3.8 7.8 3.9 5.7 7 3.4 7.8 3.1 5.3 6.7 2.9 7.3 3.4 5.4 6.7 3.2 7.2 4.6 6.7 8.1 4.4 8.6 3.7 5.9 8.1 3.4 8.9 2.5 4.3 6 2.2 6.3 2.2 3.9 5.3 2.2 5.8 1.7 3.4 4.9 1.3 5.5 1.9 3.7 5.4 1.7 5.7 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tsk(p) k( ) Pulse skew tsk(o) k( ) Pulse skew tr tf Rise time, 1.3 V to 1.8 V, B outputs 1 2.2 3.2 1 3.2 ns Fall time, 1.3 V to 1.8 V, B outputs 1 1.3 2.3 1 2.5 ns B-port input pulse rejection 8 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns 1 ns SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVER SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR B OUTPUTS tw 3V Input 1.5 V 1.5 V 3V 1.5 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th 3V 3V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V tPHL tPLH 1.55 V 1.55 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOH Output VOL 3V Output Control tPZL 2V 1.55 V 1.55 V 1V tPHL 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPLH VOH Output 1.5 V 0V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A TO B) Input 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B TO A) Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A PORT) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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