MCNIX MX10F201FC

MX10F201FC
FEATURES OF MX10F201FC (80C51 with MTP memory and LCD)
- 80C51 CPU core
- 4.5 ~ 5.5V voltage range
- 2 to 16MHz clock frequency
- 16K bytes MTP memory for code memory
- 512 bytes internal data RAM
- Low power consumption
- Up to 16 digits LCD driver/controller
- Four 8 bit general purpose I/O ports
- Two standard 16-bit Timers
- On-chip Watch Dog Timer
- Two channel PWM outputs
- UART
- 8 interrupt sources
- 100 pin PQFP package
- Single clock or dual clock
- EMI compatibility
Features list
- 80C51 CPU core
- 4.5 ~ 5.5V operation voltage range
- 2 to 16MHz clock frequency
- 16K bytes MTP memory for code memory
- More than 100 times program/erase cycles
- More than 10 years data retention
- 512 bytes internal data RAM
- Low operation current
- Power saving modes
- User friendly power control for active mode current
- Idle mode
- Sleep mode
- Power down mode, can be wake up by external interrupts or RESET
- LCD driver/controller
- Max. 16-digits display at 1/4 duty LCD
- 1:1(static), 1:2, 1:3 or 1:4 selectable LCD multiplexing rate
- 4 backplane driver, 32 segment driver
- LCD directly drive capability with display memory
- VLCD to control LCD driving voltage, (VLCD-VSS)
- 4x8 general purpose I/O ports
- Provide software I2C capability
- Two standard 16-bit Timers (Timer 0,1)
- On-chip Watch Dog Timer (WDT)
- Two channel PWM outputs
- UART
- Up to 8 interrupt sources and 8 interrupt vectors
- 4 external sources
- 4 internal sources(Timer0,Timer1,watch Timer and UART)
- 100 pin PQFP package
- Single clock or dual clock
- single clock mode : 2~16MHz system clock for CPU,Timer0/1,WDT,UART and LCD
- dual clock mode : 2~16MHz system clock for CPU,Timer0/1,WDT,UART; while 32.768KHz sub-system
clock for LCD and watch timer.
- system clock is either crystal or RC activated
- EMC(Electro-Magnetic Compatibility) improved
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MX10F201FC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
S4
S3
S2
S1
S0
BP3
BP2
BP1
BP0
NC
VDD
NC
VSS
XTAL3
XTAL4
NC
P17
P16
P15/PWM1
P14/PWM0
P13
P12
P11
P10
NC
VPP
NC
NC
P27
PINNING
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
MX10F201FC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
NC
NC
P26
P25
P24
P23
P22
P21
P20
NC
NC
NC
P37/INT3
P36/INT2
P35/T1
P34/T0
P33/INT1
P32/INT0
P31/TxD
P30/RxD
NC
S23
S24
S25
S26
S27
S28
S29
S30
S31
VLCD
NC
VSS
NC
RESET
XTAL1
XTAL2
VDD
NC
VSS
RCP
P00
P01
P02
P03
P04
P05
P06
P07
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
NC
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
Fig.1 Pinning
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MX10F201FC
Table. 1 Pin Description
I/O SYMBOL
O BP0-BP3
O S00-S31
I/O P00-P07
I/O P20-P27
PIN \QFP 100
71~74
75-79,83-100,
2-10
22-29
42-48,51
I/O P10-P17
P14
P15
I/O P30-P37
P30
P31
P32-P33,
P36-P37
P34
P35
56-63
I
I
I
I
O
I
O
I
I
15
18,69
13,20,67
16
17
66
65
21
54
RESET
VDD
VSS
XTAL1
XTAL2
XTAL3
XTAL4
RCP
TEST/VPP
31-38
31
32
DESCRIPTION
Backplane drive output line 0 to 3.
Segment drive output line 0 to 31.
Port:8-bit open drain bidirectional I/O Port
Port: 8-bit quasi-bidirectional I/O Port with
internal pull-up
Quasi-bidirectional I/O lines
also for PWM channel 0
also for PWM channel 1
Quasi-bidirectional I/O lines
also for UART Receive
also for UART Transmit
also for external interrupt 0-3
also for Timer0 external input
also for Timer1 external input
reset input
Positive power supply
Ground
XTAL connection input
XTAL connection output
32.768KHz, XTAL input
32.768KHz, XTAL output
RC oscillator resistor connection input
Supply 12V power for programming / erasing
I
VLCD
11
LCD driver power supply
Note:
1. To avoid a 'Latch-up' effect at power-on , the voltage on any pin (at any time )must not be higher than VDD +0.5 V
or lower Vss-0.5V respectively
2. The generation or use of a Port 3 pin as an alternative function is carried out automatically by the associated
Special Function Register (SFR) bit is properly written .
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MX10F201FC
XTAL1
3
3
T0
T1
T0/T1
Two 16-bit
Counter
XTAL2
3 3 3 3
INT0/1/2/3
VPP
VDD
TD
Program
Memory
16KB
CPU
VSS PWM0 PWM1 3
VLCD
Watch
Dog
Timer
Data
Memory
512x8 RAM
3
RD
PWM
Serial
Port
RESET
8-bit internal Bus
LCD Unit
Parallel I/O
Ports
8
8
8
P0
P1
P2
8
S00-S31
3
BP3
BP2
BP1
BP0
P3
Alternative Function of Port3
Fig.2 Block Diagram
Internal Bus
8
LCON
LCD Freq
LCD Duty
BIAS
ENLCD
LCD Segment
Display Register
Ext.CLK Div ider
LCD_CL K
BP0_SEG[31:0]
Timing/Duty
Control,
Voltage
Selector
Backplane Gen.
BP3_SEG[31:0]
Segment Gen.
4 BP_Output [1:0]
VLCD
VSS
LCD
BIAS
Gen.
BP Driver
32 Seg_Output [1:0]
Seg. Driver
4
32
SEG31 SEG30….SEG0
BP0
BP1
BP2
BP3
LCD Panel
Fig.3 LCD Driver Block Diagram
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MX10F201FC
FUNCTIONAL DESCTIPTION
General
The MX10F201FC is a stand-alone high-performance and low power microcontroller designed for use in many
applications which need code programmability.
The Flash EPROM offers customers to program the device themselves. This feature increases the flexibility in
many applications, not only in development stage, but also in mass production stage.
In addition to the 80C51 standard functions, the MX10F201FC provides a number of dedicated hardware functions.
MX10F201FC is a control-oriented CPU with on-chip program and data memory. It can execute program with internal
memory up to 16k bytes. MX10F201FC has four software selectable modes of reduced activity for power reduction :
active power control, idle, sleep, and Power-down. The idle mode freezes the CPU while allowing the RAM, Timers,
serial ports, interrupt system and other peripherals to continue functioning. The Power-down mode saves the RAM
contents but freezes the oscillator causing all other chip functions to be inoperative. Power-down mode can be
terminated by an external reset ,and in addition , by either of the four external interrupts. The sleep mode behaves like
power down mode, but with LCD and oscillator still turning on. And sleep mode can be terminated as the power down
mode does.
Instruction Set Execution
The MX10F201FC uses the powerful instruction set of the 80C51. Additional SFRs are incorporated to control the
on-chip peripherals. The instruction set consists of 49 single-byte, 46 two-bytes, and 16 three-bytes instructions.
When using a 16MHz oscillator, 64 instructions execute in 750 ns and 45 instructions execute in 1.5 us. Multiply and
divide instructions execute in 3 us.
MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 256 bytes
internal data memory (RAM), 256 byte auxiliary data memory (AUX-RAM) and 16k byte internal MTP program memory
(FEPROM).
Program Memory
The program memory address space of the MX10F201FC comprises an internal and an external memory space.
The MX10F201FC has 16k byte of program memory on-chip.
Program Protection
If the user choose to set security lock in MTP memory, the program content is protected from reading out of chip.
Internal Data Memory
The internal data memory is divided into three physically separated parts: 256 byte of RAM, 256 bytes of AUXRAM, and 128 bytes special function register area (SFR). These parts can be addressed as follows (see Fig.4 and
Table. 2)
- RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of
the selected register bank.
- RAM 128 to 255 can only be addressed indirectly . Address pointers are R0 and R1 of the selected register
bank.
- AUX-RAM 0 to 255 is indirectly addressable as the external data memory locations 0 to 255 with the MOVX
instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. When executing from
internal program memory, an access to AUX_RAM 0 to 255 will not affect the ports P0,P2,P3.6 and P3.7.
SFRs can only be addressed directly in the address range from 128 to 255.
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MX10F201FC
Table. 2 Internal data memory access
LOCATION
RAM 0 to 127
RAM 128 to 255
AUX-RAM 0 to 255
Special Function Register (SFR) 128 to 255
ADDRESSED
DIRECT and INDIRECT
INDIRECT only
INDIRECT only with MOVX
DIRECT only
Fig. 4 shows the internal memory address space. Table 3 shows the Special Function Register (SFR) memory
map. Location 0 to 31 at the lower RAM area can be devided into four 8-bit register banks. Only one of these
banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit
locations.
The stack can be located anywhere in the internal 256 byte RAM. The stack depth is only limited by the available
internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-byte register banks
reside in the SFR address space.
- Register
- Direct
- Register-Indirect
- Immediate
- Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing destination operands. Most instructions have a 'destination /
source' field that specifies the data type, addressing methods and operands involved. For operations other than
MOVs, the destination operand is also a source operand.
Access to memory addresses is as follows:
- Register in one of the four 8-byte register banks through Direct or Register-Indirect addressing.
- 256 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0-127 of internal RAM may be
only be addressed indirectly as data RAM.
- SFR through direct addressing at address location 128-255.
OVERLAPPED SPACE with different access schemes
INTERNAL DATA MEMORY
255
16K
internal
program
memory
INDIRECT ONLY
127
---------------------
0
DIRECT AND
INDIRECT
0
SFRs
Direct only
MAIN RAM
SFRs
AUXILIARY
RAM
through
MOVX access
AUX-RAM
PROGRAM MEMORY
Fig. 4 Internal program and data memory address space
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MX10F201FC
Table. 3 SFR Registers Map
Symbol
P0
SP
DPL
DPH
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
P1
SCON
SBUF
P2
IE
P3
IP
LCON
LCD0
LCD1
LCD2
LCD3
LCD4
INTCON
LCD5
LCD6
LCD7
LCD8
LCD9
LCDA
LCDB
PSW
LCDC
LCDD
LCDE
LCDF
ACC
WTL
WTH
IEN1
EBTCON
B
PCON1
IP1
PWM0
PWM1
PWMP
T3 (WDT)
Direct Address(ex)
80H
81
82
83
87
88
89
8A
8B
8C
8D
90
98
99
A0
A8
B0
B8
BA
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
D0
D1
D2
D3
D4
E0
E3
E4
E8
EB
F0
F1
F8
FC
FD
FE
FF
Reset Value
1111,1111
0000,0111
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
1111,1111
0000,0000
xxxx,xxxx
1111,1111
0000,0000
1111,1111
x000,0000
x001,1100
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
xx00,0000
xxxx,xx00
xxxx,001x
0000,0000
x000,0100
xxxx,xx00
0000,0000
0000,0000
0000,0000
1111,1111
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MX10F201FC
I/O facilities
MX10F201FC has one 8 bits port, port 0, which is open drain, and three 8 bits ports, port 1/2/3, which are quasi bidirectional ports. These four ports are fully compatible to standard 80C51's port 0/1/2/3.
- Port1: pins can be configured individually to provide 2 PWM outputs.
- Port3: pins can be configured individually to provide: external interrupt inputs (external interrupt 0/1/2/3);
external inputs for Timer/ counter 0 and Timer /counter1, and UART receive / transmit.
Port pins which are not used for alternate functions may be used as normal bidirectional I/O pins. The generation or
use of a Port 1 or Port 3 pin as an alternate function is carried out automatically by writing the associated SFR bit with
proper value.
+5V
2 oscillator
penods
strong pull-up
P1
P2
P3
I/O PORT
1,2,3
O
from port latch
n
input data
read port pin
INPUT
BUFFER
Fig. 5 I/O buffers in the MX10F201FC (Ports 1,2,3)
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MX10F201FC
Timer/Counter
MX10F201FC's Timer/Counter 0 and 1 are fully compatible to standard 80C51's.
The MX10F201FC's contains two 16-bit Timer/counters, Timer 0 and Timer 1. Timer 0 and Timer 1 may be
programmed to carry out the following functions:
- measure time intervals and pulse durations
- count events
- generate interrupt requests.
Timer 0 and Timer 1
Timers 0 and 1 each have a control bit in TMOD SFR that selects the Timer or counter function of the
corresponding Timer. In the Timer function, the register is incremented every machine cycle. Thus, one can think of
it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of
the oscillator frequency.
In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding
samples, when the transition shows a HIGH in one cycle and a LOW in the next cycle, the counter is incremented.
Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once
before it changes, it should be held for at least one full machine cycle.
Timer 0 and Timer 1 can be programmed independently to operate in one of four modes (refer to table 5) :
- Mode 0 : 8-bit Timer/counter with devided-by-32 prescaler
- Mode 1 : 16-bit Timer/counter
- Mode 2 : 8-bit Timer/counter with automatic reload
- Mode 3 : Timer 0 :one 8-bit Timer/counter and one 8-bits Timer. Timer 1 :stopped.
When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt
request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port
transmission-rgate generator. With a 16 MHz crystal, the counting frequency of these Timer/counters is as follows:
- in the Timer function, the Timer is incremented at a frequency of 1.33 MHz (oscillator frequency divided by 12).
- in the counter function, the frequency handling range for external inputs is 0 Hz to 0.66 MHz (oscillator
frequency divided by 24).
Both internal and external inputs can be gated to the Timer by a second external source for directly measuring
pulse duration.
The Timers are started and stopped under software control. Each one sets its interrupt request flag when it
overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3
as previously described.
TMOD : TIMER/COUNTER MODE CONTROL REGISTER
This register is located at address 89H.
Table. 4 TMOD SFR (89H)
7
6
GATE
C/ T
(MSB)
TIMER 1
5
M1
4
M0
3
GATE
2
C/ T
1
M1
0
M0
(LSB)
TIMER 0
keep the above table with the following table
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MX10F201FC
Table. 5 Description of TMOD bits
MNEMONIC
TIMER 1
GATE
POSITION
FUNCTION
TMOD.7
C/T
TMOD.6
M1
M0
TIMER 0
GATE
TMOD.5
TMOD.4
Timer 1 gating control : when set, Timer/counter '1' is enabled only while 'Int1'
pin is high and 'tr1' control bit is set. when cleared, Timer/counter '1' is enabled
whenever 'tr1' control bit is set.
Timer or counter selector: cleared for Timer operation (input from internal
system clock). set for counter operation (input from 'T1' input pin).
Operation mode: see table 6.
Operation mode: see table 6.
C/T
TMOD.2
M1
M0
TMOD.1
TMOD.0
TMOD.3
Timer 0 gating control: when set, Timer/Counter '0' is enabled only while 'Int0'
pin is high and 'tr0' control bit is set. when cleared, Timer/counter '0' is enabled
whenever 'tr0' control bit is set.
Timer or counter selector: cleared for Timer operation (input from internal
system clock). set for counter operation (input from 'T0' input pin).
Operation mode: see table 6.
Operation mode: see table 6.
Table. 6 TMOD M1 and M0 operating modes
M1
M0 FUNCTION
0
0
8-bit Timer/counter : 'THx' with 5-bit prescaler.
0
1
16-bit Timer/counter : 'THx' and 'TLx' are cascaded, there is no prescaler.
1
0
8-bit autoload Timer/counter : 'THx' holds a value which is to be reloaded into 'TLx' each time it
overflows.
1
1
Timer 0: TL0 is an 8-bit Timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8bit Timer controlled by Timer 1 control bits.
1
1
Timer 1 : Timer/counter 1 stopped.
TCON : TIMER/COUNTER CONTROL REGISTER
This register is located at address 88H.
Table. 7 TCON SFR (88H)
7
6
TF1
TR1
(MSB)
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
(LSB)
keep the above table with the following table
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MX10F201FC
Table. 8 Description of TCON bits
MNEMONIC POSITION FUNCTION
TF1
TCON.7
Timer 1 overflow flag : set by hardware on Timer/Counter overflow. Cleared when
interrupt is processed.
TR1
TCON.6
Timer 0 overflow flag : set by hardware on Timer/Counter overflow. Cleared when
interrupt is processed.
TF0
TCON.5
Timer 0 overflow flag: set by hardware on Timer/Counter overflow. Cleared when
interrupt is processed.
TR0
TCON.4
Timer 0 control bit : set/cleared by software to turn Timer/counter ON/OFF.
IE1
TCON.3
Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared
when interrupt is processed.
IT1
TCON.2
Interrupt 1 type control bit : set/cleared by software to specify falling edge/LOW
level triggered external interrupt.
IE0
TOCN.1
Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared
when interrupt is processed.
IT0
TOCN.0
Interrupt 0 type control bit: set/cleared by software tospecify falling edge/LOW
level triggered external interrupt.
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MX10F201FC
Interrupt system
The MX10F201FC contains a 8-source 4 external interrupts, Timer 0, Timer1, watch timer and UART structures
with two priority levels.
Each External interrupts INT0, INT1, INT2, and INT3 can be either level-activated or transition-activated depending
on bits IT0 and IT1 in TCON SFR and IT2, IT3 in INTCON SFR. The flags that actually generate these interrupts
are bits IE0, IE1 in TCON and IE2,IE3 in INTCON. When an external interrupt is generated, the corresponding
request flag is cleared by the hardware when the service routine is vectored to, if the interrupt is transitionactivated. If the interrupt is level-activated the external source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactive the request before the interrupt service routine is completed,
otherwise another interrupt will be generated.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated,
the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.
IE : INTERRUPT ENABLE REGISTER
This register is located at address A8H.
Table. 9 IE SFR (A8H)
7
6
5
4
3
EA
EX3
EX2
ES
ET1
(MSB)
keep the above table with the following table
2
EX1
1
ET0
0
EX0
(LSB)
Table. 10 Description of IE bits
MNEMONIC POSITION
FUNCTION
EA
IE.7
Disable all interrupt
- Low, all disabled.
- High, each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
EX3
IE.6
Enable / Disable External interrupt 3.
- Low, disabled
- High, enabled
EX2
IE.5
Enable / Disable External Interrupt 2.
- Low, disabled
- High, enabled
ES
IE.4
Enable / Disable UART interrupt.
- Low, disabled
- High, enabled
ET1
IE.3
Enable / Disable Timer1 overflow interrupt.
EX1
IE.2
Enable / Disable External interrupt 1.
- Low, disabled
- High, enabled
ET0
IE.1
Enable / disable Timer0 overflow interrupt.
EX0
IE.0
Enable / Disable External interrupt 0.
- Low, disabled
- High, enabled
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MX10F201FC
IEN1 : INTERRUPT ENABLE REGISTER 2
Table. 11 IEN1 SFR (E8H)
7
6
5
4
3
-
2
-
1
EWT
0
0
2
PX1
1
PT0
0
PX0 (LSB)
EWT : Enable / Disable Watch Timer interrupt.
IP : INTERRUPT PRIORITY REGISTER
This register is located at address B8H.
Table. 12 IP SFR (B8H)
7
6
5
PX3
PX2
4
PS
3
PT1
keep the above table with the following table
Table. 13 Description of IP bits
MNEMONIC POSITION
FUNCTION
IP.7
RESERVED
PX3
IP.6
Define External interrupt 3 interrupt priority level.
- High, assign a high priority level.
PX2
IP.5
Define External interrupt 2 interrupt priority level.
- High, assign a high priority level.
PS1
IP.4
Define interrupt priority level of UART.
PT1
IP.3
Define Timer1 overflow interrupt priority level.
PX1
IP.2
Define External interrupt 1 interrupt priority level.
- High, assign a high priority level.
PT0
IP.1
Define Timer0 overflow interrupt priority level.
PX0
IP.0
Define External interrupt 0 interrupt priority level.
- High, assign a high priority level.
IP1 : INTERRUPT PRIORITY REGISTER 2
Table. 14 IP1 SFR (F8H)
7
6
5
4
3
-
2
-
1
PWT
0
0
PWT : Define Watch Timer interrupt priority level.
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MX10F201FC
Table. 15 INTCON SFR (C0H)
7
6
5
4
0
0
WTF
WTR
3
IE3
2
IT3
1
IE2
0
IT2
Table. 16 Description of INTCON bits
IE3/2 : External interrupt 3/2 edge flag. Set by H/W when exteranl interrupt is detected, and cleared when interrupt
is processed.
IT3/2 : External interrupt 3/2 type control bit. Set/cleared by S/W to specify falling edge/low level triggered external
interrupt.
WTF : Watch timer overflow interrupt flog. Set by H/W when watch timer overflow occurred, and cleared by S/W or
warm/cold reset.
WTR : Watch timer enable bit. Set/ cleared by S/W
Table. 17 INTERRUPT VECTORS & PRIORITY WITHIN LEVELS
source
name
Priority Within Level
Ext. interrupt0
IE0
1(Highest)
Timer0 overflow
TF0
2
Ext. interrupt1
IE1
3
Timer1 overflow
TF1
4
UART interrupt
IS
5
Ext. interrupt2
IE2
6
Ext. interrupt3
IE3
7
Watch timer overflow
WTF
8
P/N:PM0730
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
REV. 0.1, FEB. 14, 2003
14
MX10F201FC
Watch Timer
The watch timer module (see Fig. 6) is clocked by 32.768KHz external crystal, and generates interrupt request
every 0.5 second. This value is derived from ftimer = fosc / (256x64). The watch timer consists of an 8-bit timer
register WTL and a 6-bit timer registers WTH. The WTL register is triggered by the 32.768KHz external crystal, and
the WTH register increases its value while WTL overflow occurs. When the overflow of WTH occurs, the WTF bit in
SFR INTCON is set High automatically and an interrupt request is sent to the microcontroller.
Both of the timer registers WTL and WTH can be loaded values by software. Therefore the time interval of the
watch timer interrupt request can be adjusted. This allows the watch timer to send interrupt request more frequently
for some special application.
The WTF can be set both by hardware and software, but it can only be cleared by software. The 32.768KHz
external oscillator is gated by the WTR bit in SFR INTCON. If WTR is cleared, the watch timer registers will hold
their values.
In the idle and sleep states the watch timer remains active, and it wakes up the microcontroller while the watch
timer overflow (i.e. WTF is set HIGH) occurs.
Since this module is clocked by the 32.768KHz external crystal, this module is disabled and consumes no power if
there is no such crystal connected to the chip.
Internal Bus
WTH
(6-bit)
Load
WTL
(8-bit)
Load
OSC
32.768K
WTF
(1-bit)
Load
Interrupt
Request
WTR
Write WTF, WTL, WTH
Fig. 6 Watch Timer
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15
MX10F201FC
LCD drivers
The LCD module includes 4 by 32 pixel memory and can drive directly 4 backplanes and 32 segments outputs. Thus,
for common digit-typed LCD, MX10F201FC can have maximum 16 digits display.
LCD Control Register (LCON)
Since MX10F201FC has several possible clocking alternatives : 2 to 16MHz system clock with possible second
32.768KHz sub-system clock, programmers need to set up this register to get proper LCD frame scan rate.
Table. 18 LCON SFR (BAH)
7
6
5
4
3
LCDF2 LCDF1 LCDF0 MD1
2
MD0
1
Bias
0
ENLCD
. LCDF2,LCDF1,LCDF0: Selection of LCD frame scan frequency
Table. 19
Frame scan freq (Hz)
Fclk
(ext. clk)
- 000 : 16Mhz
- 001 : 12Mhz
- 010 : 8Mhz
- 011 : 4Mhz
- 100 : 2Mhz
- 101 : 1Mhz
- 110 :0.5Mhz
* - 111 : 32Khz
Divider
Select
Fclk/2^18
Fclk/(2^16*3)
Fclk/2^17
Fclk/2^16
Fclk/2^15
Fclk/2^14
Fclk/2^13
Fclk/2^9
1/4 Duty
61
61
61
61
61
61
61
64
1/3 Duty
81
81
81
81
81
81
81
85
1/2 Duty
61
61
61
61
61
61
61
64
Pixel
32
64
96
128
Digits
4
8
12
16
Static
61
61
61
61
61
61
61
64
* Note : Dual clock mode is set by writing as "111".
. MD1,MD0: Mode bits, determine the LCD multiplex rate.
Table. 20
- 00 : static
- 01 : 1:2
- 10 : 1:3
- 11 : 1:4
No of Backplanes
1 (BP0)
2 (BP0,1)
3 (BP0,1,2)
4 (BP0,1,2,3)
. Bias: set LCD voltage bias generator.
- High, bias is 1/2(VLCD-VSS)
- Low, bias is 1/3(VLCD-VSS)
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16
MX10F201FC
Table. 21
LCD Drive Mode
static
1:2
1:2
1:3
1:4
No of BPs
1
2
2
3
4
LCD Bias
static
1/2
1/3
1/3
1/3
Voff(rms)
0
0.354
0.333
0.333
0.333
Von(rms)
1
0.791
0.745
0.638
0.577
Contrast
infinity
2.236
2.236
1.915
1.732
. ENLCD: Enable/Disable LCD
- Low, all segment and backplanes drivers are set to the Vss level.
- High, the LCD is enable and digits display is possible.
LCD segment display register : contain the on/off information of 4 by 32 segments of LCD
Table. 22
Register Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
LCD0
BBH
SEG1
SEG0
LCD1
BCH
SEG3
SEG2
LCD2
BDH
SEG5
SEG4
LCD3
BEH
SEG7
SEG6
LCD4
BFH
SEG9
SEG8
LCD5
C1H
SEG11
SEG10
LCD6
C2H
SEG13
SEG12
LCD7
C3H
SEG15
SEG14
LCD8
C4H
SEG17
SEG16
LCD9
C5H
SEG19
SEG18
LCDA
C6H
SEG21
SEG20
LCDB
C7H
SEG23
SEG22
LCDC
D1H
SEG25
SEG24
LCDD
D2H
SEG27
SEG26
LCDE
D3H
SEG29
SEG28
LCDF
D4H
SEG31
SEG30
BP3
BP2
BP1
BP0
BP3
BP2
BP1
Bit0
BP0
LCD drive mode waveform : used to control the voltage level of backplane and segment outputs
. Static drive mode
. 1:2 multiplex drive mode with 1/2 bias
. 1:2 multiplex drive mode with 1/3 bias
. 1:3 multiplex drive mode with 1/3 bias
. 1:4 multiplex drive mode with 1/3 bias
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17
MX10F201FC
SEG0
SEG1
SEG5
SEG6
SEG4
SEG2
SEG7
COM0
SEG3
ENLCD
-- VLCD
display data area
address
SEG0
-- VSS
BBH
***0 ***1
BCH
***1 ***1
BDH
***1 ***0
BEH
***0 ***1
-- VLCD
SEG4
-- VSS
-- VLCD
SEG7
-- VSS
(Note) *: don't care
-- VLCD
COM0
-- VSS
-- VLCD
-
COM0-SEG0
(Selected)
-- -VLCD
-- VLCD
0
-
COM0-SEG4
(Non-Selected)
-- -VLCD
Fig. 7 Static Drive
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18
MX10F201FC
COM0
SEG0
SEG3
SEG2
COM1
SEG1
ENLCD
-- VLCD
display data area
address
SEG0
-- VSS
BBH
**01 **01
BCH
**11 **10
-- VLCD
SEG1
-- VSS
(Note) *: don't care
-- VLCD
SEG2
-- VSS
-- VLCD
-
SEG3
-- VSS
-- VLCD
-- VSS
COM0
-- VLCD
COM1
-- VSS
-- VLCD
0
-
COM0-SEG1
(Selected)
-- VSS
-- VLCD
0
-
COM0-SEG2
(Non-Selected)
-- VSS
Fig. 8 1/2 Duty (1/2 Bias) Drive
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19
MX10F201FC
COM0
SEG0
SEG3
SEG2
SEG1
COM1
ENLCD
-- VLCD
-
SEG0
-- VSS
-- VLCD
-
SEG1
-- VSS
-- VLCD
-
SEG2
-- VSS
display data area
address
-- VLCD
BBH
**01 **01
BCH
**11 **10
-
SEG3
-- VSS
-- VLCD
-
COM0
-- VSS
-- VLCD
-
COM1
-- VSS
-- VLCD - VSS
0
-
COM0-SEG1
(Selected)
-- -(VLCD - VSS)
-- VLCD - VSS
0
-
COM0-SEG2
(Non-Selected)
-- -(VLCD - VSS)
Fig. 9 1/2 Duty (1/3 Bias) Drive
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REV. 0.1, FEB. 14, 2003
20
MX10F201FC
SEG1
SEG0
SEG2
COM0
COM1
COM2
ENLCD
-- VLCD
SEG0
-- VSS
-- VLCD
SEG1
-- VSS
-- VLCD
display data area
address
SEG2
BBH
*111 *010
BCH
**** **01
-- VSS
-- VLCD
COM0
-- VSS
(Note) *: don't care
-- VLCD
-
COM1
-- VSS
-- VLCD
-
COM2
-- VSS
-- VLCD
0
-
COM0-SEG1
(Selected)
-- -VLCD
-- VLCD
0
-
COM0-SEG2
(Non-Selected)
-- -VLCD
Fig. 10 1/3 Duty (1/2 Bias) Drive
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21
MX10F201FC
SEG1
SEG0
SEG2
COM0
COM1
COM2
ENLCD
-- VLCD
SEG0
-
-- VSS
-- VLCD
display data area
address
BBH
-
SEG1
-- VSS
-- VLCD
*111 *010
-
SEG2
BCH
**** **01
-- VSS
-- VLCD
(Note) *: don't care
-
COM0
-- VSS
-- VLCD
-
COM1
-- VSS
-- VLCD
-
COM2
-- VSS
-- VLCD
0
-
COM0-SEG1
(Selected)
-- -VLCD
-- VLCD
0
-
COM0-SEG2
(Non-Selected)
-- -VLCD
Fig. 11 1/3 Duty (1/3 Bias) Drive
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22
MX10F201FC
COM0
SEG1
COM1
COM2
SEG0
COM3
ENLCD
-- VLCD
SEG0
-
-- VSS
-- VLCD
SEG1
-
-- VSS
-- VLCD
-
COM0
-- VSS
-- VLCD
display data area
address
BBH
-
COM1
-- VSS
10110101
-- VLCD
-
COM2
-- VSS
-- VLCD
-
COM3
-- VSS
-- VLCD
COM0-SEG0
(Selected)
0
-
-- -VLCD
-- VLCD
0
-
COM0-SEG1
(Non-Selected)
-- -VLCD
Fig .12 1/4 Duty (1/3 Bias) Drive
P/N:PM0730
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23
MX10F201FC
Power saving modes : active power control, idle, sleep and power down modes
In order to enable lowest power consumption in system application, MX10F201FC has user friendly power control
mechanism as follows :
1) Active power control : used to turn off un-used peripherals in specific applications. For instance, UART might
not be used in audio CD application, then programmer can disable it to save power.
2) Idle mode : used to turn off 80C51 during certain conditions.
3) Sleep mode : used to turn off the whole system except LCD and possibly watch Timer.
4) Power down mode : turn off the whole system.
PCON : Power Control Register (PCON)
PCON SFR (87H)
7
6
SMOD -
5
4
SCEER WLE
3
CF1
2
1
CF0 PD
0
IDC
SMOD : Doubl band rate bit for UART.
SLEEP : Sleep mode bit. Setting it activates sleep mode, and could be terminated as the way to terminate the pull
down mode.
WLE : Watch dog load enable. This flag must be set prior to loading WDT and is cleaned when WDT is loaded.
CF1/CF0 : general-prepose flag bit.
PD : Power - down bit. Setting it activates power - down mode.
IDL : idle mode bit. Setting it activates idle mode.
Active power control mode
PCON1 : POWER CONTROL REGISTER 2
Table. 23 PCON1 SFR (F1H)
7
6
5
4
3
TD
UARTD WDTD PWMD
2
1
1
WTD
0
LCDD
Table. 24 Description of PCON1 bits
. TD : Timer0/1 Disable bit. Setting it to shut-down Timer0/1.
. UARTD: UART Disable bit. Setting it to shut-down UART.
. WDTD : WatchDog Timer Disable bit. Setting it to shut-down WDT.
. PWMD : Pulse Width Modulation Disable bit. Setting it to shut-down PWM.
. WTD : Watch Timer Disable bit, Setting it to shu-down W T.
. BIT 2 must write "1"
. LCDD : LCD Disable bit. Setting it to shut-down all LCD relative modules.
P/N:PM0730
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24
MX10F201FC
RC oscillator function
MX10F201FC provides a RC oscillator function for the application that does not need very accurate system clock
frequency and has to save the cost of crystal oscillator. As shown in Fig. 13, to use the RC oscillator function as
the system clock source, a suggested 50K~200K can be connected between the RCP pin and ground. The XTAL1
pin has to be connected to ground or the internal clock system may be failed. When the system clock source
comes from the crystal oscillator, the RCP pin is suggested to connect to VDD. The following table shows
approximately the relationship between the RC oscillator clock frequency and the resistor value.
Table. 25 RC oscillator reference table
Resistor Value (K ohm)
RC oscillator clock frequency (MHz)
5V
3V
50
12~14
9~11
75
10~12
7.5~9
100
9~10
6.5~8
125
8~9
6~7.5
150
~7.5
5.5~6.5
175
~6.5
5.2~5.8
200
~6
4.7~5.3
XTAL1
XTAL1
XTAL2
XTAL2
VDD
Resistor
RCP
RCP
(a)
(b)
Fig. 13 System clock connection way : (a) Use RC oscillator as system
clock source, (b) Use crystal oscillator as system clock source.
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25
MX10F201FC
Clock system
MX10F201FC has two possible clocking schemes with four combinations as follows :
Single clock mode
Dual clock mode
System clock
External 2 ~ 16MHz crystal (XTAL1,XTAL2)
RC oscillator with external resister (RCP)
and XTAC1 is connected to GND
External 2 ~ 16MHz crystal (XTAL1,XTAL2)
RC oscillator with external resister (RCP)
and XTAC1 is connected to GND
Sub-system clock
XTAL3 is connected to GND
XTAL3 is connected to GND
32.768KHzcrystal (XTAL3,XTAL4)
32.768KHz crystal (XTAL3,XTAL4)
The interaction between power saving modes and clock system is listed as follows :
80C51
Timer0/1, WDT, UART
LCD
Active mode
Power control active mode
Idle mode
Sleep mode
Power down mode
Single clock
System clock
System clock
System clock
All are active except watch Timer
Individual peripheral is disabled by
corresponding active power control bit
1) 80C51 is stopped
2) can be wake up by any interrupt
1) All are stopped except LCD, system
oscillator.
2) can be wake up by external interrupts,
1)All are stopped
2) can be wake up by external interrupts
or RESET
P/N:PM0730
Dual clock
System clock
System clock
Sub-system clock
All are active
Individual peripheral is disabled by
corresponding active power control bit
1) 80C51 is stopped
2) can be wake up by any interrupt
1) All are stopped except watch Timer,
LCD, sub-system oscillator.
2) can be wake up by external
interrupts,watch Timer or RESET
1) All are stopped
2) can be wake up by external
interrupts or RESET
REV. 0.1, FEB. 14, 2003
26
MX10F201FC
Watchdog Timer
The Watchdog Timer (WDT) see Fig.14 , consists of an 11-bit prescaler and an 8-bit Timer formed by SFR T3. The
Timer is incremented every 1.5 ms, derived from the system clock frequency of 16 MHz by the following formula :
fTimer = fclk / (12 x (2048)). The 8-bit Timer increments every 12 x 2048 cycles of the on-chip oscillator. When a Timer
overflow occurs, the microcontroller is reset. The internal RESET signal is not inhibited when the external RST pin
is kept 0 into high impedance, no matter if the XTAL-clock is running or not.
To prevent a system reset the Timer must be reloaded in time by the application software. If the processor suffers
a hardware / software malfunction, the software will fail to reload the Timer. This failure will result in an overflow
thus prevent the processor from running out of control. This time interval is determined by the 8-bit reload value
that is written into register T3.
Watchdog time interval = [T3] x 12 x 2048 / oscillator frequency
The watch-dog Timer can only be reloaded if the condition flag WLE (SFR PCON bit 4) has been previously set
high by software. At the moment the counter is loaded WLE is automatically cleared.
In the idle state the watchdog Timer and reset circuitry remain active.
The watchdog Timer is controlled by the watchdog enable signal EW (SFR EBTCON bit 1). A LOW level enables
the watchdog Timer. A HIGH level disable the watchdog Timer.
Internal Bus
fCLK/12
Prescaler
(11-bit)
Timer T3
(8-bit)
Clear
LOAD LOADEN
to reset circuitry
Write T3
Clear
WLE
PCON. 4
PD
LOADEN
PCON. 1
EW
Internal Bus
Fig. 14 Watchdog Timer T3
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27
MX10F201FC
Pulse Width Modulated Outputs
The MX10F201FC contains two pulse width modulated output channels (see Figure. 15). These channels generate
pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which
supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter
counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two
registers: PWM0 and PWM1. Provided the contents of either of these registers is greater than the counter value,
the corresponding PWM0 or PWM1 output is set LOW. If the contents of these registers are equal to, or less than
the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the
registers PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments
of 1/255.
Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to
the contents of PWMn. The PWM outputs may also be configured as a dual DAC. In this application, the PWM
outputs must be integrated using conventional operational amplifier circuitry. If the resulting output voltages have
to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before
they are integrated. The repetition frequency fPWM, at the PWMn outputs is give by :
fOSC
2 x (1 + PWMP) x 255
fPWM =
This gives a repetition frequency range of 123Hz to 31.4KHz (fOSC = 16MHz). At fOSC = 24MHz, the frequency range
is 184Hz to 47.1KHz. By loading the PWM registers with either 00H or FFH, the PWM channels will output a
constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach
the value of the PWM registers when they are loaded with FFH.
When a compare register (PWM0 or PWM1) is loaded with a new value, the associated output is updated
immediately. It does not have to wait until the end of the current counter period. Both PWMn output pins are driven
by push-pull drivers. These pins are not used for any other purpose.
The PWM function is enabled by setting SPR EBTCON bit 2,3. After reset, SFR EBTCON bit 2,3 need to be set to
use P1.4 or P1.5 as the PWM output, otherwise P1.4& P1.5 are general I/O ports.
Prescaler frequency control register PWMP
Reset Value = 00H
PWMP (FEH) 7
6
5
4
3
2
1
MSB
PWMP.0-7
Prescaler dividsion factor = PWMP +1.
0
LSB
Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.
PWM0 (FCH)
PWM1 (FDH)
7
MSB
6
5
4
3
Reset Value = 00H
1
0
LSB
2
PWM0/1.0-7} Low/high ratio of PWMn =
EBTCON SFR (EBH)
7
-
6
-
5
-
4
-
(PWMn)
255 - ( PWMn)
3
PWM1E
2
1
PWM0E /EW
0
-
PWM1E : Selection of P1.4 function as either PWM output or a port line, After reset PWM1E bit is low, and P1.4
is a normal port line.
PWM0E : Selection of P1.5 function as either PWM output or a port line, After reset PWM0E bit is low, and P1.5
is a normal port line.
/EW : After reset, /EW bit is set, and WDT is disable.
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28
MX10F201FC
PWM0
8-BIT COMPARATOR
OUTPUT
BUFFER
PWM0
OUTPUT
BUFFER
PWM1
Internal Bus
tOSC
1/2
PRESCALER
8-BIT COUNTER
PWMP
8-BIT COMPARATOR
PWM1
Fig. 15 Functional Diagram of Pulse Width Modulated Outputs
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MX10F201FC
UART
This module is fully compatible to standard 80C51's UART.
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30
MX10F201FC
MTP Program Memory
Features
- 16 kilobyte electrically erasable internal MTP program momory.
- Programming and erasing voltage 12 Volt
- MTP (re) programming mechanism :
- EPROM like parallel programming protocol
- Parallel programming :
- Byte programming (8 us typical)
- Chip erase less than 0.5 second typical
- 100 minimum erase/program cycles
- Advanced CMOS flash memory technology
- One security bit to protect internal ROM code.
General Description
MX10F201FC's MTP memory stores memory contents even after 100 erase and program cycles. The cell is
designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel
oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.
The MX10F201FC uses 12 Volt VPP supply to perform the Program/Erase algorithms.
PROGRAMMING AND PROGRAM VERIFY
MX10F201FC is byte programmable by using 10us programming pulse and it requires separate program verify
pulse to read out the data to check if program is ok or not. The typical programming time for each 1k bytes is
about 10ms at room temperature.
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MX10F201FC
PROGRAMMING SPECIFICATION
Parallel Programming Mode
The parallel programming works in EPROM-like programming protocol. The MX10F201FC MTP provides 100 times
cycles endurance. And the MX10F201FC MTP needs a 11.5~12.5 Volt VPP supply to perform the Program/Erase
operation. Specially note that LOCK 2 is used to security protection. So if LOCK 2 bit is programmed, then PGMVFY,
ERSVFY and normal READ are disabled from parallel programming mode. LOCK 1 and LOCK 3 are not used in this
chip.
4.5/5.5V
VDD
1
RESET
0000
BP[3:0]
11.5V ~ 12.5V
VPP
PCEB
P33
POEB
P27
PWEB
P32
XTAL1
XTAL2
MX10F201FC
A[13:0]
P2[5:0] P1[7:0]
MS[3:0]
P26, P37, P31, P30
P0[7:0]
Q[7:0]
VSS
Table. 26 Pin Description
PIN NAME
P25~P20, P17~P10
P07~ P00
P33
P27
P32
VPP
P26, P37, P31, P30
VDD
VSS
SYMBOL
PA13~PA8, PA7~PA0
Q[7:0]
PCEB
POEB
PWEB
VPP
MS[3:0]
VDD
GND
FUNCTION
Address Input
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Program Supply Voltage
Flash Mode Selection
Power Supply Voltage (5V)
Ground Pin
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32
MX10F201FC
Table. 27 parallel programming modes
External
Pin
Module I/O
EA
PVPP
P2[5:0]
P1[7:0]
PCEB POEB PWEB PA[13:0]
Standby
Normal Read
12V
12V
1
0
X
0
X
1
Initialize
12V
0
1
Chip Erase
12V
0
1
Program
12V
0
1
Erase Verify
Program Verify
Pgm LOCK
12V
12V
12V
0
0
0
0
0
1
Erase Verify
LOCK
Pgm Verify
LOCK
Read Mft ID
Read DeviceID
12V
0
12V
12V
12V
Note :
P33
P27
P32
P26, P37, P0[7:0]
P31, P30
MS[3:0]
PUOUT[7:0]
PDOUT[7:0]
X
FF,00
0000
Data
DI or
DIA
X
Z
Lock[3:1]
0.5sec X
pulse
0.5sec X
pulse
1110
FF,00
X
000
0001
FF,00
X
000
PA[13:0]
0011
FF,00
D[7:0]
PA[13:0]
PA[13:0]
PA[1:0]
0100
0101
0110
Data
Data
FF,00
Z
Z
X
0
10us
pulses
1
1
10us
pulse
1
PA[1:0]=00
1001
LOCK[3:1]
Z
0
0
1
PA[1:0]=00
1011
LOCK[3:1]
Z
0
0
0
0
1
1
PA[1:0]=00
PA[1:0]=01
1111
1111
MftID(C2H)
Z
DeviceID(0DH) Z
X
PA[13:0]
P0[7:0]
Lock[i]
0 ->1
1. Program lock bits, program LOCK [1] to be 1 if PA [1:0] = 00
Program lock bits, program LOCK [2] to be 1 if PA [1:0] = 01
Program lock bits, program LOCK [3] to be 1 if PA [1:0] = 1x
2. Verify erased LOCK bits if PA [1:0] = 00
3. Verify programmed LOCK bits if PA [1:0] = 00
4. Read Manufacture ID, Device ID
PA [1:0] = 00 : Manufacture ID (C2H)
PA [1:0] = 01 : Device ID (0DH)
P/N:PM0730
REV. 0.1, FEB. 14, 2003
33
MX10F201FC
PROGRAM AND PROGRAM VERIFY FLOWCHART
START
First Address
VDD= 5V
VPP = 12V
X=0
Program One
10us pulse
No
Program
Verify
Fail
x=x+1
X=20
YES
Increment
Address
No
Last
Address
Yes
YES
Fail
Normal Read All
Fail Device
Pass
Pass Device
P/N:PM0730
REV. 0.1, FEB. 14, 2003
34
MX10F201FC
ERASE and VERIFY FLOWCHART
START
X=0
VDD= 5V
VPP = 12V
Program array all zero
(0 ~ 16KB) & LOCK
Chip Erase
(0.5s)
No
Erase Verify
LOCK
Erase Verify Array
(16KB)
fail
=>
x=x+1
X = 30
Yes
pass
Pass Device
Fail Device
P/N:PM0730
REV. 0.1, FEB. 14, 2003
35
MX10F201FC
PROGRAM LOCK AND PROGRAM VERIFY LOCK FLOWCHART
START
LOCK Address PA [1:0]
VDD= 5V
VPP = 12V
X=0
Program LOCK
10us pulse
No
Program
Verify LOCK
Fail
x=x+1
X=20
Yes
Pass
Fail Device
Pass Device
P/N:PM0730
REV. 0.1, FEB. 14, 2003
36
MX10F201FC
A. Timing diagram of Read signature and Normal read operations
VPP
WEB
ADDRESS
A 0=0 / A 0=1
tAA
CEB
OEB
tCE
tDF
tOE
MS[3:1]
tMSCE
DATA
Min.
Max.
unit
tMSCE
Mfg ID / Device ID
tAA
tCE
tOE
130
ns
130
ns
50
ns
OUT
tDF
0
20
ns
tMSCE
100
ns
P/N:PM0730
REV. 0.1, FEB. 14, 2003
37
MX10F201FC
B. Timing Diagram of Erase and Erase Verify Array Operation
Min.
Max.
unit
tVPS
2
us
tMS
200
ns
tCES
100
ns
tER
100
ns
P/N:PM0730
tEW
0.5
s
tEV
200
ns
tMSCE
100
ns
REV. 0.1, FEB. 14, 2003
38
MX10F201FC
C. Timing Diagram of Erase and Erase Verify LOCK Operation
Min.
Max.
unit
tVPS
tMS
tCES
tER
tEW
2
200
100
100
0.5
us
ns
ns
ns
P/N:PM0730
s
tEV
tMSCE
100
200
ns
ns
REV. 0.1, FEB. 14, 2003
39
MX10F201FC
D. Timing Diagram of Program and Program Verify Operation
Min.
Max.
unit
tAS
100
ns
tDS
100
ns
tDH
100
ns
tVPS
2
us
tCES
100
ns
tMS
200
ns
P/N:PM0730
tPR
100
ns
tPW
8
us
tPV
200
ns
tMSCE
100
ns
REV. 0.1, FEB. 14, 2003
40
MX10F201FC
E. Timing Diagram of Program LOCK and Program Verify LOCK Operation
PA [1:0]
PA [1:0] =00
0110
Min.
Max.
unit
tAS
100
ns
tDS
100
ns
tDH
100
ns
1011
tVPS
2
us
tCES
100
ns
tMS
200
ns
tPR
100
ns
tPW
8
us
tPV
200
ns
tMSCE
100
ns
Note : OUT = { xxxx, LOCK [3], LOCK [2], LOCK [1], x}
P/N:PM0730
REV. 0.1, FEB. 14, 2003
41
MX10F201FC
Limiting Value
SYMBOL
VDD
Vi
VVPP
IOL(max)
Tstg
Tamb
PARAMETER
Supply voltage
Input voltage (all inputs)
Voltage on VPP pin to VSS
Maximum IOL per I/O pin
Storage temperature
Operating ambient temperature(for all devices)
MIN
4.5
-0.5
0
-65
0
MAX
5.5
VDD + 0.5
13
15
150
70
UNIT
V
V
V
mA
O
C
O
C
MIN.
MAX.
UNIT
5.5
20
12
V
mA
mA
mA
mA
8
mA
100
uA
30
uA
DC ELEECTRICAL CHARACTERISTICS
SYMBOL
Supply
VDD
I DD
Normal operation supply voltage
Operation supply current
IID
Supply current in idle mode
ISLP
Supply current in single sleep mode
IDSLP
Supply current in dual sleep mode
IPD
Supply current in power-sown mode
Inputs
RINP
IL
VIH1
PARAMETER
Input resistance RESET
Input leakage current; RESET
Input high voltage to
XTAL1, XTAL3, RESET
PORTS P0~P3
VIL
Input low voltage
VIH
Input high voltage, except
XTAL1, XTAL3, RST
IIL
Logical 0 input current
ITL
Logical 1 to 0 transition current
CONDITIONS
TYP.
4.5
fOSC=16MHZ
fOSC=12MHZ
fOSC=4MHZ
fOSC=16MHZ
fOSC=12MHZ
fOSC=4MHZ
fOSC=16MHZ
fOSC=12MHZ
fOSC=4MHZ
fOSC=16MHZ
fOSC=12MHZ
fOSC=4MHZ
fOSC=16MHZ
fOSC=12MHZ
fOSC=4MHZ
VDD=4.5V to 5.5V
VDD=5V
10
8
4
8
6
2
4
3
1
50
45
25
1
1
1
15
0.7VDD
VIN=0.4V, VDD=5V
VIN=2.0V
P/N:PM0730
-0.5
0.2VDD
+0.9
-1
100
kohm
120
uA
VDD+0.5 V
0.2VDD-0.1 V
VDD+0.5 V
-100
-650
uA
uA
REV. 0.1, FEB. 14, 2003
42
MX10F201FC
Outputs : P0~P3
SYMBOL
PARAMETER
CONDITIONS
VOL
Output low voltage
VDD=4.5V, IOL=1.6mA
VOH
Output high voltage
VDD=4.5V, IOH=- 3.3mA
IOL
Low level output sink current
VO<0.4V, VDD=5V
IOH
High level pull-up output source current
Strong pull-up
VO=VDD-0.4V, VDD=5V
Weak pull-up
VO=VDD-0.4V, VDD=5V
CIO
Pin capacitance (except EA)
MIN.
TYP.
MAX.
0.4
VDD-0.7
10
13
4
15
6
30
UNIT
V
V
mA
15
mA
uA
pF
MAX.
UNIT
4.5
VDD
100
V
mV
6
6
20
20
kohm
kohm
Hz
Hz
LCD DRIVER CHARACTERISTICS
SYMBOL
Supply
VLCD
VSS
PARAMETER
LCD operation supply voltage
DC voltage component; all backplane
and segment drivers
LCD driver outputs
RBP
Output impedance BP0~BP3
RS
Output impedance S0~S31
fLCD
LCD scan frequency
CONDITIONS
Ratio: 1:1, 1:2, 1:4
Ratio: 1:3
P/N:PM0730
MIN.
TYP.
61
81
REV. 0.1, FEB. 14, 2003
43
MX10F201FC
RCP OSCILLATOR CHARACTERISTICS
5.5
100kohm
40kohm
5
4.5
3.3
3
2.7
9.36 9.19 8.7
7.4
6.48 6.15
15.98 14.81 14.29 10.95 10.12 8.99
Fosc - Vdd
20
15
100Kohm
MHz 10
40Kohm
5
0
5.5
5
4.5
3.3
3
2.7
V
AC CHARACTERISTICS
SYMBOL
PARAMETER
System (CPU) clock
fC
Oscillator frequency
32.768KHz LCD Oscillator
fxtal
32.768KHz Oscillator frequency
CONDITIONS
MIN.
TYP.
2
32.768
P/N:PM0730
MAX.
UNIT
16
MHz
KHz
REV. 0.1, FEB. 14, 2003
44
MX10F201FC
PACKAGE INFORMATION
100-PIN PQFP
A
ITEM
MILLIMETERS
INCHES
A
24.80 ± .40
.976 ± .016
B
20.00 ± .13
.787 ± .005
C
14.00 ± .13
.551 ± .005
D
18.80 ± .40
.740 ± .016
E
12.35 [REF]
.486 [REF]
F
.83 [REF]
.033 [REF]
G
.58 [REF]
.023 [REF]
H
.30 [Typ.]
.012 [Typ.]
I
.65 [Typ.]
.026 [Typ.]
J
2.40 [Typ.]
.094 [Typ.]
K
1.20 [Typ.]
.047 [Typ.]
L
.15 [Typ.]
.006 [Typ.]
M
.10 max.
.004 max.
N
2.75 ± .15
.108 ± .006
O
.10 min.
.004 min.
P
3.30 max.
.130 max.
NOTE: Each lead centerline is located within
.25mm[.01 inch] of its true position [TP] at a
maximum material condition.
B
80
81
51
50
E
F
31
100
1
C
D
P
0
3
O
G
H
I
J
N
L
M
K
P/N:PM0730
REV. 0.1, FEB. 14, 2003
45
MX10F201FC
REVISION
DESCRIPTION
PAGE
DATE
0.1
Modify Table. 15 INTCON SFR (C8H) --> (C0H)
P14
SEP/06/2002
P/N:PM0730
REV. 0.1, FEB. 14, 2003
46
MX10FM201FC
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
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CHICAGO OFFICE:
TEL:+1-847-963-1900
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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.