MCNIX MX97103

PRELIMINARY
MX97103
ISDN S/T-PCI TRANSCEIVER
FEATURE
• Single chip solution for ISDN PC card with PCI interface
• Supports full duplex 2B+D ISDN S/T transceiver according to ITU I.430
• Integrate S-interface, D & B channel protocol controllers, and PCI controller
• 32-bit PCI bus interface
•
•
•
•
•
•
•
Each B channel has 2x64 byte FIFO for each direction
D channel has 2x32 byte FIFO for each direction
EEPROM interface for loading vendor-specific data
One programmable LED
Comply to ACPI Rev 1.0
0.5u CMOS
100-pin PQFP package
GENERAL DESCRIPTION
MX97103 is a single chip solution for ISDN-S connection on PCI bus. It integrates S-transceiver, D and B
channel protocol controllers, and PCI interface.
The layer 1 block comprises of PDLL, DAC, RT and MFC
functions. DPLL's function is to establish S/T frame synchronization. DAC resolves the contention issue for
differnet TE accessing D channel at the same time. RT
deals with the receiving S/T data extraction and put out
the transmitted data at the corrent time slot. MFC is the
multiframing S and Q channel control block.
It can be divided into the following major functional blocks
: analog front end, layer 1 function, GCI interface. LAPD
controller, B channel HDLC controllers, EEPROM interface and PCI interface. The important function of each
major block will be described below.
GCI is the digital bus for the IC. It can accomodate 8
GCI-compatible devices. This block converts the frame
between GCI and S/T interface.
According to ITU 1.430 spec. the S/T interface is a 4wire interface. Among them, 2 wires are used for transmitting, and the other two are for receiving. The wiring
configurations include short passive bus, extended passive bus and point-to-point connection. For short passive bus, the operation distance is from 100m to 200m,
and the TEs(max 8)can be connected at random points
along the full length of the cable. For extended passive
bus, TEs connect to the cable at the far end from the NT.
The total length would be at least 500m and a differential distance between TE connection points is of 25 to
50m. For point-to-point connection, the cable length can
be 1km.
LAPD block relieves the microprocessor of the duty to
generate HDLC frame on the D channel. It can generate flag, CRC, address and control field automatically.
And it can generate S-frame for HDLC protocol. It contains 2 FIFO of 2x32 byte each to facilitate the D packet
transmission and reception.
Two B channel HDLC controllers can handle tasks like
flag and CRC generation, zero insertion and deletion.
For each direction a 2x64 byte FIFO is provided to buffer
the data.
The analog front end deals with the signals transmitted
to and received from the wiring cable. It accepts the
digital data from layer 1 block and converts them into
appropriate signals to be sent out to the wire, and it also
receive the attenuated and distorted signal from the wire
and recover them to be processed by layer 1 block.
The EEPROM interface is used to load specific vendor
information after system hardware reset. Vendor ID and
device ID can be load to distinguish different products.
If EEPROM is not used, default values will be set.
The PCI interface enables the chip attached to PCI bus
directly without any glue logic. The bus speed can be
from 25MHz to 33MHz.
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MX97103
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AD15
VSS
CBE1#
PAR
VDD
PERR#
STOP#
VSS
DEVSEL#
TRDY#
IRDY#
FRAME#
CBE2#
VSS
AD16
AD17
VSS
AD18
AD19
VDD
AD20
AD21
VSS
AD22
AD23
VSS
IDSEL
CBE3#
AD24
AD25
PIN CONFIGURATION
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
MX97103
VDD
AD26
AD17
VSS
AD28
AD29
VSS
AD30
AD31
VDD
CLK
VSS
RST#
INTA#
AVDD(C)
SX2
SX1
AVDDX
AVDD(P)
AVSS(P+X)
VSS
AD1
AD0
VDD
EEDO
EEDI
EECK
EECS
PME
TEST4
VSS
TEST3
TEST2
TEST1
LED1
VDD
DD
DU
FSC
DCL
VSS
SDS1
BCL
SDS2
VSS
XTAL2
XTAL1
AVSS(C)
SR2
SR1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
AD14
VSS
AD13
AD12
VDD
AD11
AD10
VSS
AD9
AD8
VSS
CBE0#
AD7
AD6
VSS
AD5
AD4
VDD
AD3
AD2
BLOCK DIAGRAM
GCI interface
DU DD
S/T Interface
LAP-D&B-HDLC
Transmitter
Multiframe Activation/
control Deactivation
GCI
B-channel
Switching
FIFOS
Receiver
DPLL
PCI
Interface
7.68MHZ
OSC
EEPROM
Interface
DCL FSC1
PCI bus
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MX97103
PIN DESCRIPTION
PAD#
42, 43, 45, 46, 48, 49,
51, 52, 56, 57, 59, 60,
62, 63, 65, 66, 80, 81,
83, 84, 86, 87, 89, 90,
93, 94, 96, 97, 99, 100,
2, 3
53, 68, 78, 92
PIN NAME
AD[31:0]
TYPE
I/O
DESCRIPTION
PCI address/data bus.
CBE[3:0]#
I
69
FRAME#
I
71
70
TRDY#
IRDY#
O
I
72
54
DEVSEL#
IDSEL
O
I
40
38
37
75
77
74
23
22
24
19
20
18
17
34
35
29
30
27
26
9
15
CLK
RST#
INTA#
PERR#
PAR
STOP#
BCL
SDS1
SDS2
FSC
DCL
DU
DD
SX1
SX2
SR2
SR1
XTAL1
XTAL2
LED2
LED1
I
I
O/D
I/O
I/O
O
O
O
O
O(I)
O(I)
I/O
I/O
O
O
I
I
I
O
O
O
PCI command/byte enable, command during address
phase, byte enable during data phase.
PCI FRAME# signal, asserted to indicate the start of a bus
transaction.
PCI Target ready, asserted by target agent.
PCI master ready, data transferred on the rising edge of
CLK when IRDY# and TRDY# both asserted.
PCI slave device select, specific for configuration cycle.
PCI Initialization device select, specific for configuration
cycle.
PCI clock, 33MHz
PCI bus reset
PCI bus interrupt request
PCI bus data error
PCI bus parity bit, even parity for AD and CBE
PCI stop signal
GCI bit clock, 768KHz
GCI serial data strobe 1, programmable strobe signal
GCI serial data strobe 2, programmable strobe signal
GCI frame sync
GCI data clock, 1.536MHz
GCI data upward to ST interface
GCI data downward from ST interface
S-bus transmitter output(positive)
S-bus transmitter output(negative)
S-bus receiver input
S-bus receiver reference
Connection for 7.68MHz crystal/oscillator input
Crystal output
Auxillisry LED output 0
Auxilliary LED output 1
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MX97103
PAD#
8
7
6
5
10, 12, 13, 14
36, 33, 32
31, 28
4, 16, 41, 50, 61,
76, 85, 98
1, 11, 21, 25, 39,
44, 47, 55, 58, 64,
67, 73, 79, 82, 88,
91, 95
PIN NAME
EECS
EECK
EEDI
EEDO
TEST[4:1]
AVDD
AVSS
VDD
VSS
TYPE
O
O
O
I
DESCRIPTION
EEPROM chip select
EEPROM interface clock
Output data to EEPROM
Input data from EEPROM
test pins
Analog power
Analog ground
Digital power
Digital ground
ABSOLUTE MAXIMUM RATINGS
Supply Voltage(VDD)
DC Input Voltage(Vin)
DC Output Voltage(Vout)
Storage Temperature Range(Tstg)
Power Dissipation(PD)
Lead Temp.(TL)(Soldering, 10sec)
ESD Rating(Rzap=1.5k, Czap=100pf)
Clamp Diode Current
4.75V to 5.25V
-0.5V to VDD+0.5V
-0.5V to VDD+0.5V
-55°C to 150°C
500mW
260°C
2000V
±20mA
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MX97103
DC CHARACTERISTICS
PCI BUS D.C SPECS
PCI System signals
CLK, RST#
PCI Shared signals
AD[31:0](t/s), CBE[3:0]#(t/s), FRAME#(s/t/s), TRDY#(s/t/s), IDSEL(in), IRDY#(s/t/s), STOP#(s/t/s),
DEVSEL#(s/t/s), PAR(t/s), PERR#(s/t/s), INTA#(o/d), SERR#(s/t/s)
Temperature from 0 to 70°C; VDD=5V±5%, VSS=0V, AVSS=0V
SYMBOL
PARAMETER
CONDITIONS
MIN. VALUE
VIL
L-input voltage
VIH
VOL
H-input voltage
L-output voltage
VOH
IIL
IIH
CI/O
CCLK
CL
H-output voltage
L-input current
H-input current
Input/output capacitance
CLK input capacitance
Load capacitance
2.0V
IOL1=3mA
IOL2=6mA
IOH=-2mA
VIN=0.5V
VIN=2.7V
at 1MHz
at 1MHz
MAX. VALUE
0.8V
5.4V
0.45V
NOTES
1
2.4V
-70uA
70uA
10pF
17pF
50pF
NOTE:
1. IOL2 applies to signals with external pull-ups: FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#
GCI BUS & EEPROM INTERFACE D.C. SPECS
GCI signals:
BCL, DCL, DD, DU, FSC.SDS1, SDS2
EEPROM signals:
EECS, EECK, EEDI, EEDO
SYMBOL
PARAMETER
VIL
L-input voltage
VIH
H-input voltage
VOL
L-output voltage
VOH
H-output voltage
CONDITIONS
MIN. VALUE
2.0V
IOL1=2mA
IOL2=7mA
IOH=-400uA
MAX. VALUE
0.8V
5.4V
0.45V
NOTES
1
2.4V
NOTE:
1. IOL2 is for DD only.
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MX97103
S-BUS D.C. SPECS
SX1, SX2, SR1, SR2
SYMBOL
PARAMETER
VX
Absolute value of output
pulse amplitude
(VSX2-VSX1)
IX
Transmitter output
current
RX
Transmitter output
impedance
VSR1
VTR
Receive output voltage
Receiver threshold
voltage (VSR2-VSR1)
CONDITIONS
RL=50 ohm
RL=400 ohm
MIN. VALUE
2.03V
2.10V
MAX. VALUE
2.31V
2.39V
RL=5.6 ohm
7.5mA
13.4mA
(1) Inactive or during
binary 1, (2) during
binary 0 RL=50 ohm
(1)10K ohm
(2) 0 ohm
IO<5uA
Dependent on peak
level
2.35V
225mV
2.6V
375mV
NOTES
SX1, SX2
SR1, SR2
SR1, SR2
NOTE:
1. Due to the transformer, the load resistance seen by the circuit is four times RL.
CRYSTAL SPEC
27pF
XTAL1
External
oscillator
signal
XTAL1
XTAL2
NC
XTAL2
CL
CL
27pF
Crystal mode
PARAMETER
Frequency
Frequency calibration tolerance
Load capacitance
Oscillator mode
Driving from external source
SYMBOL
f
CL
LIMIT VALUES
7.680
max. 100
max. 35
fundamental
UNIT
MHz
ppm
pF
XTAL1 CLOCK CHARACTERISTICS
PARAMETER
Duty cycle
LIMIT VALUES
MIN.
MAX.
1:2
2:1
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MX97103
AC CHARACTERISTICS
Temperature from 0 to 70°C, VDD=5V±5%
Inputs are driven to 2.4V for a logical "1" and to 0.4V for
a logical "0". Timing meansurements are made at 2.0V
for a logical "1" and 0.8v for a logical "0". The AC-testing
output is loaded with a 150pF capacitor.
2.4
2.0
2.0
TEST POINTS
0.8
0.8
0.45
DUT
C=150pF
Input/Output waveform for AC tests
TIMING WAVEFORM
SERIAL INTERFACE TIMING
DCL
tBCD
BCL
tFSD
FSC
tSSD
SDS1/2
tIOD
DD/DU(O)
tIIS
tIIH
DD/DU(I)
GCI TIMING
PARAMETER
GCI output data delay
GCI input data setup
GCI input data hold
FSC strobe delay
SDS strobe delay
Bit clock delay
SYMBOL
tIOD
tIIS
tIIH
tFSD
tSDD
tBCD
MIN.
20ns
20ns
20ns
-20ns
MAX.
100ns
20ns
120ns
20ns
-20ns
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MX97103
PCI SHARED SIGNALS A.C. TIMING WAVEFORM
1.5V
CLK
t2
t1
OUTPUT
1.5V
Valid
t4
t3
Valid
INPUT
t5
t6
PARAMETER
CLK signal valid delay
CLK to signal invalid delay
Hi-Z to active delay from CLK
Active to Hi-Z delay from CLK
Input signal valid setup time before CLK
Input signal hold time from CLK
SYMBOL
t1
t2
t3
t4
t5
t6
MIN.
MAX.
11ns
NOTES
CL=50pF
2ns
2ns
28ns
7ns
0ns
PCI SIDEBAND SIGNALS A.C. TIMING WAVEFORM
1.5V
CLK
t2
t1
OUTPUT
1.5V
Valid
t4
t3
Valid
INPUT
t5
t6
PARAMETER
CLK to sideband signal valid delay
CLK to signal invalid delay
Hi-Z to active delay from CLK
Active to Hi-Z delay from CLK
Sideband signal valid setup time before CLK
Input signal hold time from CLK
SYMBOL
t1
t2
t3
t4
t5
t6
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MIN.
MAX.
12ns
NOTES
CL=50pF
2ns
2ns
28ns
12ns
0ns
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MX97103
APPLICATION
ISDN ACCESS ARCHITECTURE
ISDN User Area
ISDN
central office
TE(1)
U
T
S
TE(8)
LT-S
TE(1)
LT-S
TE(1)
LT-S
LT-T
NT1
LT
telephone
line
PBX(NT2)
NT1
TE(8)
LT
Direct Subscriber Access
PCI bus
= MX97103
where - TE is an ISDN terminal
- LT-S is a subscriber line termination
- LT-T is a trunk line termination
- LT is a trunk line termination in the central office
GCI CONNECTION
GCI
Data
Encryption
DSP-COFI
EEPROM
Speech
Processing
MX97103
S interface
PCI BUS
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MX97103
VDD
C3
C4
18pf
VDD
OSC
18pf
7.68MHz
XTAL1 XTAL2
VDD
10uF
R7
3.3K
DO
DI EEPROM
SK
(6 bit)
CS
EEDO
EEDI
EECK
EECS
DCL
FSC
DD
DU
DCLK
FS CODEC
DR
DX
VSS
R9
3.3K
R10
3.3K
AVSS
VDD
D1 D2 D3
MX97103
R1
SX1
+5V
2:1
33
D5
D4
D6 D7
R3
SX2
DC point
33
R5
8.2K
R4
SR1
1.8K
47pF
INTAN
RSTN
FRAMEN
R6
1.8K
SR2
47pF
2:1
Overvoltage
Protection
circuits
RJ45
D8 D9
D11
D10
D12 D13 D14
R8
8.2K
+5V
DC point
CLK STOPN PAR PERRN TARDYN IDSELN IRDYN IDSEL CBEN[3:0] AD[31:0]
PCI BUS
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MX97103
TEST CIRCUIT
To test digital function separately, DTMC[TMODE] can be set to enable the stimulus inputs from test1~4 pins.
PIN
DTMC SP2 SP1 SP0 I/O SIGNAL DESCRIPTION
TEST1
1
X
X
X
I
XRAMI1 test RAMI1 input signal
TEST2
1
X
X
X
I
XRAMI2 test RAMI2 input signal
TEST3
1
X
X
X
I
XZC
test ZC input signal
TEST4
1
X
X
X
I
XI0N
test I0N input signal
TEST1
0
0
0
0
O
ARAMI1 RAMI1 from analog module
TEST2
0
0
0
0
O
ARAMI2 RAMI2 from analog module
TEST3
0
0
0
0
O
AZC
ZC from analog module
TEST4
0
0
0
0
O
SAMP
SAMP from analog module
TEST1
TEST2
TEST3
TEST4
TEST1
TEST2
TEST3
TEST4
TEST1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
O
O
O
O
O
O
O
O
O
S[0]
S[1]
S[2]
S[3]
MBAS1
MBAS2
CLS
AI0N
RFN
activation/deactivation state code
TIC bus arbitration state code
D channel collision
I0N from analog module
layer sync.
For normal operation, DTMC should be set to 0. Test1~4 pins can be programmed to output internal signals for
monitoring purpose.
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MX97103
PACKAGE INFORMATION
100-PIN PLASTIC QUAD FLAT PACKAGE (PQFP)
A
ITEM
MILLIMETERS
INCHES
A
24.80±.40
.967±.016
B
20.00±.13
.787±.005
C
14.00±.13
.551±.005
D
18.80±.40
.740±.016
E
12.35 [REF]
.486 [REF]
F
.83 [REF]
.033 [REF]
G
.58 [REF]
.023 [REF]
H
.30 [Typ.]
.012 [Typ.]
I
.65 [Typ.]
.026 [Typ.]
J
2.40 [Typ.]
.094 [Typ.]
K
1.20 [Typ.]
.047 [Typ.]
L
.15 [Typ.]
.006 [Typ.]
M
.10 max.
.004 max.
N
2.75±.15
.018±.006
O
.10 min.
.004 min.
P
3.30 max.
.103 max.
B
80
81
51
50
E
F
31
30
100
1
C
D
P
O
G
H
I
J
N
L
M
NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condition.
K
ORDERING INFORMATION
PART NO.
MX97103FC
PACKAGE
100-PIN PQFP
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MX97103
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
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TEL:+81-44-246-9100
FAX:+81-44-246-9105
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TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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