QUAD MULTIPLEXER/LATCH FEATURES The SY100S355 offers four transparent latches with differential outputs and is designed for use in highperformance ECL systems. The Select inputs (S0, S1) select one of the two sources of input data (D0 or D1) to the latch. The Select inputs can also force the outputs to a logic LOW when the latch is in the transparent mode. The latches are in the transparent mode when both Enables (E1, E2) are at a logic LOW state. In the transparent mode, the Select inputs can pass an input logic HIGH from D0 or D1 to the output. If the Select inputs are tied together, then input data from either D0 or D1 is always passed through. A rising edge on either Enable input will latch the outputs with the most recent data at the latch inputs being stored. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75KΩ pull-down resistors. BLOCK DIAGRAM S1 D0a S0 Qa Qa PIN CONFIGURATIONS D0b D1a VEES 11 10 9 8 7 6 5 D0a Qa Qa VEE VEES MR D1a E1 E2 D0b CD Qb Qb D0c D Q Qc D1c E CD Qc 19 20 21 22 23 24 25 D1b E Qc Qc S0 Q VCC VCC S1 D Qb VCCA E1 MR VEE CD Top View PLCC J28-1 Qb E2 E 4 3 2 1 28 27 26 Qd Q 12 13 14 15 16 17 18 D1d Qd D S0 S1 VEES D0c D1c D0d D1d Qd 1 24 23 22 21 20 19 18 D1b 2 3 17 16 D0b D1a 15 14 D0a Qa Qd 6 Top View Flatpack F24-1 4 5 13 7 8 9 10 11 12 Qa Qd E E1 CD Qb Qb Q VCC VCCA D D1d Qc D0d Qc ■ ■ ■ ■ Max. propagation delay of 1100ps Max. enable to output delay of 1400ps IEE min. of –80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 50% faster than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages D1b ■ DESCRIPTION D0c D1c D0d ■ ■ ■ ■ ■ SY100S355 Qd E2 MR Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S355 Micrel TRUTH TABLE(1) PIN NAMES Pin Inputs Function E1 – E2 Enable Inputs (Active LOW) S0, S1 Select Inputs MR Master Reset Dna – Dnd Data Inputs Qa – Qd Data Outputs Qa — Qd Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Outputs MR E1 E2 S1 S0 D1X D0X QX QX H L L L X L L L X L L L X H H L X H H L X H L X X X X H H L H L L H L H L L L L L L L L L L L L L L H H L H L L X X H X L X X H H H L L L L H H L L L L H X L X H H X X L X X L X X L X X H L Latched Latched NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current S0, S1 E1, E2 Dna, Dnd MR Power Supply Current Min. Typ. Max. — — — — — — — — 220 350 340 430 –80 –57 –40 2 Unit Condition µA VIN = VIH (Max.) mA Inputs Open SY100S355 Micrel AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Dna – Dnd to Output (Transparent Mode) 300 1200 300 1200 300 1200 ps tPLH tPHL Propagation Delay S0, S1 to Output (Transparent Mode) 300 1500 300 1500 300 1500 ps tPLH tPHL Propagation Delay E1, E2 to Output 300 1500 300 1500 300 1500 ps tPLH tPHL Propagation Delay MR to Output 300 1200 300 1200 300 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dna – Dnd S0, S1 MR (Release Time) 700 1200 1000 — — — 700 1200 1000 — — — 700 1200 1000 — — — Hold Time Dna – Dnd S0, S1 400 400 — — 400 400 — — 400 400 — — tPW (L) Pulse Width LOW, E1, E2 1000 — 1000 — 1000 — ps tPW (H) Pulse Width HIGH, MR 1000 — 1000 — 1000 — ps tH Parameter TA = +25°C Condition ps ps PLCC VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Dna – Dnd to Output (Transparent Mode) 300 1100 300 1100 300 1100 ps tPLH tPHL Propagation Delay S0, S1 to Output (Transparent Mode) 300 1400 300 1400 300 1400 ps tPLH tPHL Propagation Delay E1, E2 to Output 300 1400 300 1400 300 1400 ps tPLH tPHL Propagation Delay MR to Output 300 1100 300 1100 300 1100 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dna – Dnd S0, S1 MR (Release Time) 700 1200 1000 — — — 700 1200 1000 — — — 700 1200 1000 — — — Hold Time Dna – Dnd S0, S1 300 300 — — 300 300 — — 300 300 — — tPW (L) Pulse Width LOW, E1, E2 1000 — 1000 — 1000 — ps tPW (H) Pulse Width HIGH, MR 1000 — 1000 — 1000 — ps tH ps ps 3 Condition SY100S355 Micrel TIMING DIAGRAMS 0.7 ± 0.1 ns –0.95V Dna – Dnd S0, S1 –1.69V tpw –0.95V ENABLE TRANSPARENT TRANSPARENT LATCHED –1.69V tPHL, tPLH tPHL, tPLH tPHL, tPLH 80% 50% 20% OUTPUT tTHL, tTLH Enable Timing RESET TIMING DATA LATCHED TRANSPARENT ENABLE TRANSPARENT tR RELEASE TIME RESET/SET tpw tPHL, tPLH tPHL, tPLH OUTPUT Reset Timing 4 tPHL, tPLH SY100S355 Micrel TIMING DIAGRAMS –0.95V S0, S1 50% tS –1.69V tH –0.95V DATA 50% tS –1.69 tH –0.95V E1, E2 50% –1.69V Data Set-up and Hold Times NOTES: 1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND 2. ts is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code 5 Package Type Operating Range SY100S355FC F24-1 Commercial SY100S355JC J28-1 Commercial SY100S355JCTR J28-1 Commercial SY100S355 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 6 SY100S355 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. 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