TI TPS40322RHBT

TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
Dual Output or Two-Phase Synchronous Buck Controller
FEATURES
DESCRIPTION
•
The TPS40322 is a dual-output, synchronous buck
controller. It can also be configured as a
single-output, two-phase controller. The 180°
out-of-phase operation reduces the input current
ripple and extends the input capacitor lifetime.
Bi-directional master/slave synchronization function
provides evenly distributed phase shift for a
four-output system that reduces input ripple further
and attenuates the system noise.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual- or Multi-phase Synchronous Buck
Controller
180° Out-of-Phase Reduces Input Ripple
Input Voltage Range from 3 V to 20 V
Output Voltage Range: 0.6 V to 5.6 V
Adjustable Frequency 100 kHz to 1 MHz
Bidirectional SYNC with 0°/180° or 90°/270°
Phase Shift
Voltage Mode Control With Input Feed-forward
Accurate Current Sharing for Multi-phase
Operation
Individual PowerGood Outputs
Individual Enable and Programmable Soft
Start, With Pre-bias Start-up
±0.5%, 600-mV Reference
Output UV/OV Protection and Input
Undervoltage Lockout
Individual Overcurrent Limit Setting
Hiccup Overcurrent Protection
Accurate Inductor DCR or Resistive Current
Sensing
Remote Sense for Multi-phase Applications
Internal N-Channel FET Drivers
Integrated Bootstrap Switches
Available in 5 mm × 5 mm 32-Pin QFN Package
The wide input range can support 3.3-V, 5-V, and
12-V buses. The accurate reference voltage satisfies
the precision voltage need of the modern ASICs and
potentially
reduces
the
output
capacitance
requirement. Separate PGOOD signals provide
flexibility for system monitoring and sequencing. The
two channels are independently controlled and each
soft-start time is programmable. Voltage mode control
is implemented to reduce noise sensitivity and also
ensures low duty ratio conversion.
.
SIMPLIFIED APPLICATION CIRCUIT
26
VIN
3V
to
20 V
20
31 UVLO
APPLICATIONS
•
•
•
•
•
BP6
VDD
24 HDRV1
HDRV2 16
25 BOOT1
BOOT2 15
23 SW1
Multiple Rail Systems
Telecom Base Station
Switcher/Router Networking
xDSL Broadband Access
Server and Storage System
SW2 17
22 LDRV1
LDRV2 18
21 PGND1
PGND2 19
30 ILIM1
ILIM2 11
28 CS1+
CS2+ 13
VOUT2
TPS40322
VOUT1
29 CS1–
CS2– 12
27 PG1
PG2 14
4
FB1
9
DIFFO
5
COMP1
2
RT
FB2
8
COMP2
7
SYNC
1
PHSET 32
EN/SS1 AGND EN/SS2
3
6
10
UDG-10215
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
TEMPERATURE RANGE
PINS
PACKAGE
ORDERING NUMBER
–40°C to 125°C
32
QFN
TPS40322RHB
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted)
VALUE
VDD
SW1, SW2 (2)
UNIT
MIN
MAX
–0.3
22
V
–3
27
V
–5
V
30
V
SW1, SW2 (<100 ns pulse width) (2)
Voltage Range
BOOT1, BOOT2 (2)
–0.3
BP6
–0.3
7
V
–2
30
V
All other pins
–0.3
7
V
TJ Operating temperature
–40
145
°C
Tstg Storage temperature
–55
150
°C
HDRV1, HDRV2 (2)
Temperature
Electrostatic disharge
Human Body Model (HBM)
2000
V
Charged Device Model (CDM)
1500
V
Soldering
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
BOOT to SW and HDRV to SW are relative measurements.
RECOMMENDED OPERATING CONDITIONS
VVDD
Input operating voltage
TJ
Operating junction temperature
2
MIN
MAX
3
20
UNIT
V
–40
125
°C
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
THERMAL INFORMATION
TPS40322
THERMAL METRIC (1)
QFN
UNITS
32 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
37.3
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
10.0
ψJT
Junction-to-top characterization parameter (5)
0.4
ψJB
Junction-to-board characterization parameter (6)
9.9
θJCbot
Junction-to-case (bottom) thermal resistance (7)
2.7
(1)
(2)
(3)
(4)
(5)
(6)
(7)
28.6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2011, Texas Instruments Incorporated
3
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VVDD = 12 V, RRT = 40 kΩ, fSW = 500 kHz (unless otherwise noted),
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
20
V
200
250
µA
6
8
mA
1.21
1.24
1.27
V
13
15
17
μA
6.2
6.5
6.8
V
50
100
mV
INPUT SUPPLY
VDD
Input voltage range
IDDSDN
Shutdown
VENx/SSx = 0 V
3
IDDQ
Quiescent, non-switching
VFB = 0.65 V, ENx/SSx float
UVLO
UVLO
Minimum turn-on voltage
UVLOHYS
Hysteresis current
BP REGULATOR
BP
Regulator voltage
7 ≤ VVDD ≤ 20 V
VDO
Regulator dropout voltage
IBP = 25 mA, VVDD = 3 V
IBP
Regulator continuous current limit (1)
100
VBPUVLO
Regulator output UVLO
2.40
2.70
2.95
V
VBPUVLO-HYS
Regulator output UVLO hysteresis
180
210
250
mV
1000
kHz
550
kHz
mA
OSCILLATOR/ RAMP GENERATOR
100
fSW
Oscillator frequency
VRAMP
Ramp amplitude (preak-to-peak)
VVAL
Valley voltage
fSYNC
SYNC frequency range
200
tPW(sync)
SYNC input minimum pulse width
100
VH(sync)
Rising edge threshold to set sync pulse
VL(sync)
Falling edge threshold to reset sync pulse
fMASTER
Master clock frequency
ΔfSYNC
Percent of master frequency for synchronization
VPHSET
RRT = 40 kΩ
450
3 V < VVDD < 20 V
500
VDD/8.5
V
0.85
V
2000
ns
2
V
0.8
200
2000
–20%
20%
Master
0°/180° phase shift
Slave
0°/180° phase shift
0.6
Slave
90°/270° phase shift
2.1
kHz
V
kHz
0.5
V
2.0
V
V
PWM
PWM(off)
Minimum PWM off-time
tON(min)
Minimum controllable pulse width
See
90
tDEAD
Output driver dead time
HDRV off to LDRV on
20
35
40
ns
tDEAD
Output driver dead time
LDRV off to HDRV on
20
35
40
ns
0°C < TJ < 70°C
597
600
603
mV
–40°C < TJ < 125°C
594
600
606
20
75
(1)
130
90
ns
ns
ERROR AMPLIFIER AND VOLTAGE REFERENCE
VFB
FB input voltage
IFB
FB input bias current
GBWP
Unity gain bandwidth
See
(1)
AVOL
Open loop gain
See
(1)
IOH
IOL
(1)
4
nA
24
MHz
High-level output current
3
mA
Low-level output current
9
mA
80
dB
Specified by design. Not production tested.
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VVDD = 12 V, RRT = 40 kΩ, fSW = 500 kHz (unless otherwise noted),
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
ENABLE/SOFT START
VIH
High-level input voltage
0.55
0.70
1.00
VIL
Low-level input voltage
0.23
0.26
0.30
V
ISS
Soft-start source current
8
10
12
μA
VSS
Soft-start voltage level
0.8
V
IDISCHG
Soft-start discharge current
130
μA
OVERCURRENT PROTECTION
IILIM
ILIM program current
tHICCUP
Hiccup cycles to recover
TJ = 25°C
9.5
10.0
10.5
6
μA
Cycles
CURRENT SENSE AMPLIFIER
VDIFF
Differential input voltage range
VCM
Input common mode range
ACS
Current sensing gain
VCSOUT
Current sense amplifier output
fC0
Closed loop bandwidth (2)
Current sense amplifier output difference
between CH1 and CH2
–60
60
0
5.6
15
VCSIN = 20 mV, TJ = 25°C
270
300
V
V/V
330
3
VCSIN = 20 mV to both CS1 and CS2
mV
mV
MHz
–15
15
mV
OVERVOLTAGE/UNDERVOLTAGE PROTECTION
VOVP
Feedback voltage limit for OVP
679
700
735
mV
VUVP
Feedback voltage limit for UVP
475
500
525
mV
GATE DRIVERS
RHDHI
High-side driver pull-up resistance
VBOOT – VSW = 6.5 V, IHDRV = –40 mA
0.8
1.5
2.5
Ω
RHDLO
High-side driver pull-down resistance
VBOOT – VSW = 6.5 V, IHDRV = 40 mA
0.5
1.0
1.6
Ω
RLDHI
Low-side driver pull-up resistance
ILDRV = –40 mA
0.8
1.5
2.5
Ω
RLDLO
Low-side driver pull-down resistance
ILDRV = 40 mA
0.35
0.60
1.30
tHRISE
High-side driver rise time
CLOAD = 5 nF, See
(2)
15
ns
tHFALL
High-side driver fall time
CLOAD = 5 nF, See
(2)
12
ns
tLRISE
Low-side driver rise time
CLOAD = 5 nF, See
(2)
15
ns
tLFALL
Low-side driver fall time
CLOAD = 5 nF, See (2)
10
ns
Bootstrap switch voltage drop
IBOOT = 5 mA
0.1
V
VIOFSET
Input offset voltage
VDIFFO = 0.9 V
Gain
Differential gain
BW
Close loop bandwidth (2)
VDIFFO
Output voltage at DIFFO pin
ISRC
Output source current
1
mA
ISNK
Output sink current
1
mA
Ω
BOOT SWITCH
VDFWD
REMOTE SENSE
–2
2
mV
0.995
1.005
V/V
2.00
MHz
VBP6-0.2
V
POWERGOOD
VOV
Feedback voltage limit for PGOOD
650
675
697
mV
VUV
Feedback voltage limit for PGOOD
510
525
545
mV
VPGD(hyst)
PGOOD hysteresis voltage at FB
25
40
mV
RRGD
PGOOD pull down resistance
50
70
Ω
IPGD(leak)
PGOOD leakage current
20
µA
THERMAL SHUTDOWN
TSD
Junction shutdown temperature
See
(2)
150
°C
TSD(hyst)
Hysteresis
See
(2)
20
°C
(2)
Specified by design. Not production tested.
Copyright © 2011, Texas Instruments Incorporated
5
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS
1.2355
UVLO Hysteresis Current (µA)
15.8
UVLO Turn−On Voltage (V)
1.2350
1.2345
1.2340
1.2335
1.2330
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
15.6
15.4
15.2
15.0
14.8
14.6
14.4
−40 −25 −10
110 125
Figure 1. UVLO Turn-On Voltage vs. Junction Temperature
10.9
10.8
10.7
10.6
10.5
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
Non−Switching Quiescent Current (mA)
Soft−Start Current (µA)
11.0
10.4
6.35
6.30
6.25
6.20
6.15
6.10
6.05
6.00
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
Figure 4. Non-Switching Quiescent Current vs. Junction
Temperature
2.80
BP UVLO Threshold Voltage (V)
601.5
Error Amplifier Feedback Voltage (V)
6.40
5.95
−40 −25 −10
G001
Figure 3. Soft-Start Current vs. Junction Temperature
601.0
600.5
600.0
599.5
599.0
598.5
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G001
Figure 5. Error Amplifier Feedback Voltage vs. Junction
Temperature
6
110 125
6.45
11.1
598.0
−40 −25 −10
95
Figure 2. UVLO Hysteresis Current vs. Junction
Temperature
11.2
10.3
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
Falling
Rising
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G001
Figure 6. BP UVLO Threshold vs. Junction Temperature
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
780
290
760
High Level Input Voltage (mV)
Low Level Input Voltage (mV)
TYPICAL CHARACTERISTICS (continued)
300
280
270
260
250
240
230
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
680
660
640
10.3
10.2
10.1
10.0
9.9
95
110 125
0.8
0.6
0.4
0.2
0.0
−0.2
−0.4
−40 −25 −10
Switching Frequency (kHz)
105.8
1.0000
0.9999
0.9998
0.9997
0.9996
0.9995
95
110 125
G001
105.6
105.4
105.2
105.0
104.8
104.6
104.4
104.2
110 125
G001
Figure 11. Remote Sense Gain vs. Junction Temperature
Copyright © 2011, Texas Instruments Incorporated
5
20 35 50 65 80
Junction Temperature (°C)
Figure 10. Remote Sense Input Offset Voltage vs. Junction
Temperature
1.0001
95
G001
1.0
106.0
5
20 35 50 65 80
Junction Temperature (°C)
110 125
1.2
1.0002
0.9994
−40 −25 −10
95
1.4
G001
Figure 9. Current Limit vs. Junction Temperature
5
20 35 50 65 80
Junction Temperature (°C)
Figure 8. ENx High-Level Inout Voltage vs. Junction
Temperature
Remote Sense Input Offset Voltage (V)
ILIM1 Program Current (µA)
10.4
9.8
Remote Sense Gain
700
G001
10.5
5
20 35 50 65 80
Junction Temperature (°C)
720
620
−40 −25 −10
110 125
Figure 7. ENx Low-Level Inout Voltage vs. Junction
Temperature
9.7
−40 −25 −10
740
RRT = 200 kΩ
VVDD = 12 V
104.0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G001
Figure 12. Frequency vs. Junction Temperature
7
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
520
Switching Frequency (kHz)
Switching Frequency (kHz)
1040
1035
1030
1025
1020
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
Figure 13. Frequency vs. Junction Temperature
8
500
490
480
470
460
RRT = 20 kΩ
VVDD = 12 V
1015
−40 −25 −10
510
G001
VVDD = 7 V
VVDD = 12 V
VVDD = 14 V
VVDD = 20 V
450
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
RRT = 40 kΩ
95
110 125
G001
Figure 14. Frequency vs. Junction Temperature
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
BP6
Linear
Regulator
VDD 26
AGND
BG
6
BP6
VREF
PWM
Logic
CS1+ 28
25 BOOT1
+
24 HDRV1
VREF
FB1
4
EN1/SS1
3
+
+
–
–
–
23 SW1
20 BP6
22 LDRV1
10 ?A
COMP1
Σ
PWM1
Anti-Cross
Conduction
Ramp1
CS1- 29
21 PGND1
ISHARE
5
BP6
VREF
FB2
8
EN2/SS2/GSNS
10
+
–
–
–
Σ
+
15 BOOT2
PWM2
Ramp2
16 HDRV2
COMP2
Anti-Cross
Conduction
10 ?A
7
CS2+ 13
+
OC
FB1
CS2- 12
FB2
ILIM1 30
OC
UV
OV
Detect
17 SW2
BP6
18 LDRV2
UV
19 PGND2
OV
ILIM2/VSNS 11
27 PG1
UVLO 31
14 PG2
DIFFO
9
SYNC
1
RT
2
R
RAMP1
Ramp
Generator
PHSET 32
R
VSNS
+
RAMP2
R
GSNS
R
UDG-10216
NOTE
•
•
•
In multi-phase mode, the EN2/SS2/GSNS pin becomes the GSNS pin and the ILIM2/VSNS pin
becomes the VSNS pin.
The two channels are identical unless specified.
The following naming conventions are used to better describe the functions. For example,
COMPx refers to COMP1 and COMP2, FBx refers to FB1 and FB2.
Copyright © 2011, Texas Instruments Incorporated
9
TPS40322
SLUSAF8 – JUNE 2011
UVLO
ILIM1
CS1–
CS1+
PG1
VDD
32
31
30
29
28
27
26
BOOT1
PHSET
www.ti.com
SYNC
1
25
24
RT
2
23
SW1
EN1/SS1
3
22
LDRV1
FB1
4
21
PGND1
COMP1
5
20
BP6
AGND
6
19
PGND2
7
18
LDRV2
8
17
SW2
10
11
12
13
14
15
16
CS2–
CS2+
PG2
BOOT2
HDRV2
DIFFO
9
ILIM2/VSNS
FB2
EN2/SS2/GSNS
COMP2
TPS40322RHB
HDRV1
PIN FUNCTIONS
NAME
PIN
I/O
AGND
6
–
Low noise ground connection to the controller.
BOOT1
25
I
BOOT1 provides a bootstrapped supply for the high-side FET driver for channel 1 (CH1). Connect a
capacitor (0.1 μF typical) from BOOT1 to SW1 pin.
BOOT2
15
I
BOOT2 provides a bootstrapped supply for the high-side FET driver for channel 2 (CH2). Connect a
capacitor (0.1 μF typical) from BOOT2 to SW2 pin.
BP6
20
O
Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor with a value of 3.3
μF or greater from this pin to the power ground plane.
COMP1
5
O
Output of the error amplifier 1 and connection node for loop feedback components.
COMP2
7
O
Output of the error amplifier 2 and connection node for loop feedback components.
CS1–
29
I
Negative terminal of current sense amplifier for CH1
CS1+
28
I
Positive terminal of current sense amplifier for CH1
CS2–
12
I
Negative terminal of current sense amplifier for CH2
CS2+
13
I
Positive terminal of current sense amplifier for CH2
DIFFO
9
O
Output of the differential amplifier. When the device is configured for dual channel mode, the DIFFO pin
must be either floating or tied to BP6
I
Logic level input which starts or stops CH1. Letting this pin float turns CH1 on. Pulling this pin low disables
CH1. This is also the soft-start programming pin. A capacitor connected from this pin to AGND programs
the soft-start time. The capacitor is charged with an internal current source of 10 μA. The resulting voltage
ramp of this pin is also used as a second non-inverting input to the error amplifier 1 after a 0.8 V (typical)
level shift downwards.
EN1/SS1
3
DESCRIPTION
EN2/SS2/GSNS
10
I
Logic level input which starts or stops CH2. Letting this pin float turns CH2 on. Pulling this pin low disables
CH2. This is also the soft-start programming pin. A capacitor connected from this pin to AGND programs
the soft-start time. The capacitor is charged with an internal current source of 10 μA. The resulting voltage
ramp of this pin is also used as a second non-inverting input to the error amplifier 2 after a 0.8 V (typical)
level shift downwards.In multi-phase mode, this pin becomes GSNS as the negative terminal of a remote
sense amplifier.
FB1
4
I
Inverting input to the error amplifier. During normal operation, the voltage on this pin is equal to the internal
reference voltage.
FB2
8
I
Inverting input to the error amplifier. During normal operation, the voltage on this pin is equal to the internal
reference voltage. Connecting the FB2 pin to the BP6 pin enables multi-phase mode and disables the error
amplifier 2.
HDRV1
24
O
Bootstrapped gate drive output for the high-side N-channel MOSFET for CH1. A 2-Ω resistor is
recommended for a noisy environment.
10
Copyright © 2011, Texas Instruments Incorporated
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SLUSAF8 – JUNE 2011
www.ti.com
PIN FUNCTIONS (continued)
NAME
PIN
I/O
DESCRIPTION
HDRV2
16
O
Bootstrapped gate drive output for the high-side N-channel MOSFET for CH2. A 2-Ω resistor is
recommended for a noisy environment.
ILIM1
30
I
Used to set the overcurrent limit for CH1 with 10 μA of current flowing through a resistor from this pin to
AGND.
ILIM2/VSNS
11
I
Used to set the overcurrent limit for CH2 with 10 μA of current flowing through a resistor from this pin to
AGND. In multi-phase mode, this pin becomes VSNS as the positive terminal of a remote sense amplifier.
LDRV1
22
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH1.
LDRV2
18
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH2.
PG1
27
O
Open drain power good indicator for CH1 output voltage.
PG2
14
O
Open drain power good indicator for CH2 output voltage.
PGND1
21
-
Power ground 1. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce
channel to channel interference.
PGND2
19
-
Power ground 2. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce
channel to channel interference.
PHSET
32
I
Used to set master or slave mode and phase angles. The master emits a 50% duty clock to the slave. The
slave synchronizes to the external clock and select the phase shift angle.
RT
2
I
Connect a resistor from this pin to AGND to set the oscillator frequency.
SW1
23
I
Connect to the switched node on converter CH1. It is the return for the CH 1 high-side gate driver.
SW2
17
I
Connect to the switched node on converter CH2. It is the return for the CH 2 high-side gate driver.
SYNC
1
I/O
UVLO
31
I
A resistor divider from VIN determines the input voltage that the controller starts.
VDD
26
I
Power input to the controller. A low ESR bypass ceramic capacitor of 0.1 μF or greater should be
connected closely from this pin to AGND.
In master mode, a 2x free running frequency clock is sent out on SYNC pin.
In slave mode, sync to an external clock which is ±20% of the free running MASTER_CLOCK frequency.
The MASTER_CLOCK frequency is 2x of the free running frequency (set by RT) and operates at 50% duty
cycle.
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TPS40322
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FUNCTIONAL DESCRIPTION
General Description/Control Architecture
The TPS40322 is a flexible synchronous buck controller. It can be used as a dual-output controller, or as a
multi-phase single-output controller. It operates with a wide input range from 3 V to 20 V and generates accurate
regulated output as low as 600 mV.
In dual output mode, voltage mode control with input feed-forward architecture is implemented. With this
architecture, the benefits are less noise sensitivity, no control instability issues for small DCR applications, and a
smaller minimum controllable on-time, often desired for high conversion ratio applications.
In two-phase single-output mode, a current-sharing loop is implemented to ensure a balance of current between
phases. Because the induced error current signal to the loop is much smaller when compared to the PWM ramp
amplitude, the control loop is modeled as voltage mode with input feed-forward.
DESIGN NOTE
•
When the device is operating in dual output mode, DIFFO must be floating or tied to BP6.
Voltage Reference
The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 0.5-% tolerance on the reference voltage allows the user to design a very accurate power
supply.
Output Voltage Setting
The output voltages of the TPS40322 are set by using external feedback resistor dividers as shown in Figure 15.
The regulated output voltage (VOUT) is determined by Equation 1.
RA
VOUTx
COMPx
+
RBIAS
VREF
UDG-11111
Figure 15. Setting the Output Voltage
æ
RA ö
VOUT = 0.6 V ´ ç 1 +
÷
è RBIAS ø
12
(1)
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Input Voltage Feed-Forward
The TPS40322 uses input voltage feed-forward to maintain a constant power stage gain as the input voltage
varies and provides very good response to input voltage transient disturbances. The simple constant power
stage gain of the controller greatly simplifies feedback loop design because the loop characteristics remain
constant as the input voltage changes, unlike a typical buck converter without voltage feed-forward. For modeling
purposes, the gain from the COMP pin to the average voltage at the input of the L-C filter is typically 8.5 V/V.
Current Sensing
The TPS40322 uses a differential current sense design to sense the output current. The sense element can be
either the series resistance of the power stage filter inductor or a separate current sense resistor. When using
the inductor series resistance as shown in Figure 16, an R-C filter must be used to remove the large AC
component voltage across the inductor so that only the component of the voltage that remains is across the
resistance of the inductor. (See Figure 16)
The values of R1 and C1 for an ideal design can be calculated using Equation 2. The time constant of the R-C
filter should equal the time constant of the inductor itself. If the time constants are equal, the voltage across C1
equals the current in the inductor multiplied by the inductor resistance. The inductor ripple current is reflected in
the voltage across C1. Typically a capacitor with a value of 0.1-µF is recommended for C1.
Please refer to the LAYOUT CONSIDERATIONS section for proper placement of the sensing elements.
VIN
L1
L
DCR
R1
VOUT1
C1
+
VC
R1´ C1 =
L1
DCR
(2)
–
CS1–
CS1+
UDG-11112
Figure 16. Inductor DCR Current Sensing
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Overcurrent Protection
The TPS40322 has dedicated ILIM pins for each channel for use when operating in dual-output mode. When
operating in multi-phase mode, both channels share the same overcurrent level set by ILIM1. The overcurrent
level is set with a resistor connected from the ILIMx pin to analog ground. The sensed current signal is amplified
by the CS amplifier with a gain of 15, and then compared with the established overcurrent level to determine if
there is an OC fault. This design is shown in Figure 17.
IOUT
L1
L
DCR
VOUT1
SW1
R1
C1
CS1+
CS1–
ACS=15
+
ILIM1
10 A
+
OC
RILIM
UDG-11114
Figure 17. Overcurrent Protection
Equation 3 shows the current limit resistance (RLIM) calculation for desired overcurrent limit.
æ
æ IRIPPLE ö ö
ç IOC + ç
÷ ´ DCR ´ A CS
2 ÷ø ø
è
è
RLIM =
IILIM
where
•
•
•
•
•
IOC is the desired DC over current limit level
IRIPPLE is the inductor peak-peak ripple current
DCR is the inductor DC resistance
ACS is the current sensing amplifier gain (typically 15)
IILIM is the internal source current out of ILIMx pin (typically 10 µA)
(3)
The TPS40322 implements cycle-by-cycle current limit when the inductor peak current has exceeded the set
limit. When the controller counts three consecutive clock cycles of an overcurrent condition, the high-side and
low-side MOSFETs are turned off and the controller enters a hiccup mode. After six soft-start cycles, normal
switching is attempted. If the overcurrent has cleared, normal operation resumes, otherwise the sequence
repeats.
14
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Multi-Phase Mode and Current Sharing Loop
The TPS40322 can be configured to operate in single-output multi-phase mode for high-current applications.
With proper selection of the external MOSFETs, this device can support up to 50-A of load current in a
multi-phase configuration. As shown in Figure 18, to configure TPS40322 as multi-phase mode, FB2 is tied to
BP6. In this mode, COMP1 must be connected to COMP2 to ensure current sharing between the two phases.
For high-current applications, the remote sense amplifier is used to compensate for the parasitic offset to provide
an accurate output voltage. The EN2/SS2 and ILIM2 pins are designed for multiple functions. They are used as
VSNS and GSNS for remote sensing in a multi-phase mode. DIFFO, which is the output of the remote sensing
amplifier, is connected to the resistor divider of the feedback network.
Power Stage
RPARASITIC
L
O
A
D
COMP2
COMP1
FB2
RPARASITIC
BP6
R
GSNS
ILIM2/VSNS
R
+
VSNS
EN2/SS2/GSNS
R
R
DIFFO
+
VREF
FB1
COMP1
UDG-11113
Figure 18. Multi-phase Mode Configuration
When the device operates in multi-phase mode, a current sharing loop as shown in Figure 19 is designed to
maintain the current balance between phases. Both phases share the same comparator voltage (COMP1). The
sensed current in each phase is compared first in a current share block, then an error current and fed into
COMP. The resulted error voltage is compared with the voltage ramp to generate the PWM pulse.
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IO1
L1
DCR
L
SW1
VOUT
R1
C1
CS1+
CS1–
ISNS2
ISNS1
ISHARE Block
+
FB1
+
VREF
–
+
PWM1
COMP1
PWM2
+
–
+
ISNS2
ISHARE Block
ISNS1
CS2+
CS2–
C2
R2
IO2
L
DCR
SW2
L2
VOUT
UDG-11115
Figure 19. Multi-phase Mode Current Share Loop
16
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Startup and Shutdown
Startup Sequence
When the ENx/SSx pin is pulled below 0.3 V, the respective channel is disabled. When ENx/SSx is released, the
controller starts automatically and an internal 40-µA current source begins to charge the external soft-start
capacitor. When the voltage across the soft-start capacitor is over 0.7 V, the internal BP regulator is enabled.
The ENx/SSx voltage is clamped to 1.3 V while waiting for signals indicating that BP6, VDD, and the oscillator
clock are good. After all the signals are confirmed, ENx/SSx is discharged to 0.4 V with a 140-µA current source,
and then charged again with the internal 10-µA current source. The operation is described by the waveform
shown in Figure 20. VSS_INT is an internal signal level shifted from ENx/SSx and then connected to the
non-inverting terminal of the error amplifier.
The soft-start time is determined by the internal charge current and the external capacitance. The actual output
ramp-up time is the time for the internal current source to charge the capacitor through a 600 mV range. There is
some initial lag time due to the offset (800 mV typical) from the actual ENx/SSx pin voltage to VSS_INT. The
soft-start sequence takes place in a closed loop fashion, meaning that the error amplifier controls the output
voltage constantly during the soft-start period and the feedback loop is never open (as occurs in duty cycle limit
soft-start designs). The error amplifier has two non-inverting inputs, one connected to the 600-mV reference
voltage, and the other connected to the offset VSS_INT. The error amplifier controls the FB pin to the lower of
these two voltages. As the voltage on the ENx/SSx pin ramps up past approximately 1.4 V (800 mV offset
voltage plus the 600 mV reference voltage), the 600 mV reference voltage becomes the dominant input and the
converter has reached its final regulation voltage.
Equation 4 shows how to calculate the soft start capacitance.
Voltage (V)
VEN1/SS1
t ´I
CSS = SS SS
600mV
where
1.3
•
0.8
VSS_INT
0.4
•
•
CSS is the soft start capacitance
connected to ENx/SSx pin
tSS is the desired soft-start time
ISS is the internal soft-start current
(typically 10 µA)
(4)
Time
Figure 20. EN/SS Start-Up Waveform
Pre-Biased Output Start-Up
The TPS40322 contains a circuit that prevents current from being pulled from the output during the start-up
sequence in a pre-biased output condition. There are no PWM pulses until the internal soft-start voltage rises
above the error amplifier input (FBx pin), if the output is pre-biased. Once the soft-start voltage exceeds the error
amplifier input, the device slowly initiates synchronous rectification by starting the synchronous rectifier with a
narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated
by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a
pre-biased output, and ensures the output voltage start-up and ramp-to-regulation sequences are smooth and
controlled.
DESIGN NOTE
During the soft-start sequence, when the PWM pulse width is shorter than the minimum
controllable on-time, which is generally caused by the PWM comparator and gate driver
delays, pulse skipping may occur and the output might show larger ripple voltage.
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Shutdown
During the shutdown sequence, BP6 is controlled by ENx/SSx. If both of ENx/SSx pins are pulled low, BP6 is
turned off regardless of the input voltage remaining higher than programmed UVLO threshold.
Switching Frequency and Master/Slave Synchronization
The switching frequency is set by the value of the resistor connected from the RT pin to AGND. The RT resistor
value is calculated in Equation 5.
RRT =
20 ´ 109
fSW
where
•
•
RRT is the the resistor from RT pin to AGND, in Ω
fSW is the desired switching frequency, in Hz
(5)
The TPS40322 device can also synchronize to an external clock that is ±20% of the master clock frequency
which is two times the free running frequency. Each TPS40322 can be set by the PHSET pin as either master or
slave. The master produces a 50% duty cycle clock to the slave. The slave synchronizes to the external clock
with 50% duty cycle and selects the phase shift angle as shown in Table 1.
Figure 21 shows an example on synchronizing two TPS40322 devices to generate an evenly distributed shift to
reduce input ripple.
Table 1. Phase Shift Angle Selection
PHSET
CONNECTION
MODE
RANGE
(V)
PHASE ANGLE (°)
CH1
CH2
AGND
< 0.5
Master
0
180
Floating
0.6 to 2
Slave
0
180
High
> 2.1
Slave
90
270
XXXX
XXXX
TPS40322
Master
PHSET
PWM1
PWM1
0°
PWM2
PWM2
180°
PWM1
PWM1
90°
PWM2
PWM2
270°
SYNC
TPS40322
Slave
SYNC
BP6
PHSET
UDG-11117
Figure 21. Synchronizing Two TPS40322 Devices
18
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Overvoltage and Undervoltage Fault Protection
The TPS40322 has output overvoltage protection and undervoltage protection capability. The comparators that
regulate the overvoltage and undervoltage conditions use the FBx pin as the output sensing point so the filtering
effect of the compensation network connected from COMPx to FBx has an effect on the speed of detection. As
the output voltage rises or falls below the nominal value, the error amplifier attempts to force FBx to match its
reference voltage. When the error amplifier is no longer able to do this, the FB pin begins to drift and trip the
overvoltage threshold (VOVP) or the undervoltage threshold (VUVP) as described in the ELECTRICAL
CHARACTERISTICS table.
When an undervoltage fault is detected, the TPS40322 enters hiccup mode and resumes normal operation when
the fault is cleared.
When an overvoltage fault is detected, the TPS40322 turns off the high-side MOSFET and latches on the
low-side MOSFET to discharge the output current to the regulation level (within the power good window)
When operating in dual-channel mode, both channels have identical but independent protection schemes which
means one channel would not be affected when the other channel is in fault mode.
When operating in multi-phase mode, only the FB1 pin is detected for overvoltage and undervoltage fault.
Therefore both channels take action together during a fault.
Input Undervoltage Lockout (UVLO)
A dedicated UVLO pin allows the user to program the desired input turn-on threshold voltage. The diagram is
shown in Figure 22. The desired input turn-on threshold can be calculated using Equation 6. The input turn off
hysteresis can be calculated using Equation 7.
15 mA
VIN
æ (RON1 + RON2 ) ö
VIN _ UVLO = 1.24 V ´ ç
÷
ç
÷
RON2
è
ø
(6)
VIN _ HYS = 15 mA ´ RON1
(7)
RON 1
UVLO
+
VIN_OK
RON 2
TPS40322
UDG-11118
Figure 22. Input UVLO Diagram
Power Good
The TPS40322 provides an indication that output is good for each channel. This is an open-drain signal and pulls
low when any condition exists that would indicate that the output of the supply might be out of regulation. These
conditions include:
• Feedback voltage (VFB) is more than ±12.5% from nominal
• Soft-start is active
Thermal Shutdown
If the junction temperature of the device reaches the thermal shutdown limit of 150°C, the PWMs and the
oscillators are turned off and HDRVs and LDRVs are driven low. When the junction cools to the required level
(130°C typical), the PWM initiates soft start as during a normal power-up cycle.
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LAYOUT CONSIDERATIONS
Power Stage
A synchronous BUCK power stage has two primary current loops. The input current loop carries high AC
discontinuous current while the output current loop carries high DC continuous current. The input current loop
includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground
path back to the input capacitors. To maintain the loop as small as possible, it is generally good practice to place
some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the
synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop
includes the SR MOSFET, the inductor, the output capacitors, and the ground return between the output
capacitors and the source of the SR MOSFET. As with the input current loop, the ground return between the
output capacitor ground and the source of the SR MOSFET should be routed under the inductor and SR
MOSFET to minimize the power loop area. The SW node area should be as small as possible to reduce the
parasitic capacitance and minimize the radiated emissions. The gate drive loop impedance
(HDRV-gate-source-SW and LDRV-gate-source- GND) should be kept to as low as possible. The HDRV and
LDRV connections should widen to 20 mils as soon as possible out from the device pin.
Device Peripheral
The TPS40322 provides separate signal ground (AGND) and power ground (PGND1 and PGND2) pins. It is
required to properly separate the circuit grounds. The return path for the pins associated with the power stage
should be through PGND. The other pins (especially for those sensitive pins such as FB1, FB2, RT, ILIM1, and
ILIM2) should be through the low noise AGND. The AGND and PGND planes are suggested to be connected at
the output capacitor with single 20-mil trace. A minimum 0.1-µF ceramic capacitor must be placed as close to the
VDD pin and AGND as possible with at least 15-mil wide trace from the bypass capacitor to the AGND. A
minimum value of 3.3-µF ceramic capacitor should be connected from BP6 to PGND, placed as close to the BP6
pin as possible. When DCR sensing method is applied, the sensing resistor should be placed close to the SW
node and connected to the inductor with a Kelvin connection. The sensing traces from the power stage to the
chip should be away from the switching components. The sensing capacitor should be placed very close to the
CS+ and CS- pins for each output. The frequency setting resistor should be placed as close to RT pin and AGND
as possible. In multi-phase mode, the ILIM2/VSNS and EN2/SS2/GSNS pins should be directly connected to the
point of load where the voltage regulation is required. A parallel pair of 10-mil traces connects the regulated
voltage back to the chip. They should be away from the switching components. The PowerPAD™ should be
electrically connected to AGND.
PowerPAD™ Layout
The PowerPAD™ package provides low thermal impedance for heat removal from the device. The PowerPAD™
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD™ package.
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz. copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a
diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD™
Thermally Enhanced Package (TI LIterature Number SLMA002) for more information on the PowerPAD™
package.
20
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TPS40322 Design Example 1
Dual-Output Configuration from 12-V Nominal to 1.2-V and 1.8-V DC-to-DC Converter Using the
TPS40322
The following example illustrates the design process and component selection for a dual output synchronous
buck converter using the TPS40322 controller. The design goal parameters are listed in Table 2.
Table 2. TPS40322 Dual Output Design Example Specification
PARAMETER
TEST CONDITION
MIN
NOM
8
12
MAX
UNIT
INPUT CHARACTERSTICS
VIN
Input voltage
VIN(ripple)
Input ripple
IOUT1 = IOUT2 = 10 A
15
V
0.25
V
OUTPUT 1 CHARACTERSTICS
Output voltage
IOUT1(min) ≤ IOUT1 ≤ IOUT1(max)
Line regulation
VIN(min) ≤ VIN ≤ VIN(max)
0.5%
Load regulation
IOUT1(min) ≤ IOUT1 ≤ IOUT1(max)
0.5%
VRIPPLE1
Output ripple
IOUT1 = IOUT1(max)
VOVER1
Output overshoot
ΔIOUT1 = 5 A
40
VUNDER1
Output undershoot
ΔIOUT1 = 5A
40
IOUT1
Output current
VIN(min) ≤ VIN ≤ VIN(max)
ISCP1
Short circuit current trip point
VOUT1
1.2
V
24
0
mV
mV
mV
10
15
A
A
OUTPUT 2 CHARACTERSTICS
VOUT2
Output voltage
IOUT2(min) ≤ IOUT2 ≤ IOUT2(max)
Line regulation
VIN(min) ≤ VIN ≤ VIN(max)
0.5%
0.5%
Load regulation
IOUT2(min) ≤ IOUT2 ≤ IOUT2(max)
VRIPPLE2
Output ripple
IOUT2 = IOUT2(max)
VOVER2
Output overshoot
ΔIOUT2 = 5 A
VUNDER2
Output undershoot
ΔIOUT2 = 5 A
IOUT2
Output current
VIN(min) ≤ VIN ≤ VIN(max)
ISCP2
Short circuit current trip point
1.8
V
36
40
mV
40
0
mV
mV
10
A
15
A
2
ms
GENERAL CHARACTERSTICS
tSS
Soft-start time
VIN = 12 V
η
Efficiency
VIN = 12 V, IOUT1= IOUT2 = 10 A
fSW
Switching frequency
88%
500
kHz
Design Procedure
Equations and calculations are shown regarding VOUT1. VOUT2 values can be calculated using similar equations.
Selecting a Switching Frequency
To maintain acceptable efficiency and meet minimum on-time requirements, a 500kHz switching frequency is
selected.
Inductor Selection (L1)
Synchronous BUCK power inductors are typically sized for approximately 20% - 40% peak-to-peak ripple current
(IRIPPLE). Given a target ripple current of 30%, the required inductor size, at maximum rated output current, can
be calculated using Equation 8.
VIN(max) - VOUT1 VOUT1
1
15 V - 1.2 V 1.2 V
1
L1 »
´
´
=
´
´
= 0.736 mH
0.3 ´ IOUT1
VIN(max) fSW
0.3 ´ 10 A
15 V 500kHz
(8)
Selecting a standard, readily available inductor, with a rated inductance is 0.88 µH at 10 A, IRIPPLE1 = 2.5 A
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The RMS current through the inductor is approximated by the equation:
2
1 ´I
12 RIPPLE1
(I ( ) ) + (
IL1(rms ) =
L1 avg
2
)
2
=
(IOUT1 )2 + (112 ´ IRIPPLE1 )
2
= 102 + (112 ´ 2.5 ) = 10.026 A
(9)
Output Capacitor Selection (C10 through C16)
The selection of the output capacitor is typically driven by the output transient response requirement.
Equation 10and Equation 11 over-estimate the voltage deviation to account for delays in the loop bandwidth and
can be used to determine the required output capacitance:
2
VOVER1 <
DIOUT1
DI
DI
´ L1 (DIOUT1 ) ´ L1
´ Dt = OUT1 ´ OUT1
=
COUT1
COUT1
VOUT1
VOUT1 ´ COUT1
(10)
2
VUNDER1 <
(DIOUT1 ) ´ L1
DIOUT1
DI
DI
´ L1
´ Dt = OUT1 ´ OUT1
=
COUT1
COUT1 VIN - VOUT1 (VIN - VOUT1 )´ COUT1
(11)
When VIN(min) > 2 x VOUT1, use the overshoot equation, VOVER1, to calculate minimum output capacitance. When
VIN(min) < 2 x VOUT1 use Equation 11, VUNDER1, to calculate minimum output capacitance. In this design example,
VIN(min) is much larger than 2 x VOUT1 so Equation 12 is used to determine the required minimum output
capacitance.
COUT1(min) =
(DIOUT1 )2 ´ L1
VOUT ´ VOVER1
=
52 ´ 0.88 mH
= 458 mF
1.2 ´ 40mV
(12)
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is
approximated by Equation 13.
æ
ö
IRIPPLE1
æ
ö
2.5 A
VRIPPLE1 - ç
÷ 24mV - ç
÷
VRIPPLE1 - VRIPPLE(cap)
è 8 ´ COUT1 ´ fSW ø =
è 8 ´ 458 mF ´ 500kHz ø = 9mW
=
ESRMAX =
IRIPPLE1
IRIPPLE1
2.5 A
(13)
Two 220-µF, 4-V, aluminum electrolytic capacitors were chosen for load response requirements. Additionally two
0805 10-µF, X7R, along with two 0603, 3.3-µF X5R, and one 1-µF, X5R ceramic capacitors are selected for low
ESR and high frequency decoupling.
Peak Current Rating of Inductor
With the output capacitance known, it is possible to calculate the charge current during start-up and determine
the minimum saturation current rating for the inductor. The start-up charging current is approximated using
Equation 14.
´ COUT1 1.2 V ´ (2 ´ 220 mF + 2 ´ 10 mF + 2 ´ 3.3 mF + 1mF )
V
=
= 0.281A
ICHARGE = OUT1
tSS
2ms
1
IL1(peak ) = IOUT1(max) + (
2 ´ IRIPPLE1
(14)
1
)+ ICHARGE = 10 A + ( 2 ´ 2.5A )+ 0.281A = 11.53 A
(15)
Table 3. Inductor Requirements Summary
PARAMETER
VALUE
UNITS
0.88
µH
RMS current (thermal rating)
10.026
A
Peak current (saturation rating)
11.53
A
L1
Inductance
IL1_RMS
IL1_PEAK
22
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A 744314110 from Wurth-Midcom with 1.1-µH zero current inductance is selected. Inductance for this part is
0.88-µH at 10 A bias. This 15-A, 3.15 mΩ inductor exceeds the minimum inductor ratings in a 7 mm x 7 mm
package.
Input Capacitor Selection (C3 through C6)
The input voltage ripple is divided between the capacitance and ESR of the input capacitor. For this design
VRIPPLE(cap) = 200 mV and VRIPPLE(esr) = 50 mV. The minimum capacitance and maximum ESR are estimated
using Equation 16.
IOUT1 ´ VOUT1
10 A ´ 1.2 V
=
= 15 mF
CIN1(min) =
VRIPPLE(cap) ´ VIN(min) ´ fSW 200mV ´ 8 V ´ 500kHz
(16)
ESRMAX =
VRIPPLE(esr)
1 ´I
2 RIPPLE1
IOUT1 + (
=
)
50mV
= 4.44mW
11.25 A
(17)
The RMS current in the input capacitors is estimated using Equation 18.
IRMS(cin1) = IOUT1 ´ D ´ (1 - D ) = 10 A ´ 0.15 ´ (1 - 0.15) = 3.57 A
(18)
V
D = OUT1
VIN(min)
(19)
To achieve these goals, two 0805, 10-µF capacitors, one 0605, 1.0-µF capacitor and one 0402, 0.1-µF X5R
ceramic capacitor are combined at the input.
MOSFET Selection (Q1)
Texas Instruments CSD86330, 20-A power block device was chosen. This device incorporates the high-side and
low-side MOSFETs in a single 3 mm x 3 mm package. The high-side MOSFET has an on-resistance (RDS(on)) of
8.8 mΩ, while the low-side on-resistance (RDS(on)) is 4.6 mΩ, both at 4.5 V gate voltage. A 5.11-Ω gate resistor is
used on the HDRV pin on each device for added noise immunity.
ILIM Resistor (R2)
The output current is sensed across the DCR of the L1 output inductor. An RC combination having a time
constant equal to that of the L1 inductance and the DCR is used to extract the current information as a voltage. A
standard capacitor value of 0.1-µF is used. The resistor, R13, can be calculated using Equation 20.
L1
0.88 mH
=
= 2.8kW
R13 =
C ´ VDCR 0.1mF ´ 3.15mW
(20)
A standard 3.09-kΩ resistor was selected.
This design limits the maximum voltage drop across the current sense inputs, VCS(max), to 60 mV. If the voltage
drop across the DCR of the inductor is greater than VCS(max), after allowing for 30% overshoot spikes and a 20%
variation in the DCR value, then a resistor is added to divide the voltage down to 60 mV. The divider resistor,
R15, is calculated by Equation 21.
R13 ´ VCS(max )
R15 =
VDCR - VCS(max )
)
(
where
VDCR = (DCR ´ 1.2 )´ IL(peak ) ´ 1.3
(
)
(22)
(22)
The TPS40322 uses the negative drop across the low-side FET at the end of the “OFF” time to measure the
inductor current. Allowing for 20% over the minimum current limit for transient recovery and 20% rise in RDS(on)Q2
for self-heating of the MOSFET, the voltage drop across the low-side FET at current limit is given by
Equation 23.
Copyright © 2011, Texas Instruments Incorporated
23
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
éæ
ù
éæ
ù
I
2.5 A ö
ö
VOC = êç IOUT1 + RIPPLE1 ÷ ´ 1.2ú ´ (DCR ´ 1.2 ) = êç 10 A +
÷ ´ 1.2ú ´ (3.15mW ´ 1.2 ) = 51.05mV
2
2
ø
ø
ëè
û
ëè
û
(23)
The current limit resistor is calculated using the minimum ILIM programming current, IILIM(min), the maximum
current sense amplifier gain, ACS(max), and taking into account the current sense amplifier minimum input offset
voltage, VOS(min).
(V
=
OC
RILIM
)
´ A CS(max ) - VOS(min )
IILIM(min)
51.05mV ´ 16 V )- (-3mV )
(
V
=
= 86.29kW » 86.6kW
9.5 mA
(24)
Feedback Divider (R10, R14)
The TPS40322 controller uses a full operational amplifier with an internally fixed 0.600-V reference. Tha value for
R10 is selected between 10-kΩand 50-kΩ for a balance of feedback current and noise immunity. With the R10
resistor set to 20-kΩ, the output voltage is programmed with a resistor divider given by Equation 25.
VFB ´ R10
0.600 V ´ 20.0kW
R14 =
=
= 20kW
VOUT1 - VFB
1.2 V - 0.600 V
(25)
Compensation: (R11, R12, C17, C19, C21)
Using the TPS40k Loop Stability Tool for an 85-kHz bandwidth and 50° of phase margin with an R10 value of
20.0 kΩ, and measuring the theoretical results in the laboratory and modifying accordingly for system
optimization yields the following values.
• C21 = 10 pF
• C17 = 220 pF
• C19 = 470 pF
• R12 = 4.42 kΩ
• R11 = 82.5 kΩ
Boot-Strap Capacitor (C7)
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to < 100 mV.
QG1
7nC
CBOOST =
=
= 70nF » 100nF
VBOOT(ripple ) 100mV
(26)
General Device Components
Synchronization (SYNC Pin)
The SYNC pin can be left open for independent dual outputs.
RT Resistor (R6)
The desired switching frequency is programmed by the current through RRT to GND. the value of RRT is
calculated using Equation 27.
RRT =
209
209
=
= 40kW » 40.2kW
fSW 500kHz
(27)
Differential Amplifier Out (DIFFO Pin)
In dual output configuration the DIFFO pin is not used and must remain open (unconnected).
EN/SS Timing Capacitors (C8)
The soft-start capacitor provides smooth ramp of the error amplifier reference voltage for controlled start-up. The
soft-start capacitor is selected using Equation 28.
24
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
t ´I
2ms ´ 10 mA
CSS = SS SS =
» 33nF
VFB
0.6 V
(28)
Power Good (PG1, PG2 Pins)
PG1 and PG2 can each be pulled up to BP6 through a 100-kΩ resistor, or remain not-connected. For sequencing
the start-up of output 1 before output 2, connect PG1 to EN2/SS2; for sequencing the startup of output 2 before
output 1, connect PG2 to EN1/SS1.
Phase Set (PHSET Pin)
The PHSET pin can be connected to ground or connected to the BP6 pin for connections to ground (GND).
UVLO Programming Resistors (R1 and R3)
The UVLO hysteresis level is programmed by R1 with Equation 29 and Equation 30.
VUVLO(on ) - VUVLO(off ) 8 V - 7 V
=
= 66.7kW » 68.1kW
RUVLO(hys ) =
IUVLO
15 mA
RUVLO(set ) > RUVLO(hys ) ´
VUVLO(max)
(VUVLO(on _ min) - VUVLO(max) )
= 68.1kW
1.25 V
= 12.6kW » 12.7kW
8.0
( V - 1.25 V )
(29)
(30)
VDD Bypass Capacitor (C2)
As shown in the ELECTRICAL CHARACTERISTICS table, a 0.1-µF, 50-V, X7R capacitor has been selected for
VDD bypass.
VBP6 Bypass Capacitor (C18)
Per the TPS40322 datasheet, select a 3.3-µF (or greater) low ESR capacitor for BP6. For this design a 3.3-µF,
X5R ceramic capacitor was chosen
Schematic
Figure 23 shows the dual output converter schematic for this design example
Copyright © 2011, Texas Instruments Incorporated
25
TPS40322
SLUSAF8 – JUNE 2011
+
+
+
+
+
www.ti.com
Figure 23. Design Example 1, Dual Output Converter Schematic
26
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
Typical Performance Characteristics
95
95
VOUT = 1.2 V
90
85
80
80
Efficiency (%)
85
70
65
60
50
0
1
2
3
4
5
6
7
Output Current (A)
8
9
65
55
50
10
VIN = 8 V
VIN = 12 V
VIN = 15 V
VOUT = 1.8 V
0
1
2
G001
Figure 24. Efficiency vs Load Current (8 V to 15 V
to 1.2 V at 10 A, Design Example 1)
3
4
5
6
7
Output Current (A)
8
9
10
G001
Figure 25. Efficiency vs Load Current (8 V to 15 V
to 1.8 V at 10 A, Design Example 1)
100
225.0
100
225.0
80
180.0
80
180.0
60
135.0
60
135.0
40
90.0
40
90.0
20
45.0
20
45.0
0
0.0
0
0.0
−20
−40
−60
100
Gain
Phase
1000
10000
Frequency (Hz)
100000
−45.0
−20
−90.0
−40
−135.0
1000000
Figure 26. Design Example 1 Loop Response
VIN = 12 V, VOUT1 = 1.2 V, IOUT1 = 10 A, 80-kHz
Bandwidth, 50° Phase Margin
Copyright © 2011, Texas Instruments Incorporated
Phase (°)
Gain (dB)
70
60
VIN = 8 V
VIN = 12 V
VIN = 15 V
55
75
−60
100
Phase (°)
75
Gain (dB)
Efficiency (%)
90
−45.0
−90.0
Gain
Phase
1000
10000
Frequency (Hz)
100000
−135.0
1000000
Figure 27. Design Example 1 Loop Response
VIN = 12 V, VOUT2 = 1.8 V, IOUT2 = 10 A, 80-kHz
Bandwidth, 50° Phase Margin
27
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
Figure 28 shows the switching waveform, VIN = 12 V, IOUT1 = IOUT2 = 10 A, Ch.1 = HDRV1, Ch.2 = LDRV1, Ch.3
= VOUT1 ripple. The high-frequency noise is caused by parasitic inductive and capacitive elements interacting
with the high energy, rapidly switching power elements resulting in ringing at the transition points. Capacitive
filtering at the load input will successfully attenuate these noise spikes.
Figure 28. Design Example 1 Switching Waveform
28
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
Table 4. Design Example 1, Dual-Output List of Materials
REFERENCE
DESIGNATOR
QTY
DESCRIPTION
PART NUMBER
MFR
C1
1
Capacitor, Aluminum, 100 µF, 35 V, ±20%, 0.328 x
0.328 inch
EEV-FK1V101GP
Panasonic - ECG
C2, C7, C20, C26,
C39
5
Capacitor, Ceramic, 0.1 µF, 50 V, X7R, ±10%, 0603
Std
Std
C3, C35
2
Capacitor, Ceramic, 0.1 µF, 25 V, X5R, ±10%, 0402
Std
Std
C4, C36
2
Capacitor, Ceramic, 1.0 µF, 25 V, X7R, ±10%, 0603
Std
Std
C5, C6, C37, C38
4
Capacitor, Ceramic, 10 µF, 25 V, X5R, ±10%, 0805
Std
Std
C8, C25
2
Capacitor, Ceramic, 33 nF, 16 V, X7R, ±10%, 0603
Std
Std
C9, C19, C22, C34
4
Capacitor, Ceramic, 470 pF, 25 V, C0G, NP0, ±5%,
0603
Std
Std
C10, C27
2
Capacitor, Ceramic, 1.0 µF, 6.3 V, X5R, ±10%, 0402
Std
Std
C11, C12, C18, C28,
C29
5
Capacitor, Ceramic, 3.3 µF, 10 V, X5R, ±10%, 0603
C1608X5R1A335K
TDK Corporation
C13, C14, C30, C31
4
Capacitor, Ceramic, 10 µF, 6.3 V, X7R, ±10%, 0805
Std
Std
C15, C16, C32, C33
4
Capacitor, Polymer Aluminum, 220 µF, 4 V, ±20%, 5m
ESR
EEF-SE0G221ER
Panasonic - ECG
C17, C23
2
Capacitor, Ceramic, 220 pF, 50 V, C0G, NP0, ±5%,
0603
Std
Std
C21, C24
2
Capacitor, Ceramic, 10 pF, 50 V, C0G, NP0, ±5%, 0603
Std
Std
C40
1
Capacitor, Ceramic, 1.0 nF, 25 V, C0G, NP0, ±5%, 0603
Std
Std
L1, L2
2
Inductor, Power Choke, 1.1 µH, ±20%, 3.15mΩ, 7.0 x
6.9 mm
744314110
Wurth Elektronik
Q1, Q2
2
MOSFET, Synchronous Buck NexFET Power Block,
QFN-8 POWER
CSD86330Q3D
Texas Instruments
R1
1
Resistor, Chip, 68.1 kΩ, 1/10W, ±1%, 0603
Std
Std
R2, R21
2
Resistor, Chip, 86.6 kΩ, 1/10W, ±1%, 0603
Std
Std
R3
1
Resistor, Chip, 12.7 kΩ, 1/10W, ±1%, 0603
Std
Std
R4, R5, R22
3
Resistor, Chip, 1.00 Ω, 1/10W, ±1%, 0603
Std
Std
R6
1
Resistor, Chip, 40.2 kΩ, 1/10W, ±1%, 0603
Std
Std
R7, R24
2
Resistor, Chip, 49.9 Ω, 1/10W, ±1%, 0603
Std
Std
R8, R17
2
Resistor, Chip, 5.11 Ω, 1/8W, ±1%, 0805
Std
Std
R9, R16
2
Resistor, Chip, 0 Ω, 1/10W, ±1%, 0603
Std
Std
R10, R14, R19, R27
4
Resistor, Chip, 20.0 kΩ, 1/10W, ±1%, 0603
Std
Std
R11, R18
2
Resistor, Chip, 82.5 kΩ, 1/10W, ±1%, 0603
Std
Std
R12, R23
2
Resistor, Chip, 1.62 kΩ, 1/10W, ±1%, 0603
Std
Std
R13
1
Resistor, Chip, 3.09 kΩ, 1/10W, ±1%, 0603
Std
Std
R15
1
Resistor, Chip, 29.4 kΩ, 1/10W, ±1%, 0603
Std
Std
R20, R30
2
Resistor, Chip, 5.11 Ω, 1/10W, ±1%, 0603
Std
Std
R25
1
Resistor, Chip, 10.0 kΩ, 1/10W, ±1%, 0603
Std
Std
R26
1
Resistor, Chip, 3.24 kΩ, 1/10W, ±1%, 0603
Std
Std
R28, R29
2
Resistor, Chip, 100 kΩ, 1/10W, ±1%, 0603
Std
Std
1
IC, TPS40322 Dual Synchronous Buck Controller,
QFN-32
TPS40322RHB
Texas Instruments
U1
Copyright © 2011, Texas Instruments Incorporated
29
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
TPS40322 Design Example 2
Two-Phase Single Output Configuration from 12-V nominal to 1.2-V DC-to-DC Converter Using
the TPS40322
The following example shows the schematic, waveforms, and components for a two-phase single output
synchronous buck converter using the TPS40322 controller. The design goal parameters are given in Table 5.
Table 5. TPS40322 Design Example Specification
PARAMETER
TEST CONDITION
MIN
NOM
4.5
MAX
VIN
Input voltage
15
VOUT
Output voltage
IOUT(min) ≤ IOUT ≤ IOUT(max)
Line regulation
VIN(min) ≤ VIN ≤ VIN(max)
0.5%
0.5%
1.2
Load regulation
IOUT(min) ≤ IOUT ≤ IOUT(max)
VRIPPLE
Output ripple
IOUT1 = IOUT1(max)
VOVER
Output overshoot
ΔIOUT1 = 5 A
40
VUNDER
Output undershoot
ΔIOUT1 = 5A
40
IOUT
Output current
VIN(min) ≤ VIN ≤ VIN(max)
tSS
Soft-start time
VIN = 12 V
η
Efficiency
VIN = 12 V, IOUT1= IOUT2 = 10 A
fSW
Switching frequency
30
mV
mV
mV
10
2
V
V
12
0
UNIT
A
ms
88%
500
kHz
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
+
+
+
+
+
+
+
+
+
+
Figure 29 shows the two-phase converter schematic described in design example 2.
Figure 29. Design Example 2, Two-Phase Converter Schematic
Copyright © 2011, Texas Instruments Incorporated
31
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
Design Example 2 Characterization
1.1955
SW2
(10 V/div)
1.1950
Output Voltage (V)
1.1945
1.1940
SW1
(10 V/div)
1.1935
1.1930
1.1925
IL1
(5 A/div)
IL2
(5 A/div)
1.1920
VOUT = 30 A
1.1915
0
Figure 30. Steady-State Switching and Current
Sharing
2
4
6
8
10
Input Voltage (µV)
12
14
16
G001
Figure 31. Line Regulation
1.2030
1.2020
Output Voltage (V)
1.2010
1.2000
1.1990
1.1980
1.1970
1.1960
0
5
10
15
20
Input Current (A)
25
30
G001
Figure 32. Load Regulation
32
Copyright © 2011, Texas Instruments Incorporated
TPS40322
SLUSAF8 – JUNE 2011
www.ti.com
Table 6. TPS40322 Design Example 2, Two-Phase, Single Output Bill of Materials
REFERENCE
DESIGNATOR
QTY
DESCRIPTION
PART NUMBER
MFR
C1, C2, C3, C31,
C32, C33
6
Capacitor, Ceramic, 22 µF, 25V, X5R, ±20%, 1210
Std
Std
C4, C18, C28, C30
4
Capacitor, Ceramic, 1 µF, 50V, X7R, ±10%, 0603
Std
Std
C5, C6, C7, C22, C29
5
Capacitor, Ceramic, 0.1 uF, 50V, X7R, ±10%, 0603
Std
Std
C8, C21
2
Capacitor, Ceramic, 6.8 nF, 50V, X7R, ±10%, 0805
Std
Std
C9
1
Capacitor, Ceramic, 2.2 nF, 16V, X7R, ±10%, 0603
Std
Std
C10, C11, C12, C13,
C23, C24, C25, C26
8
Capacitor, Polymer Aluminum, 220 µF, 4V, ±20%,
5m ESR
EEFSE0G221R
Panasonic - ECG
C14, C27
2
Capacitor, Ceramic, 22 µF, 6.3 V, X5R, ±10%, 0805
Std
Std
C15
1
Capacitor, Ceramic, 8.2 nF, 16 V, X7R, ±10%, 0603
Std
Std
C16
1
Capacitor, Ceramic, 330 pF, 16 V, X7R, ±10%, 0603
Std
Std
C17
1
Capacitor, Ceramic, 22 nF, 50 V, X7R, ±10%, 0603
Std
Std
C19, C20
2
Capacitor, Ceramic, 4.7 µF, 16 V, X7R, ±10%, 0805
Std
Std
C38, C39
2
Capacitor, Aluminum, 100 µF, 25 V, ±20%, F8
ECE-V1EA101XP
Panasonic - ECG
L1, L2
2
Inductor, SMT, 0.47 µH, ±20%, 1.2 mΩ, 0.512 x
0.571"
IHLP5050FDERR47M01 Vishay/Dale
Q1, Q4
2
MOSFET, N-channel, 30 V, 30 A, 8mΩ, 5-LFPAK
RJK0305
Renesas Electronics
Q2, Q3
2
MOSFET, N-channel, 30 V, 60 A, 2.1 mΩ, 5-LFPAK
RJK0328
Renesas Electronics
R1
1
Resistor, Chip, 42 kΩ, 1/10W, ±1%, 0603
Std
Std
R2
1
Resistor, Chip, 100 kΩ, 1/10W, ±1%, 0603
Std
Std
R3, R19
2
Resistor, Chip, 4.7 kΩ, 1/10W, ±1%, 0603
Std
Std
R4
1
Resistor, Chip, 38.5 kΩ, 1/10W, ±1%, 0603
Std
Std
R5
1
Resistor, Chip, 49.9 Ω, 1/10W, ±1%, 0603
Std
Std
R6, R8, R16
3
Resistor, Chip, 10 kΩ, 1/10W, ±1%, 0603
Std
Std
R7, R27, R28, R29,
R30
5
Resistor, Chip, 0 Ω, 1/10W, ±1%, 0603
Std
Std
R9
1
Resistor, Chip, 511 Ω, 1/10W, ±1%
Std
Std
R10, R17
1
Resistor, Chip, 1.00 Ω, 1/8W, ±1%, 0805
Std
Std
R11, R18
2
Resistor, Chip, 5.11 Ω, 1/10W, ±1% 0603
603
Std
R12, R13
2
Resistor, Chip, 51 Ω, 1/10W, ±1%, 0603
Std
Std
R14
1
Resistor, Chip, 3.32 kΩ, 1/10W, ±1%, 0603
Std
Std
R15
1
Resistor, Chip, 40 kΩ, 1/10W, ±1%, 0603
Std
Std
R26, R31
2
Resistor, Chip, 2 Ω, 1/10W, ±1%, 0603
Std
Std
R20, R21, R22, R23,
R24, R25,
0
not used
Std
Std
U1
1
Dual synchronous buck controller, QFN-32
TPS40322RHB
Texas Instruments
Copyright © 2011, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS40322RHBR
ACTIVE
QFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS40322RHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS40322RHBR
QFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
TPS40322RHBT
QFN
RHB
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS40322RHBR
QFN
RHB
32
3000
346.0
346.0
29.0
TPS40322RHBT
QFN
RHB
32
250
190.5
212.7
31.8
Pack Materials-Page 2
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