May 1997 ML4825* High Frequency Power Supply Controller GENERAL DESCRIPTION FEATURES The ML4825 High Frequency PWM Controller is an IC controller optimized for use in Switch Mode Power Supply designs running at frequencies to 1MHz. Propagation delays are minimal through the comparators and logic for reliable high frequency operation while slew rate and bandwidth are maximized on the error amplifier. This controller is designed to work in either voltage or current mode and provides for input voltage feed forward. ■ ■ ■ ■ ■ ■ ■ A 1V threshold current limit comparator provides cycleby-cycle current limit while exceeding a 1.4V threshold initiates a soft-start cycle. The soft start pin doubles as a maximum duty cycle clamp. An under-voltage lockout circuit with 800mV of hysteresis assures low startup current and drives the outputs low. ■ ■ ■ ■ This controller is similar in architecture and performance to the UC1825 controller, however the ML4825 includes many features not found on the 1825. These features are set in Italics. ■ ■ Practical operation at switching frequencies to 1.0MHz High current (2A peak) dual totem pole outputs Wide bandwidth error amplifier Fully latched logic with double pulse suppression Pulse-by-pulse current limiting Soft start and maximum duty cycle control Under voltage lockout with hysteresis Precision trimmed 5.1V bandgap reference Pin compatible improved replacement for UC1825 Fast shut down path from current limit to outputs Outputs preset to known condition after under voltage lockout Soft start latch ensures full soft start cycle Outputs pull low for undervotage lockout BLOCK DIAGRAM (Pin configuration shown for 16-pin version) 5 6 7 3 2 1 *Some Packages Are Obsolete or End Of Life RT CLOCK OUT OSC CT 1.25V + RAMP E/A OUT NI INV R + COMP S – + Q PWR VC ERROR AMP OUT A C V+ – Q Q POWER VC PWR GND + – 1V ILIM/SD – Q 12 4V 1.5V VREF 16 9V + – 14 VREF GEN + R 1.4V 11 – 1V ENABLE VREF 9 OUT B SS + 13 POWER GND TF.F. P 9µA 8 4 – S UNDER VOLTAGE LOCKOUT + INTERNAL BIAS VCC SIGNAL GND 15 10 1 ML4825 PIN CONFIGURATION 5.1V REF NI 2 15 VCC E/A OUT 3 14 OUT B VCC 16 5.1V REF 1 NC INV INV ML4825 20-Pin PLCC NI ML4825 16-Pin PDIP 16-Pin SOIC 3 2 1 20 19 E/A OUT 4 18 OUT B CLOCK 5 17 VC NC 6 16 NC RT 5 12 PWR GND RT 7 15 PWR GND CT 6 11 OUT A CT 8 14 OUT A 7 10 GND SS 8 9 ILIM/SD TOP VIEW 10 11 12 13 NC RAMP 9 GND VC ILIM/SD 13 SS 4 RAMP CLOCK TOP VIEW PIN DESCRIPTION (Pin number in parentheses is for PLCC version) PIN 1 (2) NAME FUNCTION INV Inverting input to error amp. 2 (3) NI Non-inverting input to error amp. 3 (4) E/A OUT Output of error amplifier and input to main comparator 4 (5) CLOCK Oscillator output 5 (7) RT Timing resistor for oscillator— sets charging current for oscillator timing capacitor (pin 6) 6 (8) CT Timing capacitor for oscillator 7 (9) RAMP Non-inverting input to main comparator. Connected to CT for voltage mode operation or to current sense resistor for current mode 8 (10) SS 2 Normally connected to soft start capacitor PIN NAME FUNCTION 9 (12) ILIM/SD Current limit sense pin. Normally connected to current sense resistor. 10 (13) GND Analog signal ground 11 (14) OUT A High current totem pole output. This output is the first one energized after power on reset 12 (15) PWR GND Return for the high current totem pole outputs 13 (17) VC Positive supply for the high current totem pole output 14 (18) OUT B High current totem pole output 15 (19) VCC Positive supply for the IC 16 (20) 5.1V REF Buffered output for the 5.1V voltage reference ML4825 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage (VC, VCC) ........................................... 30V Output Current, Source or Sink (OUT A, OUT B) DC ....................................................................... 0.5A Pulse (0.5µs) ......................................................... 2.0A Analog Inputs (INV, NI, RAMP) ................................ GND –0.3V to 7V (SS, ILIM) ........................................... GND –0.3V to 6V CLOCK Output Current ........................................... –5mA E/A OUT Output Current .......................................... 5mA Soft Start Sink Current ............................................ 20mA RT Charging Current ................................................ –5mA Junction Temperature ML4825IX, ML4825CX ....................................... 150°C Storage Temperature Range ..................... –65°C to 150°C Lead Temperature (soldering 10 sec.) ..................... 260°C Thermal Resistance (θJA) Plastic DIP or SOIC ......................................... 65°C/W Plastic Chip Carrier (PCC) ................................ 60°C/W OPERATING CONDITIONS Temperature Range ML4825CX ................................................ 0°C to 70°C ML4825IX .............................................. –40°C to 85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, RT = 3.65kΩ, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V (Note 1). PARAMETER CONDITIONS MIN TYP MAX UNITS 360 400 440 kHz –2 0.2 2 % 5 % 460 kHz OSCILLATOR Initial Accuracy TJ = 25°C Voltage Stability 10V < VCC < 30V, TA = 25°C Temperature Stability Total Variation Line, temperature 340 Clock Out High 3.9 Clock Out Low 4.5 V 2.3 2.9 V Ramp Peak 2.6 2.8 3.0 V Ramp Valley 0.7 1.0 1.25 V Ramp Valley to Peak 1.6 1.8 2.0 V C suffix 5.00 5.10 5.20 V I suffix 5.00 5.10 5.20 V REFERENCE Output Voltage TJ = 25°C, IO = 1mA Line Regulation 10V < VCC < 30V –20 2 20 mV Load Regulation 1mA < IO < 10mA –20 5 20 mV Temperature Stability –55°C < TJ < 150°C 0.2 0.4 % Total Variation Line, load, temperature C suffix 4.95 5.25 V I suffix 4.95 5.25 V µV Output Noise Voltage 10Hz to 10kHz 50 Long Term Stability TJ = 125°C, 1000 hours 5 25 mV Short Circuit Current VREF = 0V –15 –50 –100 mA C suffix –15 15 mV I suffix –15 15 mV ERROR AMPLIFIER Input Offset Voltage Input Bias Current 0.6 3 µA Input Offset Current 0.1 1 µA Open Loop Gain 1 < VO < 4V 60 96 dB 3 ML4825 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP 75 95 MAX UNITS ERROR AMPLIFIER (Continued) CMRR 1.5V < VCM < 5.5V C suffix dB I suffix 75 95 dB PSRR 10V < VCC < 30V C suffix 80 110 dB I suffix 80 110 dB Output Sink Current VEA OUT A = 1.0V 1 2.5 mA Output Source Current VEA OUT A = 4.0V –0.5 –1.3 mA Output High Voltage IEA OUT A = –0.5mA 4.0 4.7 5.0 Output Low Voltage IEA OUT A = 1mA 1.0 V 0 0.5 Unity Gain Bandwidth 3 5.5 MHz V Slew Rate 6 12 V/µs PWM COMPARATOR Ramp Bias Current VRAMP = 0V, TA > 0°C C suffix –1 E/A OUT Zero DC Threshold µA –5 µA C suffix 85 100 % I suffix 80 100 % 1.25 1.7 V 50 80 nS –9 –20 µA I suffix Duty Cycle Range –5 VRAMP = 0V 1.1 Delay to Output SOFT START Charge Current SS = 0.5V –3 Discharge Current SS = 1V 1 mA CURRENT LIMIT/SHUTDOWN ILIM Bias Current 0V < VI(LIM) < 0.5V C suffix –10 10 µA I suffix –10 10 µA Current Limit Threshold Shutdown Threshold 0.9 1 1.1 V TA > 0°C 1.25 1.4 1.55 V TA < 0°C 1.25 1.4 1.60 V 40 70 ns IOUT = 20mA 0.25 0.4 V IOUT = 200mA 1.2 2.2 V Delay to Output OUTPUT Output Low Level Output High Level IOUT = –20mA 13.0 13.5 V IOUT = –200mA 12.0 13.0 V Collector Leakage VC = 30V 100 500 µA Rise/Fall Time CL = 1000pF 30 60 ns UNDERVOLTAGE LOCKOUT Start Threshold 8.8 9.2 9.6 V UVLO Hysteresis 0.3 0.8 1.2 V C suffix 0.1 1.1 2.5 mA I suffix 0.1 3.5 mA 33 mA SUPPLY Start Up Current ICC Note 1: 4 VCC = 8V VINV, VRAMP, VI(LIM)/SD = 0V, VNI = 1V, TA = 25°C Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 10 26 ML4825 100k FUNCTIONAL DESCRIPTION 100nF 47nF OSCILLATOR 22nF RT (Ω) The ML4825 oscillator charges the external capacitor (CT) with a current (ISET) equal to 3/RSET. When the capacitor voltage reaches the upper threshold (Ramp Peak), the comparator changes state and the capacitor discharges to the lower threshold (Ramp Valley) through Q1. While the capacitor is discharging, Q2 provides a high pulse. 0nF 10k 4.7nF 2.2nF The oscillator period can be described by the following relationship: 1nF 470pF 1k 100 tOSC = tRAMP + tDEADTIME 1k 1M 100k 10k FREQUENCY (Hz) where: tRAMP = Figure 2. Oscillator Timing Resistance vs Frequency C (Ramp Valley to Peak) ISET and: tDEADTIME = C (Ramp Valley to Peak) IQ1 160 1.0nF 140 ISET RT ISET 3V 6 CT TD (ns) 5.1V 5 + IQ1 120 100 – 470pF 4 Q1 80 10k 100k 1M FREQUENCY (Hz) Figure 3. Oscillator Deadtime vs Frequency CLOCK tD RAMP PEAK 4.70 CT RAMP VALLEY 2.20 TD (µs) Figure 1. Oscillator Block Diagram 1.00 0.47 0.22 0.10 0.047 0.47 1.0 2.2 4.7 10.0 22 47 100 CT (nF) Figure 4. Oscillator Deadtime vs CT (3kΩ ≤ RT ≤ 100kΩ) 5 ML4825 ERROR AMPLIFIER SOFT START AND CURRENT LIMIT The ML4825 error amplifier is a 5.5MHz bandwidth 12V/µs slew rate op-amp with provision for limiting the positive output voltage swing (Output Inhibit line) for ease in implementing the soft start function. The ML4825 employs two current limits. When the voltage at ILIM/SD exceeds 1V, the outputs are immediately shut off and the cycle is terminated for the remainder of the oscillator period by resetting the RS flip flop. OUTPUT DRIVER STAGE The ML4825 Output Driver is a 2A peak output high speed totem pole circuit designed to quickly switch the gates of capacitive loads, such as power MOSFET transistors. If the output current is rising quickly such that the voltage on ILIM/SD reaches 1.4V before the outputs have turned off, a soft start cycle is initiated. The soft start capacitor is discharged and outputs are held “off” until the voltage at SS reaches 1V, ensuring a complete soft start cycle. The duty cycle on start up is limited by limiting the output voltage of the error amplifier voltage to the voltage at SS. 5 100 80 4 60 AV AV (dB) (V) VIN 3 VOUT 40 20 0 0 2 0 0 –90 –20 1 0 0.2 0.4 0.6 1.0 0.8 100 1k TIME (µs) 10k 100k 1M 10M –180 100M FREQUENCY (Hz) Figure 5. Unity Gain Slew Rate Figure 6. Open Loop Frequency Response VCC 3 POWER VC 13 Q2 2 OUT B 11 14 SOURCE VSAT (V) OUT A 1 Q1 POWER GND SINK 12 0 0 0.5 1.0 IOUT (A) Figure 7. Simplified Schematic 6 Figure 8. Saturation Curves 1.5 15 0.2 IL (A) 2 IL (A) 0 0 –0.2 10 5 VOUT (V) VOUT (V) ML4825 15 –2 10 5 0 0 0 40 80 160 120 200 TIME (ns) 0 100 200 300 400 500 TIME (ns) Figure 9. Rise/Fall Time (CL = 1000pF) Figure 10. Rise/Fall Time (CL = 10,000pF) 40 ICC — SUPPLY CURRENT 35 30 25 20 15 10 5 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 11. Supply Current vs. Temperature 7 ML4825 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 1 0.02 MIN (0.50 MIN) (4 PLACES) 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) 11 ML4825 PHYSICAL DIMENSIONS inches (millimeters) (Continued) Package: Q20 20-Pin PLCC 0.385 - 0.395 (8.89 - 10.03) 0.042 - 0.056 (1.07 - 1.42) 0.350 - 0.356 (8.89 - 9.04) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 0.042 - 0.048 (1.07 - 1.22) 6 PIN 1 ID 16 0.350 - 0.356 (8.89 - 9.04) 0.385 - 0.395 (8.89 - 10.03) 0.200 BSC (5.08 BSC) 0.290 - 0.330 (7.36 - 8.38) 11 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.165 - 0.180 (4.19 - 4.57) 0.026 - 0.032 (0.66 - 0.81) 0.146 - 0.156 (3.71 - 3.96) 0.100 - 0.110 (2.54 - 2.79) 0.013 - 0.021 (0.33 - 0.53) SEATING PLANE ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE ML4825CP ML4825CS ML4825CQ 0°C to 70°C 0°C to 70°C 0°C to 70°C ML4825IP ML4825IS ML4825IQ –40°C to 85°C –40°C to 85°C –40°C to 85°C PACKAGE 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) 20-Pin PLCC (Q20) (End Of Life) 16-Pin PDIP (P16) (End Of Life) 16-Pin Wide SOIC (S16W) (End Of Life) 20-Pin PLCC (Q20) (Obsolete) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 9 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4825-01