July 1999 ML4903 High Current Synchronous Buck Controller GENERAL DESCRIPTION FEATURES The ML4903 high current synchronous buck controller provides high efficiency DC/DC conversion to generate VCCP for processors such as the Pentium® Pro and Pentium II from Intel®. ■ Designed to meet Pentium Pro and Pentium II VRM power supply requirements ■ DC regulation to +1% maximum The ML4903 controller, when combined with two external MOSFETs, generates output voltages between 1.8V and 3.5V from a 12V supply. The output voltage is selected via an internal 2 chord 4-bit DAC. In the upper range, the output can be set between 2.1V and 3.5V in 100mV steps. In the lower range, the output can be set between 1.8V and 2.05V in 50mV steps. Output currents in excess of 20A can be attained at efficiencies greater than 80%. ■ Proprietary circuitry provides transient response of ±5% maximum over a 0A to 14A load range ■ Programmable output voltage (1.8V to 3.5V) is set by an onboard 2 chord 4-bit DAC ■ Synchronous buck topology for maximum power conversion efficiency The ML4903 can be enabled/disabled via the SHDN pin. While disabled, the output of the regulator is completely isolated from the circuit’s input supply. The ML4903 employs fixed-frequency PWM control combined with a sophisticated control loop enhancement circuit to provide excellent load transient response. ■ Fixed frequency operation for easier system integration ■ Integrated anti-shootthrough logic, short circuit protection, shutdown, and UV lockout BLOCK DIAGRAM 19 VDD + 10.5V 18 – P DRV UVLO VCC 17 + 4.4V – CONTROL LOGIC 5V N DRV 16 30µA PROTECT 3.5V 20 + + – – PWR GND 15 COMP SHDN 13 200kHz 6 D0 VFB – 1 D1 + VDAC D2 + -107mV I SENSE 11 2 – 3 D3 4 8 RANGE 5 12 PWR GOOD 2 CHORD 4 BIT DAC VDAC VDAC + 3% VFB VDAC - 3% + VDAC + 10% VDAC + 3% – VFB + VDAC - 10% – + – + – 3.5V REFERENCE VDAC - 3% VREF 9 GND 10 1 ML4903 PIN CONFIGURATION ML4903 20-Pin TSSOP (T20) D0 1 20 PROTECT D1 2 19 VDD D2 3 18 VCC D3 4 17 P DRV RANGE 5 16 N DRV SHDN 6 15 PWR GND NC 7 14 NC PWR GOOD 8 13 COMP VREF 9 12 ISENSE GND 10 11 VFB TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 D0 LSB input to the DAC which sets the output voltage 9 V REF Bypass connection for the internal 3.5V reference 2 D1 Input to the DAC which sets the output voltage 10 GND Analog signal ground 3 11 Input to the DAC which sets the output voltage V FB Output voltage feedback pin D2 12 I SENSE Current sense input 4 D3 MSB input to the DAC which sets the output voltage 13 COMP Connection for the compensation and optional soft-start delay network 5 RANGE Range selection bit for the 2 chord 4bit DAC. Logic 1 sets the range at 2.1V to 3.5V with an LSB of 100mV. Logic 0 sets the range at 1.8V to 2.05V with an LSB of 50mV. 15 PWR GND Power ground 16 N DRV Synchronous rectifier driver output 17 P DRV Buck switch driver output Grounding this pin shuts down the regulator 18 VCC Connection point for monitoring the 5V supply to determine the proper condition of PWR GOOD 19 V DD 12V power supply input 20 PROTECT Connection for the integrating current limit network 6 SHDN 8 PWR GOOD This open drain output goes low whenever SHDN goes low or when the output is not within +10% of its nominal value 2 ML4903 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. V DD ........................................................................................... 13.5V VCC .................................................................................................. 7V Peak Driver Output Current ....................................... ±2A VFB Voltage ...................................... GND - 0.3V to 5.5V ISENSE Voltage .................................. GND - 0.5V to 5.5V All Other Inputs .................... GND - 0.3V to VDD + 0.3V SHDN Input Current .............................................. 100mA Junction Temperature .............................................. 150°C Storage Temperature Range ..................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................... 260°C Thermal Resistance (qJA) .................................... 100°C/W OPERATING CONDITIONS Temperature Range ....................................... 0°C to 70°C VDD Range .............................................. 11.4V to 12.6V VCC Range ............................................... 4.75V to 5.25V ELECTRICAL CHARACTERISTICS Unless otherwise specified, VDD = 12V, VCC = SHDN = 5V, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 3.51 3.535 3.56 V REFERENCE VREF Output Voltage Line Regulation 11V < VDD < 13V 0.5 mV/V UV LOCKOUT VDD Start-up Threshold 10.0 10.5 10.8 V VDD Hysteresis 300 450 600 mV VCC Start-up Threshold 4.25 4.4 4.6 V VCC Hysteresis 300 400 500 mV 0.8 V SHUTDOWN Input Low Voltage Input High Voltage 2.0 Delay to Output V 50 ns POWER GOOD COMPARATOR Output Voltage in Regulation 5kW pull-up to 5V Output Voltage out of Regulation VFB < 90% VDAC or >110% VDAC 0.4 V Output Voltage in Shutdown SHDN = 0V, 5kW pull-up to 5V 0.4 V 230 kHz 98 % 0 % 0.8 V 4.8 V BUCK REGULATOR Oscillator Frequency Duty Cycle Ratio 160 RANGE = 1, VFB = 0V, DAC (D3-D0) Code = 0100 80 RANGE = 1, VFB > 3.193V, DAC (D3-D0) Code = 0100 DAC (RANGE, D3-D0) Input Low Voltage DAC (RANGE, D3-D0) Input High Voltage 2.0 200 V 3 ML4903 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Continued) CONDITIONS MIN TYP MAX UNITS RANGE = 0, (D3-D0) Code = 0000 2.050 2.071 2.092 V RANGE = 0, (D3-D0) Code = 0001 2.000 2.020 2.04 V RANGE = 0, (D3-D0) Code = 0010 1.950 1.970 1.989 V RANGE = 0, (D3-D0) Code = 0011 1.900 1.919 1.938 V RANGE = 0, (D3-D0) Code = 0100 1.850 1.869 1.887 V RANGE = 0, (D3-D0) Code = 0101 1.800 1.818 1.836 V RANGE = 1, (D3-D0) Code = 0000 3.500 3.535 3.570 V RANGE = 1, (D3-D0) Code = 0001 3.400 3.434 3.468 V RANGE = 1, (D3-D0) Code = 0010 3.300 3.333 3.366 V RANGE = 1, (D3-D0) Code = 0011 3.200 3.232 3.264 V RANGE = 1, (D3-D0) Code = 0100 3.100 3.131 3.162 V RANGE = 1, (D3-D0) Code = 0101 3.000 3.030 3.060 V RANGE = 1, (D3-D0) Code = 0110 2.900 2.929 2.958 V RANGE = 1, (D3-D0) Code = 0111 2.800 2.828 2.856 V RANGE = 1, (D3-D0) Code = 1000 2.700 2.727 2.754 V RANGE = 1, (D3-D0) Code = 1001 2.600 2.626 2.652 V RANGE = 1, (D3-D0) Code = 1010 2.500 2.525 2.550 V RANGE = 1, (D3-D0) Code = 1011 2.400 2.424 2.448 V RANGE = 1, (D3-D0) Code = 1100 2.300 2.323 2.346 V RANGE = 1, (D3-D0) Code = 1101 2.200 2.222 2.244 V RANGE = 1, (D3-D0) Code = 1110 2.100 2.121 2.142 V -117 mV BUCK REGULATOR (Continued) VFB Threshold Voltage (Note 2) ISENSE Threshold Voltage -80 ISENSE Hysteresis 10 mV PROTECT Threshold Voltage 3.2 3.5 3.8 V PROTECT Hysteresis 1.8 2 2.2 V PROTECT Charging Current V(ISENSE) = -120mV PROTECT Leakage Current 30 µA +100 nA ns Transition Time, P DRV and N DRV CL = 5000pF, 10-90% 40 VDD Current SHDN = 0V DAC (D3-D0) Code = 0000 650 900 µA SHDN = 5V, VFB = 5V 1 2 mA SHDN = 5V, VFB = 0V, CL = 5000pF 20 SUPPLY IDD I CC VCC Current Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2: Codes 00110 to 01111, and 11111 are not valid; applying these codes to the DAC will shut off P DRV and N DRV. 4 1 mA 10 µA ML4903 FUNCTIONAL DESCRIPTION The ML4903 PWM controller permits the construction of a simple yet sophisticated power supply for Intel’s Pentium Pro and Pentium II microprocessor families. The ML4903 and its associated circuitry can be built either as a Voltage Regulator Module (VRM) or as a dedicated supply on the motherboard. The ML4903 controls a P-channel MOSFET and an N-channel MOSFET in a synchronous buck regulator topology to convert a 5V input to the voltage required by the microprocessor. The output voltage can be set between 1.8V and 3.5V, as selected by an onboard DAC. Other features which facilitate the design of DC-DC converters for any type of processor include a trimmed 1% reference, special transientresponse optimization in the feedback paths, a shutdown input, input and output power good monitors, and overcurrent protection. POWER GOOD (PWR GOOD) OUTPUT VOLTAGE SELECTION INTERNAL REFERENCE The inputs of the internal 2-chord 4-bit DAC come from open collector signals provided by the processor. These signals specify what supply voltage the microprocessor requires. The output voltage of the buck converter is compared directly with the DAC voltage to maintain regulation. D3 is the MSB input and D0 is the LSB input of the DAC, while RANGE selects the output voltage range and the LSB voltage increment of the DAC. The output of the DAC is between 2.121V to 3.535V in 100mV steps when RANGE = 1, and between 1.818V to 2.071V in 50mV steps when RANGE = 0. The output voltage set by the DAC is 1% above the processor’s nominal operating voltage to counteract the effects of connector and PC trace resistance, and of the instantaneous output voltage droop which occurs when a transient load is applied. For codes 00110 to 01111 and code 11111, the P DRV and N DRV outputs are disabled. The ML4903 contains a 3.535V, temperature compensated, precision band-gap reference. The VREF pin is connected to the output of this reference, and should be bypassed with a 100nF to 220nF ceramic capacitor for proper operation. VOLTAGE FEEDBACK LOOP The ML4903 contains two control loops to improve the load transient response. The output voltage is directly monitored via the VFB pin and compared to the desired output voltage set by the internal DAC. When the output voltage is within +3% of the DAC voltage, the proportional control loop (closed by the voltage error amplifier) keeps the output voltage at the correct value. If the output falls below the DAC voltage by more than 3%, one side of the transient loop is activated, forcing the output of the ML4903 to maximum duty cycle until the output comes back within the +3% limit. If the output voltage rises above the DAC voltage by more than 3%, the other side of the transient loop is activated, and the Pchannel MOSFET drive is disabled until the output comes back within the +3% limit. If the output voltage rises above the DAC voltage by more than 10%, both P DRV and N DRV will be disabled to turn the converter off. During start-up, the transient loop is disabled until the output voltage is within -3% of the DAC voltage. An open drain signal is provided by the ML4903 which tells the microprocessor when the entire power system is functioning within the expected limits. PWR GOOD will be false (low) if either the 5V or 12V supply is not in regulation, when the SHDN pin is pulled low, or when the output is not within +10% of the nominal output voltage selected by the internal DAC. When PWR GOOD is false, the PWR GOOD voltage window is held to +3%; when PWR GOOD is true (high), the window is expanded to +10%. Using different windows for coming into and going out of regulation makes sure that PWR GOOD does not oscillate during the start-up of the microprocessor. OVERCURRENT PROTECTION Overcurrent sensing for the ML4903 application circuit is typically accomplished by monitoring the voltage drop across the synchronous rectifier MOSFETs (Q3||Q4) during their conduction period. Alternately, current can be sensed using a low-value, low-inductance sense resistor connected between the most negative end of the current recirculating element and ground. In either case, the resulting IR drop is presented to the ML4903’s internal overcurrent comparator via the part’s ISENSE pin. The overcurrent comparator has approximately 250ns of leading-edge blanking. This blanking interval allows the ML4903 to ignore spurious circuit voltages such as inductive transients and the synchronous rectifier’s drainbody diode voltage during the anti-shootthrough interval. Following this blanking interval, the comparator will turn on if the voltage on the ISENSE pin is more negative than –80mV. Each time the overcurrent comparator turns on, the PROTECT pin of the ML4903 sources a small current (30µA) into an external RC network. If this current source is activated over a number of cycles, the voltage on the PROTECT pin will charge above 3.5V, signaling a sustained overcurrent or short circuit at the load. This will cause the P DRV output to turn off. P DRV will remain off until the capacitor attached to the PROTECT pin has discharged down to 1.5V, at which time the converter is re-enabled. If the fault causing the overcurrent condition has not been cleared, the overcurrent protection cycle will repeat, and the ML4903 circuit will operate in a “hiccup” mode to protect itself, the input supply, and the output. 5 ML4903 FUNCTIONAL DESCRIPTION (Continued) UNDERVOLTAGE LOCKOUT COMPENSATION The ML4903 has hysteretic undervoltage lockout protection circuits for both the 12V (VDD) and 5V (VCC) supplies. During an input undervoltage condition, the internal reference and voltage monitor circuits remain in operation, but P DRV and N DRV are disabled and the PWR GOOD output will be false (low). The COMP pin is connected to the output of the transconductance amplifier which forms the gain block for the proportional control loop of the ML4903. An RC network from this pin to GND is used to compensate the amplifier. R6 10Ω 12VIN C10 220nF 16V C20 22µF 25V C12 220nF 16V L1 1µH R3 1MΩ R2 1kΩ C1 5VIN 1 VID0 2 VID1 3 VID2 4 VID3 5 VID4 6 OUTEN 7 8 PWRGD 9 C22 1nF 10 C14 220nF 16V D0 PROTECT D1 VDD D2 VCC D3 P DRV RANGE N DRV SHDN PWR GND N/C N/C PWR GOOD COMP VREF ISENSE GND VFB U1 ML4903 20 C3 19 18 17 16 Q1, Q2 2X IRF7416 15 14 Q3, Q4 2X IRF7413 L2 5.6µH VCCP R1 33Ω 13 C4-C9 12 R5 100Ω 11 VSS R4 470kΩ C13 1nF Figure 1. Typical VRM Circuit 6 C2 C11 220nF 16V C1 - C3 - 820µF, 16V, Sanyo 16MV820GX C4 - C9 - 1500µF, 6.3V, Sanyo 6MV1500GX ML4903 DESIGN CONSIDERATIONS This section is a quick-check guide for getting ML4903 circuits up and running, with a special emphasis on Pentium Pro and Pentium II applications. Unless otherwise noted, all component designators refer to the circuit shown in Figure 1. COMPENSATION The R and C values connected to the COMP pin for loop compensation are 100kW and 1nF, respectively. These values yield stable operation and rapid transient response for a most values of L2 and COUT (1µH to 10µH, 1200µF to 10,000µF), and will generally not need to be altered. If changes do need to be made, note that the drive capability of the transconductance error amplifier is typically 20µA, its ZOUT is 5MW, and its unity-gain crossover frequency is approximately 10 MHz. INPUT AND OUTPUT CAPACITORS The input and output capacitors used in conjunction with the ML4903, especially in Pentium Pro and Pentium II applications, must be able to meet several criteria: 1. The input capacitors must be able to handle a relatively high ripple current 2. The output capacitors must have a low Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) 3. The output capacitors must be able to hold up the output during the time that the current through the buck inductor is slewing to meet a transient load step. The circuit’s input bypass capacitance should be able to handle a ripple current equal to 0.5 x ILOAD. If the converter sees load peaks only occasionally, and for less than 30 seconds at a time during those intervals, then the aluminum electrolytic or OS-CON® input capacitors need only be sized to accommodate the average output load. Note that tantalum input capacitors have much less thermal mass than aluminum electrolytics, so this relaxation of ripple current requirements may not apply to them. During a 30A/µs load transient, it is not practical for a buck converter to slew the its current fast enough to regulate the instantaneous output voltage required by this application. During the first few microseconds following such a “load step,” the output capacitance of the converter must act as a passive energy source. In delivering its energy to the load, the output capacitance must not introduce any considerable impedance, or its purpose will be defeated. A total voltage aberration during load transients of ±5% is allowed for the Pentium Pro and Pentium II. The voltage transient due to ESL and ESR is: 1 ! 6 DV = ESR ´ DIOUT + ESL ´ di dt "# $ (1) For example, assume that the output voltage of the ML4903 is set to 2.8V. To allow no more than 3% of DVOUT to be contributed by the ESR (84mV) of the output capacitance, and 2% by its ESL (56mV), the output ESR should not exceed: ESR(MAX) = 84mV = 6mW 14A (2) Similarly, the output ESL should be less than or equal to: ESL(MAX) = 1ms 56mV = 18 . nH 30A (3) Achieving these low values of ESL and ESR is not trivial; doing so typically requires using multiple high-quality capacitors in parallel, often with dedicated power and ground planes to minimize interconnection impedance. The output capacitance should have a value of > 1500µF to hold the output voltage relatively constant (< 50mV of sag) until the current in the buck inductor can catch up with the change in output current. To meet the ESR and ESL requirements, the actual output capacitance will usually be significantly greater than this theoretical minimum. These capacitors can be of all one type, or a combination of aluminum electrolytic, OS-CON®, and tantalum devices. Figures 2(a) and 2(b) show oscilloscope photographs of the transient response of the circuit shown in Figure 1. OVERCURRENT PROTECTION Overcurrent protection for the ML4903 application circuit can be accomplished either by using a low value sense resistor placed between the current recirculating rectifier and ground, or by directly monitoring the voltage drop across a synchronous rectifier MOSFET (Q3||Q4) during its conduction period. Using a current sense resistor has the advantages of accuracy over the entire operating temperature range, and of allowing the use of a Schottky diode in place of a synchronous rectifier if the efficiency loss is acceptable. The disadvantages to using a sense resistor are higher cost and increased power dissipation. Sensing across the synchronous rectifier has the advantages of lower cost and of enhanced protection against overtemperature conditions (the current limit point is linearly reduced as the MOSFET temperature rises). If a current sensing resistor is employed (see Figure 3), the resistor monitors the inductor current during the buck converter’s off period. This is the interval during which current will recirculate through the synchronous rectifier, or the Schottky diode if no synchronous rectifier is used. 7 ML4903 Figure 2(a). Output Transient Response of Figure 1 Circuit, IOUT from 0A to 14A (Reference 1 = VOUT, Channel 2 = IOUT). Figure 2(b). Output Transient Response of Figure 1 Circuit, IOUT from 14A to 0A (Reference 2 = VOUT, Channel 2 = IOUT). 12VIN L1 1µH PROTECT VDD VCC P DRV N DRV PWR GND N/C COMP ISENSE VFB 20 19 INPUT CAPACITORS 18 17 16 Q1, Q2 2X IRF7416 L2 5.6µH VCCP 15 14 Q3, Q4 2X IRF7413 13 12 11 RSENSE 6mΩ 1W OUTPUT CAPACITORS VSS U1 ML4903 Figure 3. Connecting a Sense Resistor to the ML4903 8 ML4903 DESIGN CONSIDERATIONS (Continued) Given a –80mV trip point for the overcurrent comparator, the value required for the sense resistor can be found by: R SENSE = |-107mV| (125 . IOUT( MAX ) ) (4) The power handling requirement for RSENSE is given by: PD = IOUT( MAX) 2 ´ V 1 - ´ R ! V OUT SENSE IN "# #$ (5) HIGHER CURRENT LEVELS For example, for a 14A output, RSENSE should be: R SENSE = |−80mV| = 4.57mΩ ≅ 5.0mΩ 125 . × 14A The power dissapated in RSENSE for a 12.0V input remains at approximately 1W for all output voltages from 1.80V to 3.50V. RSENSE must be a low inductance part, such as Dale/ Vishay’s type WSL-2512 series (WSL–2512–.005±1%). Using a PCB trace as a current sense element is not recommended due to the high temperature coefficient of copper, and due to etching and plating tolerances which can occur from board to board. If a current sense resistor is not employed for overcurrent protection, the voltage drop across (Q3||Q4)’s channel during its conducting interval (the synchronous rectification interval) is used to monitor the inductor current. Ignoring the AC component of the current in the buck inductor, the voltage across (Q3||Q4) will be: VSENSE = I1 Q 3||Q 46 R DS0 ON51 Q3||Q 46 (6) RDS(ON) is typically specified at a MOSFET junction temperature (Tj) of 25ºC, but its value at other junction temperatures can either be found graphically in the MOSFET data sheet, or can be estimated by: 0 5 RDS( ON)( T 2) = RDS( ON)( 25ºC) 1007 . T2 - 25º C (7) With a threshold of -80mV for the ISENSE comparator, the current limit threshold is then: ILIMIT = hiccup mode are 1MW and 220nF, respectively. These values will protect the external power components and the power source from overheating during an overcurrent condition. If it is necessary to change the ratio of on and off times during overcurrent conditions, this can be done by selecting a different value for C12. Larger values of C12 will increase the delay between retry attempts (the length of the “hiccup”), and smaller values will reduce the delay. -107mV RDS( ON)( T 2) (8) For Pentium Pro and Pentium II applications, the continuous current may be as high as 14A, so the current limit threshold should be set for a minimum value of 16A at the (Q3||Q4)’s highest anticipated TJ. If necessary, the voltage across the channel of (Q3||Q4) may be divided using two moderately-valued resistors and presented after that division to the ML4903. The R and C values connected to the PROTECT pin for setting the current limit delay and the off-time of the Next generation processor chips will require currents of up to 20A. Additionally, it is often desirable in larger systems to distribute all power at one elevated voltage, such as 12V, regulating it down to other voltages as needed at the points of use. These applications are readily met by the ML4903. For instance, the circuit shown in Figure 1 will deliver an output current of 20A with only three changes: • As IOUT increases, the ripple current through the input capacitor bank will also increase. Add at least one 820µF, 16V input capacitor in parallel with the three shown (C1 - C3). • Synchronous rectifier transistors Q3 and Q4 will see a significantly greater RMS drain current at 20A output than at 14A. Therefore, the use of lower RDS(ON) parts such as Siliconix’ Si4420DY is required. • The value of R1 may require adjustment, depending upon factors such as the specific MOSFET type chosen for Q3 and Q4, and the required operating ambient temperature. In dealing with circuits handling greater than 50W, it is always important to pay attention to thermal issues. When the circuit of Figure 1 is modified for >20A applicatons, a key consideration is that it be provided with adequate heatsinking. Ideally, the system should provide 100 linear feet per minute (LFM) of airflow as specified in Intel’s standards relating to VRMs. Micro Linear does not recommend using the sense resistor method of overcurrent protection at high output current levels, as this does not provide the inherent thermal foldback of IOUT(MAX) which is obtained by directly sensing the VDS(ON) of the rectifier MOSFETs. LAYOUT ISSUES The two pins of the ML4903 which actually sense the current limit voltage are ISENSE and GND. To facilitate the required low-level sensing of the voltage between these pins, there is no connection inside the ML4903 between GND and PWR GND. Because of this, there must be an external connection between the ML4903 GND and PWR GND pins. PWR GND must have a low impedance connection to the ground plane used on the board, as high instantaneous currents will flow in PWR GND when N 9 ML4903 DESIGN CONSIDERATIONS (Continued) DRV and P DRV switch the capacitive loads of the output MOSFET gates. At the same time, GND must not see the resulting switching spikes. If a current sensing resistor is used, the voltage across the resistor must be Kelvin-sensed. This ensures that the ML4903 monitors only the voltage across the resistor, and ignores the voltage drops and inductive transients in the PCB traces which carry current into and out of this resistor. The two pins of the ML4903 which must be Kelvin-connected to the sense resistor are ISENSE and GND. PWR GND should then return to the to the grounded end of RSENSE as well, using a high current Kelvin connection. This causes any noise across the resistor to appear primarily as a common-mode signal on ISENSE, GND, and PWR GND. Figure 4 shows a recommended implementation of these PCB layout requirements. When directly monitoring the voltage across the channel of the synchronous rectifier, the voltage across that MOSFET should be sensed as closely as possible to its drain. If a resistor divider is used to reduce the voltage at the ISENSE pin for a given current through (Q3||Q4)’s channel resistance, then the lower end of the divider should be returned to the immediate vicinity of its source. This ensures that the ML4903 monitors only the voltage across the synchronous rectifier, and not the voltage drops or inductive transients in the PCB traces which carry current into and out of it. If a PC board with a dedicated ground plane is used (recommended), the best return points for GND and PGND are directly into the ground plane. If the board does not have a dedicated ground plane, GND must be returned to a point near the IC which TO ISENSE TO PWR GND is relatively free from switching transients. Such a point may need to be empirically determined but will usually be near the ground connection of the output capacitor bank. MISCELLANEOUS POINTS ISENSE is the input to a medium-speed, high-sensitivity comparator (roughly comparable to an LM339-type comparator in terms of speed of response). Because of the leading-edge blanking on this comparator, it has a substantial ability to reject switching noise. Still, proper circuit function requires that the comparator not see significant noise at the time during which the synchronous rectifier MOSFET is on. The compensation components R3 and C13 are highimpedance nodes connected to the output of the voltage loop error amplifier. These components should be kept in close proximity to the ML4903. C13 should be returned to GND, not to PWR GND or the ground plane of the PC board. Keep the VREF bypass capacitor C14 close to the ML4903. Ensure that its ground connection is to GND, not to PWR GND. The 12V VDD input is both the converter's bulk power input, and the supply from which the internal circuitry of the ML4903 operates. VDD also provides the gate drive for P DRV and N DRV. The VDD pin of the ML4903 should be decoupled from the raw 12V system power to prevent noise on the 12V supply from affecting the circuit's switching action. A 10W resistor between 12VIN and VDD TO SYNCHRONOUS RECTIFIER MOSFET SOURCE SENSE RESISTOR TO GND POWER GROUND RETURN (GROUND PLANE) Figure 4. Kelvin Sense Connections 10 ML4903 DESIGN CONSIDERATIONS (Continued) of the ML4903, and the VDD bypass capacitors C10 and C15 serve this purpose. The VDD bypass capacitors should be returned to PWR GND or to the PC board ground plane. They should not be returned to GND due to high transient currents which could interfere with the current sensing function. VCC is the input to the 5V undervoltage lockout comparator circuitry. The 5V UVLO function makes the start-up of the ML4903 independent of power sequencing. It also provides load protection in case VCC should go below acceptable levels. To reject logic switching noise on the 5V input, an RC filter should be used between the 5V source and VCC. Typical values for this filter are R2 = 1kW, and C11 = 220nf. Optional capacitor C16 may be needed in some layouts to filter out “glitches” which could occur on the PWR GOOD signal. In conjunction with the resistive pullup for the PWR GOOD line, its value should yield an RC product of approximately 5µs. Power MOSFETs in 8-pin SOIC packages are among the best for this application, especially for the P-channel devices. Using P-channel MOSFETs minimizes component count while ensuring full enhancement of both the P-channel and N-channel MOSFETs. If 8-pin SOIC MOSFETs are chosen, keep in mind that the thermal dissipation capability of these parts is largely dictated by the copper area available to their drains. A good layout will maximize this area. 11 ML4903 PHYSICAL DIMENSIONS inches (millimeters) Package: T20 20-Pin TSSOP 0.251 - 0.262 (6.38 - 6.65) 20 0.169 - 0.177 (4.29 - 4.50) 0.246 - 0.258 (6.25 - 6.55) PIN 1 ID 1 0.026 BSC (0.65 BSC) 0.043 MAX (1.10 MAX) 0º - 8º 0.033 - 0.037 (0.84 - 0.94) 0.008 - 0.012 (0.20 - 0.30) SEATING PLANE 0.002 - 0.006 (0.05 - 0.15) 0.020 - 0.028 (0.51 - 0.71) 0.004 - 0.008 (0.10 - 0.20) ORDERING INFORMATION © Micro Linear 1999. PART NUMBER TEMPERATURE RANGE PACKAGE ML4903CT 0°C to 70°C 20-Pin TSSOP (T20) is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 DS4903-01 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 www.microlinear.com 07/12/99 Printed in U.S.A.