PIC18F46J50 FAMILY PIC18F46J50 Family Silicon Errata and Data Sheet Clarification The PIC18F46J50 family devices that you have received conform functionally to the current Device Data Sheet (DS39931C), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18F46J50 family silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (Rev. A4). For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ 3: 1. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger or PICkit™ 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a “Connect” operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. 2. 3. 4. Note: Data Sheet clarifications and corrections start on page 8, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18F46J50 family silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Device ID(1) Revision ID for Silicon Revision(2) A2 A4 PIC18F24J50 4C0Xh PIC18F25J50 4C2Xh PIC18F26J50 4C4Xh PIC18F44J50 4C6Xh PIC18F45J50 4C8Xh PIC18F46J50 4CAXh 2h 4h PIC18LF24J50 4CCXh PIC18LF25J50 4CEXh PIC18LF26J50 4D0Xh PIC18LF44J50 4D2Xh PIC18LF45J50 4D4Xh PIC18LF46J50 4D6Xh Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format “DEVID DEVREV”. 2: Refer to the “PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification” (DS39687) for detailed information on Device and Revision IDs for your specific device. 2010 Microchip Technology Inc. DS80436C-page 1 PIC18F46J50 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A2 A4 MSSP I2 C™ Modes 1. Must keep LATB<5:4> bits clear. MSSP I2C Slave 2. Module may not receive the correct data if there is a delay in reading SSPxBUF after SSPxIF interrupt. X X X EUSART Enable/Disable 3. If interrupts are enabled, a 2 TCY delay needed after re-enabling the module. X X A/D FOSC/2 Clock 4. FOSC/2 A/D Conversion mode may not meet linearity error limits. X X PMP PSP 5. Incorrect data capture in Slave modes. X Low-Power modes Deep Sleep 6. Wake-up events that occur during Deep Sleep entry may not generate an event. X DC Characteristics Supply Voltage 7. Minimum operating voltage (VDD) parameter for “F” devices is 2.25V. X A/D Band Gap Reference 8. At high VDD voltages, performing an A/D conversion on Channel 15 could have issues. X CTMU Constant Current 9. Low voltages turn off constant current source. Note 1: X X X Only those issues indicated in the last column apply to the current silicon revision. DS80436C-page 2 2010 Microchip Technology Inc. PIC18F46J50 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (Rev. A4). 1. Module: Master Synchronous Serial Port (MSSP1) 2. Module: Master Synchronous Serial Port (MSSP) In extremely rare cases, when configured for I2C™ slave reception, the MSSP module may not receive the correct data. This occurs only if the Serial Receive/Transmit Buffer Register (SSPxBUF) is not read within a window after the SSPxIF interrupt has occurred. Work around The issue can be resolved in either of these ways: If the LATB<5> or LATB<4> bit is set, the MSSP1 module will not work correctly in the I2C™ modes. If both LATB<5> and LATB<4> are clear, the module will work normally. • Prior to the I2C slave reception, enable the clock stretching feature. Work around • Each time the SSPxIF is set, read the SSPxBUF before the first rising clock edge of the next byte being received. Clear the bits, LATB<5:4>, prior to enabling the MSSP1 module in an I2C mode. Keep these bits clear while using the module. For operation in I2C modes, the TRISB<5:4> bits should be set. Affected Silicon Revisions A2 This is done by (SSPxCON2<0>). setting the SEN bit Affected Silicon Revisions A2 A4 X X A4 X 2010 Microchip Technology Inc. DS80436C-page 3 PIC18F46J50 FAMILY 3. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In rare situations, when interrupts are enabled, unexpected results may occur if: Work around Add a 2 TCY delay after any instruction that reenables the EUSART module (sets SPEN = 1). Refer to Example 1. • The EUSART is disabled (the SPEN bit, RCSTAx<7> = 0) • The EUSART is re-enabled (RCSTAx<7> = 1) • A two-cycle instruction is executed immediately after setting SPEN = 1 EXAMPLE 1: RE-ENABLING A EUSART MODULE ;Initial conditions: SPEN = 0 (module disabled) ;To re-enable the module: ;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed) ;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet ;Now enable the module, but add a 2-Tcy delay before executing any two-cycle ;instructions bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2 nop ;1 Tcy delay nop ;1 Tcy delay (two total) ;CPU may now execute 2 cycle instructions Affected Silicon Revisions A2 A4 X X DS80436C-page 4 2010 Microchip Technology Inc. PIC18F46J50 FAMILY 4. Module: 10-Bit Analog-to-Digital Converter (ADC) When the A/D conversion clock select bits are set for FOSC/2 (ADCON1<2:0> = 000), the Integral Linearity Error (EIL) parameter (A03) and Differential Linearity Error (EDL) parameter (A04) may exceed data sheet specifications. Work around 5. Module: Parallel Master Port (PMP) When configured for Parallel Slave Port (PMMODEH<1:0> = 0x and PMPEN = 1), the data bus (PMD<7:0>) may not work correctly and incorrect data could be captured into the PMDIN1L register. Work around None. Select one of the alternate AD clock sources shown in Table 3. The EIL and EDL parameters are met for the other clocking options. Affected Silicon Revisions A2 A4 X TABLE 3: ALTERNATE ADC SETTINGS ADCON1<2:0> ADCS<2:0> Clock Setting 110 101 100 011 010 001 FOSC/64 FOSC/16 FOSC/4 FRC FOSC/32 FOSC/8 Affected Silicon Revisions A2 A4 X X 2010 Microchip Technology Inc. DS80436C-page 5 PIC18F46J50 FAMILY 6. Module: Low-Power Modes (Deep Sleep) Entering Deep Sleep mode takes approximately 2 TCY, following the SLEEP instruction. Wake-up events that occur during this Deep Sleep entry period may not generate a wake-up event. instruction before the SLEEP instruction eliminates the 2 TCY window where wake-up events could be missed. Work around Before using this work around, users should check their device’s revision ID bits to verify that they have the A4 silicon. This can be done at run time by a table read from address, 3FFFFEh. If using the RTCC alarm for Deep Sleep wake-up, code should only enter Deep Sleep mode when the RTCC Value registers read synchronization bit (RTCCFG<4>) is clear. On revision A2 silicon devices, the instruction cannot be inserted between setting the DSEN bit and executing the SLEEP instruction or the device will enter conventional Sleep mode, not Deep Sleep. This will prevent missing an RTCC alarm that could occur during the period after the SLEEP instruction, but before the Deep Sleep mode has not been fully entered. Even on A4 silicon devices, if the firmware immediately executes SLEEP after setting DSEN, the device will enter Deep Sleep mode without benefitting from this work around. The revision A4 silicon allows insertion of a single instruction between setting the Deep Sleep Enable bit (DSEN, DSCONH<7>) and issuing the SLEEP instruction (see Example 2). The insertion of a NOP EXAMPLE 2: DEEP-SLEEP WAKE-UP WORK AROUND EnterDeepSleep: bsf DSCONH, DSEN nop sleep (…) goto EnterDeepSleep ; ; ; ; ; ; Enter Deep Sleep mode on SLEEP instruction Not compatible with A2 silicon Enter Deep Sleep mode Add code here to handle wake up events that may have been asserted prior to Deep Sleep entry re-attempt Deep Sleep entry if desired Affected Silicon Revisions A2 A4 X DS80436C-page 6 2010 Microchip Technology Inc. PIC18F46J50 FAMILY 7. Module: DC Characteristics (Supply Voltage) The minimum operating voltage (VDD) parameter (D001) for “F” devices is 2.25V. For “LF” devices (such as the PIC18LF46J50), the minimum rated VDD operating voltage is 2.0V. Work around None. Affected Silicon Revisions A2 A4 X 9. Module: Charge Time Measurement Unit (CTMU) On an “F” device, the CTMU current source will stop sourcing current if the applied VDD voltage falls below the LVDSTAT (WDTCON<6>) threshold (2.45V nominal). When VDD is above the LVDSTAT threshold, the CTMU will function normally. This issue does not apply to “LF” devices. The current source will continue to function normally at all rated voltages for these devices. Work around None Affected Silicon Revisions 8. Module: Analog-to-Digital Converter (Band Gap Reference) At high VDD voltages (ex: >2.5V), performing an ADC conversion on Channel 15 (the VBG absolute reference) can temporarily disturb the reference voltage supplied to the HLVD module and comparator module (only when configured to use the VIRV). At lower VDD voltages, the disturbance will be less or non-existent. A2 A4 X Work around If precise HLVD or comparator VIRV thresholds are required at high VDD voltages, avoid performing ADC conversions on Channel 15 while simultaneously using the HLVD or comparator VIRV. If an ADC conversion is performed on Channel 15, a settling time of approximately 100 s is needed before the reference voltage fully returns to the original value. Affected Silicon Revisions A2 A4 X X 2010 Microchip Technology Inc. DS80436C-page 7 PIC18F46J50 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the Device Data Sheet (DS39931C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Special Features (CONFIG2L) The “T1DIG” feature mentioned in the Device Data Sheet (DS39931C) is not implemented in this device family. The feature, associated with bit 3 of the CONFIG2L Configuration register, is discussed in Section 26.1 “Configuration Bits” and Section 2.5.1 “Oscillator Control Register”. 3. Module: DC Characteristics (Input Leakage) In Table 29-7 USB Module Specifications, electrical parameter D314 indicates the D+ and D- pin leakage is +/-0.2 A maximum. The updated specification is +/-0.5 A maximum, over the -40°C to +85°C temperature range. The input leakage specification for all other I/O pins remains unchanged at the +/-0.2 A maximum level, as indicated by electrical parameters D060, D061 and D063 (IIL), in Section 29.3 “DC Characteristics”. For application firmware to switch to the Timer1 clock source, it must first enable the crystal driver by setting the T1OSCEN bit (T1CON<3>). The microcontroller will ignore attempts to clock switch to the Timer1 clock source when the crystal driver is disabled. 2. Module: DC Characteristics (Power-Down Current) Section 29.2 “DC Characteristics: PowerDown and Supply Current” lists the maximum Power-Down (IPD) Sleep mode current for PIC18FXXJ50 devices, operating at VDD = 2.15V and -40°C, and 25°C at 5 A. The correct maximum is 6 A. DS80436C-page 8 2010 Microchip Technology Inc. PIC18F46J50 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (2/2009) First release of this document. Silicon issues 1 (T1DIG), 2-3 (MSSP), 4 (EUSART), 5 (ADC), 6 (PMP), 7 (Deep Sleep), 8 (Supply Voltage). Rev B Document (5/2009) Added silicon issues 9 (Band Gap Reference) and 10 (Charge Time Measurement Unit – CTMU). Rev C Document (1/2010) Converted existing document for the A2 silicon revision to the new, combined format. (There were no other silicon errata or data sheet clarification documents for the device family.) Removed silicon issue 1 (Special Features, T1DIG) and modified decremented issue 1, formerly 2 (MSSP1) and 6 (Low-Power Modes – Deep Sleep). Added data sheet clarifications 1 (Special Features – CONFIG2L), 2 (DC Characteristics – Power-Down Current) and 3 (DC Characteristics – Input Leakage). 2010 Microchip Technology Inc. DS80436C-page 9 PIC18F46J50 FAMILY NOTES: DS80436C-page 10 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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