dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
Family Silicon Errata and Data Sheet Clarification
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 family devices that you have received conform
functionally to the current Device Data Sheet
(DS70318F), except for the anomalies described in this
document.
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
2.
3.
1.
4.
The errata described in this document will be addressed
in future revisions of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A4).
5.
Note:
Data Sheet clarifications and corrections start on page 17,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
The Device and Revision ID values for the various
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 silicon revisions are shown in Table 1.
Device ID(1)
dsPIC33FJ06GS101
0x0C00
dsPIC33FJ06GS102
0x0C01
dsPIC33FJ06GS202
0x0C02
dsPIC33FJ16GS402
0x0C04
dsPIC33FJ16GS404
0x0C06
dsPIC33FJ16GS502
0x0C03
dsPIC33FJ16GS504
0x0C05
2:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
SILICON DEVREV VALUES
Part Number
Note 1:
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window >
Dashboard and click the Refresh Debug
Tool Status icon (
).
Depending on the development tool used, the
part number and Device ID and Revision ID
values appear in the Output window.
Revision ID for Silicon Revision(2)
A2
A3
A4
0x3002
0x3003
0x3004
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.
2009-2013 Microchip Technology Inc.
DS80439M-page 1
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Affected
Revisions(1)
Issue Summary
A2
A3
A4
PWM
Leading-Edge
Blanking
1.
Reading LEBCONx registers, as well as writing individual
bits and bytes within these registers, does not work.
X
X
X
PWM
Immediate
Updates
2.
PWM Immediate Update mode (IEU = 1) for the Master
Duty Cycle register (MDC) is not functional.
X
X
X
PWM
Status Bits
3.
PWM Fault Status bits do not function if the associated
PWM Fault interrupts are disabled.
X
X
X
PWM
Clock
4.
PWM output will exhibit jitter with some PWM clock divider
settings.
X
X
X
PWM
Faults
5.
If the PWM is in Complementary, Redundant and PushPull mode and the Independent Time Base bit (ITB) is set,
the Independent Fault mode may not work as expected for
the PWMxL pin.
X
X
X
PWM
Independent
Time Base
6.
The Independent Time Base PWM outputs may not be
synchronized with the Master time base PWM outputs
when both modes are used simultaneously.
X
X
X
PWM
Latched Faults
7.
In PWM Latched Fault mode, the PWM outputs may be
latched on both the rising as well as the falling edge of the
Fault signal regardless of the Fault input polarity selection
(set with the FCLCONx<FLTPOL> bit setting).
X
X
X
PWM
Faults
8.
A bit write to the CLMOD bit (bit 8) in the FCLCONx
register, or consecutive writes to the lower byte and higher
byte of the FCLCONx register, causes all other bits of the
high byte to be loaded with zeros.
X
X
X
PWM
Sleep Mode
9.
The PWM module fails to wake the CPU from Sleep mode
on a PWM Fault event.
X
X
X
Comparator
—
10.
For slow input signals, the Comparator module may
generate erroneous triggers/interrupts.
X
X
X
ADC
Clock
11.
Selecting the primary FRC (FVCO) as a clock source for
the ADC module by setting the SLOWCLK bit
(ADCON<12>) to the default setting of ‘0’, does not work.
X
X
X
Auxiliary
Clock
Module Disable
12.
When the PWMMD bit in the PMD1 register is set, the
Auxiliary Clock to both the ADC and PWM modules is
disabled.
X
X
X
Comparator
Interrupts
13.
Comparator interrupts are incorrectly generated when the
High-Speed Analog Comparator is configured for an
inverted polarity setting (CMPCONx<CMPPOL> = 1).
X
X
X
UART
4x Mode
14.
When the UART is in 4x mode (BRGH = 1) and using two
Stop bits (STSEL = 1), it may sample the first Stop bit
instead of the second one.
X
X
X
UART
IR Interface
Operations
15.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
X
X
X
I2C™
10-bit
Addressing
Mode
16.
When the I2C™ module is configured for 10-bit
addressing using the same address bits (A10 and A9) as
other I2C devices, the A10 and A9 bits may not work as
expected.
X
X
X
PWM
ADC
Conversion
17.
The PWM module may fail to trigger a conversion on
certain ADC pairs when the primary or secondary PWMx
generator is selected as a trigger source.
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80439M-page 2
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
TABLE 2:
SILICON ISSUE SUMMARY (CONTINUED)
Module
Feature
Item
Number
Affected
Revisions(1)
Issue Summary
A2
A3
A4
PGEC3/
PGED3
Programming
Pins
Device
Programming
18.
When using the PGEC3/PGED3 pins for device
programming, the programming time may be slower as
compared to other available PGECx/PGEDx pin pairs.
X
X
X
UART
Break
Character
Generation
19.
The UART module will not generate back-to-back Break
characters.
X
X
X
PWM
Current Limit
20.
Cycle-by-cycle current-limit operation does not work when
the PWM module is configured for Center-Aligned mode.
X
X
X
PWM
Current Reset
Mode
21.
Current Reset mode does not work when the current-limit
source (CLSRC) occurs during, and persists past, the
assertive time interval of the PWM, and leading-edge
blanking time is less than the PWM assertive time interval.
X
X
X
UART
IrDA® Encoder/
Decoder and
8-bit Operating
Mode
22.
When the UART module is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
X
X
X
UART
UxE Interrupt
23.
The UART error interrupt may not occur, or may occur at
an incorrect time, if multiple errors occur during a short
period of time.
X
X
X
I2C
10-bit
Addressing
Mode
24.
When the I2C module is configured as a 10-bit slave with
an address of 0x102, the I2CxRCV register content for the
lower address byte is 0x01 rather than 0x02.
X
X
X
I2C
10-bit
Addressing
Mode
25.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register, on address match if the Least
Significant bits (LSbs) of the address are the same as the
7-bit reserved addresses.
X
X
X
PSV
Operations
Addressing
Modes
26.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
X
X
X
Comparator
Sleep Mode
27.
The Comparator fails to wake the CPU from Sleep mode
when the internal voltage reference is used.
X
X
X
PWM
Independent
Time Base
28.
When updating the frequency on the fly, push-pull PWM
outputs may not be synchronized with other PWM output
modes.
X
X
X
Analog
Comparator
Internal
Band Gap
Reference
Voltage
29.
The Internal Band Gap Reference Voltage (INTREF) for
the analog comparator does not meet the stated accuracy
specifications.
X
X
X
Auxiliary PLL
Input
Frequency
30.
For extended temperature devices, the auxiliary PLL input
frequency does not meet the published specification
range.
X
X
X
ADC
Current
Consumption
in Sleep Mode
31.
If the ADC module is in an enabled state when the device
enters Sleep mode, the power-down current (IPD) of the
device may exceed the device data sheet specifications.
X
X
X
High-Speed
PWM
PWM Module
Enable
32.
A glitch may be observed on the PWM pins when the
PWM module is enabled after assignment of pin
ownership to the PWM module.
X
X
X
Reserved
—
33.
Note 1:
—
—
Only those issues indicated in the last column apply to the current silicon revision.
2009-2013 Microchip Technology Inc.
DS80439M-page 3
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
TABLE 2:
SILICON ISSUE SUMMARY (CONTINUED)
Module
Feature
Item
Number
Affected
Revisions(1)
Issue Summary
A2
A3
A4
PWM
Duty Cycle
Updates
34.
When the PWM duty cycle update coincides with the
PWM period rollover, the PWM output may be corrupted
for one PWM period.
X
X
X
JTAG
Active Pull-up
35.
In JTAG mode, the TMS pin will not have an active pull-up
as required by the JTAG specification.
X
X
X
SPI
Framed Master
Mode
36.
When the SPI module is configured in Framed Master
mode and the Frame Sync Pulse Edge Select bit
(FRMDLY) is set to ‘1’, transmitting a word and then
buffering another word in the SPIxBUF register before the
transmission has completed, results in an incomplete
transmission of the first data word.
X
X
X
Comparator
Trigger Voltage
Level
37.
Output signal transitions occurring on the DACOUT pin
(with DAC output disabled) can cause the Comparator
trigger voltage level to change.
X
X
X
CPU
Interrupt
Disable
38.
When a previous DISI instruction is active (i.e., the
DISICNT register is non-zero), and the value of the
DISICNT register is updated manually, the DISICNT
register freezes and disables interrupts permanently.
X
X
X
CPU
div.sd
39.
When using the div.sd instruction, the overflow bit is not
getting set when an overflow occurs.
X
X
X
UART
TX Interrupt
40.
A Transmit (TX) interrupt may occur before the data
transmission is complete.
X
X
X
JTAG
Flash
Programming
41.
JTAG Flash programming is not supported.
X
X
X
PWM
Edge-Aligned
Complimentary
Mode
42.
When operating in Edge-Aligned Complimentary mode,
the dead time could become 0.
X
X
X
PWM
PWM Module
Enable
43.
If the PWM Clock Divider Select register, PTCON2, is not
equal to zero, the PWM module may or may not initialize
from an override state
X
X
X
PWM
PWM SWAP
44.
If the PWM is configured for Complimentary mode and the
SWAP bit is enabled, the PWM outputs might operate as
Redundant mode when the PHASE value is greater than
the programmed dead-time (DTRx) value.
X
X
X
PWM
PWM in
Current-Limit
Mode
45.
A <8-ns glitch may be observed on the PWM output pins
when the Current-Limit event occurs.
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80439M-page 4
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
1. Module: PWM
Reading LEBCONx registers, as well as writing
individual bits and bytes within these registers
does not work.
Work around
Use a Word write operation to modify LEBCONx
registers. For example, to set the PHR bit within
the LEBCON1 register, use the following C code:
LEBCON1 = 0x8000
There is no work around for reading LEBCONx
registers.
Affected Silicon Revisions
A2
A3
A4
X
X
X
2. Module: PWM
If PWM Immediate Update mode is selected
(IUE = 1), and the PWM duty cycle is provided via
the Master Duty Cycle (MDC) register (MDCS = 1
mode), the updates to the MDC register are
synchronized to the PWM time base instead of an
immediate update (duty cycle will be updated on
the next PWM period).
3. Module: PWM
If PWM Fault interrupts are disabled (FLTIEN = 0
or CLIEN = 0), then associated Status bits
(FLTSTAT and CLSTAT) will not function.
Work around
Enable PWM
CLIEN = 1).
Fault
interrupts
(FLTIEN = 1,
Affected Silicon Revisions
A2
A3
A4
X
X
X
4. Module: PWM
The PWM output will exhibit jitter under the
following conditions:
When the PWM clock divider has the value of 1, 5
or 6 (PTCON2<PCLKDIV> = 0b001, 0b101 or
0b110), and the three Least Significant bits of the
PWM Period Register (PTPER or PHASEx), Duty
Cycle Register (MDC or PDCx) or Phase Register
(PHASEx) are non-zero.
Work around
Use PWM clock dividers other than 1, 5 or 6.
Affected Silicon Revisions
A2
A3
A4
X
X
X
Work arounds
Work around 1:
Use the Enable Immediate Period Update mode
(EIPU = 1) in conjunction with PWM Immediate
Update mode (IUE = 1). This will update the period
and duty cycle on an immediate basis.
Work around 2:
Use individual duty cycle registers (PDCx) and
PWM Immediate Update mode (IUE = 1) to update
individual duty cycle registers on an immediate
basis.
Affected Silicon Revisions
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
DS80439M-page 5
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
5. Module: PWM
When
PWM
module
is
operated
in
Complementary, Redundant and Push-pull output
modes, with Independent Time Base (ITB = 1) and
Independent Fault mode (IFLTMOD = 1) enabled,
the PWMxH and PWMxL outputs should be
affected by the Fault and Current-Limit events as
follows:
• PWMxH is affected by Current-Limit source
(FCLCON<CLSRC>) and the Current-Limit
should be reset at the end of the primary local
time base.
• PWMxL is affected by Fault source
(FCLCON<FLTSRC>) and the Fault should be
reset at the end of the primary local time base.
On silicon revisions affected by this erratum, the
Current-Limit event works correctly for the PWMxH
pin. However, the Fault event is reset by the
secondary local time base although it is not used to
generate the time base value. As a result, the Fault
event on PWMxL pin may not work as expected.
This erratum only applies to the cycle-by-cycle Fault
mode (FLTMOD = 0b01).
Work around
If PWM is in Complementary, Redundant or PushPull mode and (ITB = 1), set SPHASEx to have the
same value as PHASEx. This will ensure that the
Fault event on the PWMxL pin is reset at the start
of the new PWM period for cycle-by-cycle
independent Fault operation.
Affected Silicon Revisions
A2
A3
A4
X
X
X
6. Module: PWM
The independent time base PWM outputs may not
be synchronized with the Master time base PWM
outputs
when
both
modes
are
used
simultaneously.
Work around
To synchronize the Independent PWM outputs
with the Master time base PWM outputs, disable
the Immediate Update Enable bit (IUE = 0), ensure
that the three Least Significant bits of the period
are zero, and that the duty cycle is between 8 ns
and the period minus 0x8.
This work around will not work if the frequency of
the PWM module is being updated on the fly.
Affected Silicon Revisions
A2
A3
A4
X
X
X
7. Module: PWM
In PWM Latched Fault mode, the PWM outputs
may be latched on both the rising as well as the
falling edge of the Fault signal, regardless of the
Fault input polarity selection (set with the
FCLCONx<FLTPOL> bit setting).
Work around
None.
Affected Silicon Revisions
A2
A3
A4
X
X
X
8. Module: PWM
A bit write to the CLMOD bit (bit 8) in the
FCLCONx register or consecutive writes to the
lower byte and higher byte of the FCLCONx
register, causes all other bits of the high byte to be
loaded with zeros.
Work around
Use Word writes for the FCLCONx register instead
of bit or byte writes.
Affected Silicon Revisions
DS80439M-page 6
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
9. Module: PWM
The PWM module fails to wake the CPU from
Sleep mode on a PWM Fault event.
Work around
Use the external interrupt pins to wake the CPU
from Sleep mode.
Affected Silicon Revisions
A2
A3
A4
X
X
X
10. Module: Comparator
If the slew rate of the Comparator input signal is
lower than 198 mV/µs, the Comparator module
generates erroneous triggers/interrupts.
Work around
The Slew rate of Comparator input signal must be
higher than 198 mV/µs to avoid multiple triggers/
interrupts.
Affected Silicon Revisions
A2
A3
A4
X
X
X
11. Module: ADC
Selecting the primary FRC (FVCO) as a clock
source for the ADC module by setting the
SLOWCLK bit (ADCON<12>) to the default setting
of ‘0’, does not work.
Work around
Always set the SLOWCLK bit (ADCON<12>) to ‘1’,
which selects the Auxiliary Clock (ACLK) as a
clock source for the ADC. Use the Auxiliary Clock
Configuration registers to select the primary FRC
(FVCO) as a source (if desired) or other clock
sources as inputs. See Section 8.0 “Oscillator
Configuration” of the device data sheet
(DS70318) for more information.
Affected Silicon Revisions
A2
A3
A4
X
X
X
12. Module: Auxiliary Clock
When the PWMMD bit in the PMD1 register is set,
the Auxiliary Clock to both the ADC and PWM
modules is disabled.
Work around
To disable the Auxiliary clock for the PWM module
but not for the ADC module, set the individual
PWM generator PMD bits in the PMD6 register.
Affected Silicon Revisions
A2
A3
A4
X
X
X
13. Module: Comparator
The comparator interrupt should be generated on
a rising edge of the comparator output. When
using the inverted polarity setting for the analog
comparator (CMPCONx<CMPPOL> = 1), the
interrupt should be generated when the analog
voltage at the comparator input falls below the
programmable threshold determined by the
CMPDAC register setting. However, with this
setting the interrupts may be generated regardless
of the state of the comparator.
Work around
When using comparator interrupts, configure the
external circuit to use the non-inverted polarity
comparator setting (CMPCONx<CMPPOL> = 0).
Affected Silicon Revisions
A2
A3
A4
X
X
X
14. Module: UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
2009-2013 Microchip Technology Inc.
A2
A3
A4
X
X
X
DS80439M-page 7
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
15. Module: UART
17. Module: PWM
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
When the primary or secondary PWMx generator
is selected as a trigger source for ADC convert
pairs 3, 4, 5 or 6 and the PWM module is running
at the maximum speed, the PWM module may fail
to trigger a conversion on these ADC pairs.
Work around
Work arounds
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
Work around 1:
Affected Silicon Revisions
A2
A3
A4
X
X
X
16. Module: I2C™
If there are two I2C devices on the bus, one of
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are
configured for 10-bit addressing mode, and have
the same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I2C devices, the addresses as well as bits
A10 and A9 should be different.
A3
A4
X
X
X
1. Enable the dual trigger mode bit (DTM) in the
TRGCONx register.
2. Configure the TRIGx register to the desired
trigger point.
3. Configure the STRIGx register to TRIGx + 0x8.
4. Select the PWMx primary trigger as the ADC
trigger source for conversion.
If the PWM channel is configured for independent
output mode and both channels are operating on
the same time base, the phase difference between
the two channels must be considered when setting
the STRIGx register. This work around will not
work for True Independent Time Base mode.
With this work around, the PWMx secondary
trigger should not be selected as the trigger source
for the ADC convert pair.
Work around 2:
Configure the PWM Input Clock Prescaler bits
(PCLKDIV) for divide by 2 or higher.
Work around 3:
Utilize other available trigger sources, such as
software or timer triggers, to initiate conversion on
the affected ADC convert pairs.
Affected Silicon Revisions
A2
Configure the PWM module to trigger the ADC
module per the following steps (see Example 1 for
the code used in this work around):
Affected Silicon Revisions
A2
A3
A4
X
EXAMPLE 1:
USING DUAL TRIGGER MODE
TRGCON1bits.DTM = 1;
/*
/*
TRIG1 = 1224;
/*
STRIG1 = 1232;
/*
ADCPC2bits.TRGSRC5 = 0x4; /*
DS80439M-page 8
Dual trigger mode (DTM) and STRIG used in combination to generate */
ADCPx triggers */
Configure desired trigger */
STRIG1 should be configured for TRIG1 + 8 */
PWM1 primary trigger selected as ADC trigger source for ADCP5*/
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
18. Module: PGEC3/PGED3 Programming
Pins
When using the PGEC3/PGED3 pins for device
programming, the programming time may be
slower as compared to other available PGECx/
PGEDx pin pairs, because the Enhanced ICSP™
programming algorithm cannot be executed on
this pin pair.
Refer
to
the
“dsPIC33F/PIC24H
Flash
Programming Specification” (DS70152) for
additional information on this limitation.
Work around
Use alternate PGECx/PGEDx programming pin
pairs.
Affected Silicon Revisions
A2
A3
A4
X
X
X
19. Module: UART
The UART module will not generate consecutive
Break characters. Trying to perform a back-toback Break character transmission will cause the
UART module to transmit the dummy character
used to generate the first Break character instead
of transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
21. Module: PWM
During normal operation, if Leading-Edge
Blanking (LEB) is triggered to start counting at a
rising edge of PWM and the PWM module has a
blanking time period less than the PWM assertive
time (TON time), and the current-limit event occurs
during the TON period and is still pending after the
TON period is over, the current-limit event should
be ignored during TON time, but should be
recognized after the TON time is over.
However, the device fails to recognize the currentlimit event after TON time is over, when previously
described conditions exist.
Work around
Initialize the LEBCONx register as shown below,
which specifies the LEB function for the (CLSRC)
input to be triggered on the falling (trailing) edge of
PWM, and set the LEB delay to a minimum value
of 8 ns:
• PHF bit is set
• CLLEBEN bit is set
• LEB<9:3> bits are set to a minimum value of ‘1’
If the user application needs LEB to be triggered at
a falling edge, make sure that the LEB delay is set
for more than the TON time.
Affected Silicon Revisions
A2
A3
A4
X
X
X
22. Module: UART
Affected Silicon Revisions
A2
A3
A4
X
X
X
20. Module: PWM
Cycle-by-cycle current-limit operation does not
work when the PWM module is configured for
Center-Aligned mode.
Work around
None.
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA® encoder/
decoder (IREN = 1), the module incorrectly
transmits a data payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
A2
A3
A4
X
X
X
Affected Silicon Revisions
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
DS80439M-page 9
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
23. Module: UART
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
Affected Silicon Revisions
A2
A3
A4
X
X
X
24. Module: I2C
When the I2C module is configured as a 10-bit
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02; however, the module
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
A2
A3
A4
X
X
X
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register I2CxRCV, if the lower address
byte matches the reserved addresses. In
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
001111000X
011111001X
101111010X
111111011X
• MOV.D
• Register Indirect Addressing (Word or Byte
mode) with pre/post-decrement
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
Version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 toolsuite for further details.
Affected Silicon Revisions
A2
A3
A4
X
X
X
27. Module: Comparator
The comparator fails to wake the CPU from Sleep
mode when the internal voltage reference is used
(i.e., the EXTREF bit is set to ‘0’).
Use the external reference source by setting the
EXTREF bit to ‘1’.
Affected Silicon Revisions
A2
A3
A4
X
X
X
28. Module: PWM
When multiple PWM channels are operating in
Independent Time Base mode (ITB = 1) and the
frequency is being updated on the fly, PWM channels
configured for Push-Pull mode may not remain
synchronized with other PWM output modes.
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
A2
A3
A4
X
X
X
DS80439M-page 10
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This occurs only when using the
following addressing modes:
Work around
25. Module: I2C
•
•
•
•
26. Module: PSV Operations
Work around
When multiple PWM channels are operating in
Independent Time Base mode, immediate updates
to the PWM module (IUE = 1) must be enabled for
PWM channels to remain synchronized.
Affected Silicon Revisions
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
29. Module: Analog Comparator
The Internal Band Gap Reference Voltage
(INTREF) for the analog comparator provides the
reference to the analog comparator if the EXTREF
bit (CMPCONx<5>) = 0 and the RANGE bit
(CMPCONx<0>) = 0.The data sheet states that
the INTREF voltage should be 1.2V nominal and
within ±1%.
However, the internal band gap reference voltage
does not meet the specification stated above. For
the actual range of the INTREF voltage, refer to
the IVREF specification in the “Electrical
Characteristics” chapter of the device data
sheet.
Work arounds
To avoid this issue, implement one of the following
two work arounds, depending on the application
requirements.
30. Module: Auxiliary PLL
For extended temperature devices (designated
with the -E suffix in the device part number) with
the date code of 09XX, the auxiliary PLL input
frequency does not meet the published
specification range at operating temperatures
above 85ºC.
Work around
Use the internal FRC oscillator as the input to the
auxiliary PLL, or use the external oscillator with a
frequency of 7.37 MHz.
Affected Silicon Revisions
A2
A3
A4
X
X
X
Work around 1:
Use an external voltage reference for the Analog
Comparator by setting the EXTREF bit
(CMPCONx<5>) = 1 and providing an external
reference to the EXTREF pin.
Work around 2:
Use the high-range setting for the internal
reference by setting the EXTREF bit
(CMPCONx<5>) = 0 and the RANGE bit
(CMPCONx<0>) = 1. This setting uses AVDD/2 as
the comparator reference voltage.
Affected Silicon Revisions
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
DS80439M-page 11
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
31. Module: ADC
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (IPD) may exceed the specifications listed
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work arounds
Work around 1:
In order to remain within the IPD specifications
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
#0
instruction.
Note:
The ADC module must be reinitialized by
the user application before resuming ADC
operation.
Work around 2:
If the ADC module was previously initialized and
enabled, before entering Sleep, execute the lines
of code provided in Example 2.
Note:
Unlike Work around 1, the user
application does not need to reinitialize
the ADC module; however, it is necessary
to re-enable the ADC module by setting
the ADON bit after waking from Sleep.
EXAMPLE 2:
AD1CON1bits.ADON = 0;
__asm__ volatile ("REPEAT #50");
__asm__ volatile ("NOP");
Sleep();
//Disable the ADC module
//Wait 50 TCY
//Repeat NOP 51 times
// Execute PWRSAV #0 and go to Sleep
Affected Silicon Revisions
A2
A3
A4
X
X
X
DS80439M-page 12
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
32. Module: High-Speed PWM
2. Assign pin ownership to the GPIO module by
configuring IOCONx<PENH> = 0
and
IOCONx<PENL> = 0.
3. Specify the PWM override state to the desired
safe state for the PWM pins using the
OVRDAT<1:0> bit field in the IOCONx register.
4. Override
the
PWM
outputs
by
setting IOCONx<OVRENH> = 1 and
IOCONx<OVRENL> = 1.
5. Enable the PWM module by setting
PTCON<PTEN> = 1.
6. Remove
the
PWM
overrides
by
making IOCONx<OVRENH> = 0 and
IOCONx<OVRENL> = 0.
7. Ensure a delay of at least one full PWM cycle.
8. Assign pin ownership to the PWM module
by setting IOCONx<PENH> = 1 and
IOCONx<PENL> = 1.
The PENH and PENL bits in the IOCONx register
are used to assign ownership of the pins to either
the PWM module or the GPIO module. The correct
procedure to configure the PWM module is to
assign pin ownership to the PWM module and then
enabling it using the PTEN bit in the PTCON
register.
If the PWM module is enabled using the above
sequence, then a glitch may be observed on the
PWM pins before actual switching of the PWM
outputs begins. This glitch may cause momentary
turn-on of power MOSFETs that are driven by the
PWM pins and may cause damage to the
application hardware.
Work around
Follow the given sequence to avoid any glitches
from appearing on the PWM outputs at the time of
enabling.
The code in Example 3 illustrates the use of this
work around.
1. Configure the respective PWM pins to digital
inputs using the TRISx registers. This step will
put the PWM pins in a high-impedance state.
The PWM outputs must be maintained in a safe
state by using pull-up or pull-down resistors.
EXAMPLE 3:
Affected Silicon Revisions
A2
A3
A4
X
X
X
CONFIGURE PWM MODULE TO PREVENT GLITCHES ON PWM1H AND PWM1L
PINS AT THE TIME OF ENABLING
TRISAbits.TRISA4 = 1;
TRISAbits.TRISA3 = 1;
//
//
//
//
//
//
Configure PWM1H/RA4
Ensure output is in
pull-down resistors
Configure PWM1L/RA3
Ensure output is in
pull-down resistors
as digital input
safe state using pull-up or
as digital input
safe state using pull-up or
IOCON1bits.PENH = 0;
IOCON1bits.PENL = 0;
// Assign pin ownership of PWM1H/RA4 to GPIO module
// Assign pin ownership of PWM1L/RA3 to GPIO module
IOCON1bits.OVRDAT = 0;
// Configure override state of the PWM outputs to
// desired safe state.
IOCON1bits.OVRENH = 1;
IOCON1bits.OVRENL = 1;
// Override PWM1H output
// Override PWM1L output
PTCONbits.PTEN = 1;
// Enable PWM module
IOCON1bits.OVRENH = 0;
IOCON1bits.OVRENL = 0;
// Remove override for PWM1H output
// Remove override for PWM1L output
Delay(x);
IOCON1bits.PENH = 1;
IOCON1bits.PENL = 1;
// Introduce a delay greater than one full PWM cycle
// Assign pin ownership of PWM1H/RA4 to PWM module
// Assign pin ownership of PWM1L/RA3 to PWM module
2009-2013 Microchip Technology Inc.
DS80439M-page 13
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
33. Module: Reserved
36. Module: SPI
The issue in a previous version of the document
was removed.
34. Module: PWM
The High-Speed PWM provides a feature to
update the PWM duty cycle at any time during the
PWM period. The new duty cycle should take
effect:
• On the next PWM period when immediate duty
cycle updates are disabled
(PWMCONx<IUE> = 0).
• On the same PWM period when immediate
duty cycle updates are enabled
(PWMCONx<IUE> = 1).
However, when the immediate duty cycle updates
are disabled and the duty cycle update coincides
with a PWM period roll-over, the PWM output may
be corrupted and exhibit a 100% duty cycle for one
PWM period. The new duty cycle value will take
effect on the next PWM period.
Work around
Enable immediate duty cycle
configuring PWMCONx<IUE> = 1.
updates
by
Affected Silicon Revisions
A2
A3
A4
X
X
X
35. Module: JTAG
In JTAG mode, the TMS pin will not have an active
pull-up as required by the JTAG specification.
Instead, the pull-up function will be enabled on the
TCK pin.
Note:
This issue is only present in the
dsPIC33FJ06GS101 device.
Work around
An external pull-up resistor can be connected to
the TMS pin to ensure that the signal does not
enter a tri-state condition when in JTAG mode.
There is no work around for the wrongly enabled
pull-up function on the TCK pin.
Affected Silicon Revisions
A2
A3
A4
X
X
X
DS80439M-page 14
When the SPI module is configured in Framed
Master mode and the Frame Sync Pulse Edge
Select bit (FRMDLY) is set to ‘1’, transmitting a
word and then buffering another word in the SPIxBUF register before the transmission has completed, results in an incomplete transmission of the
first data word. Only the first 15 bits from the first
data word are transmitted, followed by the sync
pulse and the complete second word.
Work around
Between the two back-to-back SPI operations,
add a delay to ensure that the first word is fully
transmitted before the second word is written to
the SPIxBUF register, as shown in Example 4.
EXAMPLE 4:
SPI1BUF = 0x0001;
while (SPI1STATbits.SPITBF);
asm("REPEAT #50");.
asm("NOP");
// The number of NOPs depends on the SPI
// clock prescalers
SPI1BUF = 0x0002;
Affected Silicon Revisions
A2
A3
A4
X
X
X
37. Module: Comparator
With the DAC output is disabled by clearing the
DACOEN bit (CMPCONx<8>), output signal
transitions occurring on the DACOUT pin can
cause the comparator trigger voltage level to
change. For example, if the UART1 Transmit
(U1TX) signal is mapped to the same pin as
DACOUT, UART data transmissions can cause
the comparator to get triggered at different trigger
levels than what is programmed through the
CMPDACx register.
Work around
When the comparator is enabled, do not use the
DACOUT pin, either as a general purpose I/O pin
or a peripheral output signal.
Affected Silicon Revisions
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
38. Module: CPU
When a previous DISI instruction is active (i.e.,
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the
DISICNT register freezes and disables interrupts
permanently.
Work around
Avoid updating the DISICNT register manually.
Instead, use the DISI #n instruction with the
required value for ‘n’.
Affected Silicon Revisions
A2
A3
A4
X
X
X
39. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
A2
A3
A4
X
X
X
40. Module: UART
When using UTXISEL = 01 (interrupt when last
character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register, the
Transmit (TX) interrupt may occur before the final
bit is shifted out.
41. Module: JTAG
JTAG Flash programming is not supported.
Work around
None.
Affected Silicon Revisions
A2
A3
A4
X
X
X
42. Module: PWM
When operating in Edge-Aligned Complimentary
mode, if the duty cycle (PDCx) becomes less than
the alternate dead time (ALTDTRx), the dead time
on the PWMs will become 0.
Work around
Ensure that the duty cycle (PDCx) always meets
the following condition: PDCx > (ALTDTRx – 1).
Affected Silicon Revisions
A2
A3
A4
X
X
X
43. Module: PWM
If the PWM Clock Divider Select register, PTCON2, is
not equal to zero, the PWM module may or may
not
initialize
from
an
override
state
(IOCONxbits.OVRENH = 1 or
IOCONxbits.OVRENL = 1).
Work around
When configuring the Override Enable bits
(OVRENL/OVRENH) in the PWMx I/O Control
register, IOCONx, set these bits implicitly via word
format and not explicitly via bit format.
Work around
For example:
If it is critical that the interrupt processing occur
only when all transmit operations are complete.
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
IOCONx = IOCONx & 0xFCFF;
Affected Silicon Revisions
A2
A3
A4
X
X
X
Affected Silicon Revisions
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
DS80439M-page 15
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
44. Module: PWM
If the PWM is configured for Complimentary mode
and the SWAP bit is enabled, the PWM outputs
might operate as Redundant mode when the
PHASE value is greater than the programmed
dead-time (DTRx) value.
Work around
Using true independent output mode with the
independent Time Base mode bit (ITB) set to ‘0’,
the PWM module can be configured to replicate
the original complementary signal by properly
setting up the phase (PHASEx, SPASEx) and the
independent duty cycle (PDCx, SDCx).
Affected Silicon Revisions
A2
A3
A4
X
X
X
45. Module: PWM
The PWM current-limit operation allows the PWM
module to set/reset the output signals when a
specific current limit is detected with a minimum
latency delay. When operating the PWM module in
Complementary mode (PMOD = 0), positive dead
time, and with Current-Limit Interrupt Enable
(CLIEN = 1), a less than 8-ns pulse glitch on the
complementary output may be present right after
the current limit is detected. This glitch, if present,
will occur prior to the implementation of the dead
time.
Work around
In order to avoid the <8 ns glitch to be propagated
into the MOSFET gate driver, a low-pass filter
(e.g., resistor-capacitor network) should be
implemented between the dsPIC® DSC PWM
output pin and the gate driver IC input pin.
Affected Silicon Revisions
DS80439M-page 16
A2
A3
A4
X
X
X
2009-2013 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS70318F):
Note:
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
1. Module: Idle Current (IIDLE)
The typical values for Table 24-6 were stated
incorrectly in the data sheet. The correct values
are shown in Table 3.
TABLE 3:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off Clock On Base Current(2)
DC40d
48
—
mA
-40°C
DC40a
48
—
mA
+25°C
DC40b
48
—
mA
+85°C
DC40c
48
—
mA
+125°C
DC41d
60
—
mA
-40°C
DC41a
60
—
mA
+25°C
DC41b
60
—
mA
+85°C
DC41c
60
—
mA
+125°C
DC42d
68
—
mA
-40°C
DC42a
68
—
mA
+25°C
DC42b
68
—
mA
+85°C
DC42c
68
—
mA
+125°C
DC43d
77
—
mA
-40°C
DC43a
77
—
mA
+25°C
DC43b
77
—
mA
+85°C
DC43c
77
—
mA
+125°C
DC44d
86
—
mA
-40°C
DC44a
86
—
mA
+25°C
DC44b
86
—
mA
+85°C
86
—
mA
+125°C
DC44c
Note 1:
2:
3:
3.3V
10 MIPS(3)
3.3V
16 MIPS(3)
3.3V
20 MIPS(3)
3.3V
30 MIPS(3)
3.3V
40 MIPS
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
Base IIDLE current is measured with core Off, clock On and all modules turned off. Peripheral module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
These parameters are characterized but not tested in manufacturing.
2009-2013 Microchip Technology Inc.
DS80439M-page 17
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
APPENDIX A:
REVISION HISTORY
Rev A Document (3/2009)
Initial release of this document; issued for revision A2
silicon.
Includes silicon issues 1-9 (PWM), 10 (Comparator), 11
(ADC), 12 (Auxiliary Clock), 13 (Comparator), 14-15
(UART) and 16 (I2C™).
Rev M Document (1/2013)
Ammends silicon issue 43 with correct PWM Clock
Divider Select register bit name (changed from PTCON
to PTCON2).
Includes silicon issue 45 (PWM).
Rev B Document (4/2009)
Added silicon issue 17 (PWM).
Rev C Document (5/2009)
Updated silicon issue 17 (PWM) to clarify which ADC
pairs are involved.
Rev D Document (5/2009)
Revised to include revision A3 silicon information.
Added silicon issues 18 (PGEC3/PGED3 Programming
Pins), 19 (UART) and 20-21 (PWM).
Added data sheet clarification 1 (Idle Current (IIDLE)).
Rev E Document (8/2009)
Added silicon issues 22-23 (UART), 24-25 (I2C), 26
(PSV Operations), 27 (Comparator) and 28 (PWM).
Rev F Document (1/2010)
Added silicon issues 29 (Analog Comparator) and
30 (Auxiliary PLL).
Added data sheet clarification 2 (Auxiliary PLL).
Rev G Document (6/2010)
Added silicon issues 31 (ADC) and 32 (High-Speed
PWM) and data sheet clarification 3 (DC Characteristics:
I/O Pin Input Specifications).
Rev H Document (10/2010)
Added revision A4 silicon information to all tables.
Updated the work arounds for silicon issue 31 (ADC).
Removed silicon issue 33 (PWM) and marked its
location as reserved.
Added silicon issues 34 (PWM) and 35 (JTAG).
Rev J Document (3/2011)
Updated silicon issue 29 (Analog Comparator).
Added silicon issues 36 (SPI) and 37 (Comparator).
Added data sheet clarification 4 ().
Rev K Document (11/2011)
Added silicon issues 38 (CPU), 39 (CPU), 40 (UART),
41 (JTAG), and 42 (PWM).
Rev L Document (5/2012)
Removed data sheet clarifications 2, 3, and 4.
Updated silicon issues 29 (Analog Comparator) and 32
(High-Speed PWM).
Added silicon issues 43 (PWM) and 44 (PWM).
DS80439M-page 18
2009-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
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Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-873-0
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2009-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80439M-page 19
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS80439M-page 20
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
2009-2013 Microchip Technology Inc.