SP5659 2·7GHz I2C Bus Low Phase Noise Synthesiser Preliminary Information Supersedes March 1996 version, DS4206-1.8 The SP5659 is a single chip frequency synthesiser designed for tuning systems up to 2·7GHz. The RF preamplifier drives a divide-by two prescaler which can be disabled for applications up to 2GHz, allowing direct interfacing with the programmable divider, resulting in a step size equal to the comparison frequency. For applications up to 2·7GHz the divide-by two is enabled to give a step size of twice the comparison frequency. The comparison frequency is obtained either from an onchip crystal controlled oscillator or from an external source. The oscillator frequency FREF or the comparison frequency FCOMP may be switched to the REF/COMP output; this feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see Fig. 5). The synthesiser is controlled via an I 2C bus and responds to one of four programmable addresses which are selected by applying a specific voltage to the Address input. This feature enables two or more synthesisers to be used in a system. The SP5659 contains four switching ports, P0-P3 and a 5-level ADC, the output of which can be read via the I 2C bus. The SP5659 also contains a varactor line disable and charge pump disable facility. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete 2·7GHz Single Chip System DS4296 - 2.0 June 1998 CHARGE PUMP 1 16 DRIVE CRYSTAL 2 15 VEE REF/COMP 3 14 RF INPUT ADDRESS 4 13 RF INPUT SDA 5 12 VCC SCL 6 11 ADC PORT P3 7 10 PORT P0 PORT P2 8 9 PORT P1 SP5659 MP16 Fig. 1 Pin connections – top view ■ ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1) ■ Pin Compatible with SP5658 (1) Normal ESD handling precautions should be observed. Optimised for Low Phase Noise APPLICATIONS ■ Satellite TV Selectable 42 prescaler ■ High IF Cable Tuning Systems Selectable Reference Division Ratio Selectable Reference/Comparison Frequency Output THERMAL DATA Selectable Charge Pump Current uJC = 41°C/W uJA = 111°C/W Varactor Drive Amplifier Disable 5-Level ADC Variable I2C BUS Address for Multi-tuner Applications ORDERING INFORMATION SP5659 KG/MP1S (Tubes) SP5659 KG/MP1T (Tape and reel) SP5659 ELECTRICAL CHARACTERISTICS TAMB = 220°C to 180°C, VCC = 14·5V to 15·5V, reference frequency = 4MHz. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Supply current, ICC Pin Min. 12 RF input voltage 13,14 RF input impedance RF input capacitance 13,14 13,14 SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Input hysteresis 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 SDA Output voltage 5 Charge Pump Output current Output leakage current Drive output current Drive saturation voltage 1 1 16 16 Typ. Max. 68 58 85 73 50 300 mA mA 5·5 1·5 10 210 10 0·8 V V µA µA µA V V External reference input frequency External reference input amplitude Crystal frequency Crystal oscillator drive level Recommended crystal series resistance Crystal oscillator negative resistance 2 2 2 2 REF/COMP output voltage, enabled 3 2 63 1 2 200 4 35 10 400 610 350 200 nA mA mV 20 500 16 MHz mVp-p MHz mVp-p Ω Ω 200 350 2 2142 240 480 7,8,9,10 See Fig. 10 See Fig. 10 Input voltage = VCC Input voltage = VEE VCC = VEE Sink current = 3mA Drive output disabled AC coupled sinewave AC coupled sinewave Parallel resonant crystal (note 2) Includes temperature and process tolerances mVp-p AC coupled, RE = 1, see note 3 MHz dBC/Hz See note 4 131071 262142 Prescaler disabled, see Table 1 Prescaler enabled, see Table 1 See Table 1 Reference division ratio P0, P1, P2, P3 sink current P0, P1, P2, P3 leakage current VCC = 5V, PE = 1 (note 1) VCC = 5V, PE = 0 0·4 Comparison frequency Equivalent phase noise at phase detector RF division ratio Conditions mVrms 300MHz to 2·7GHz, PE = 1 (prescaler enabled) see Fig. 4b mVrms 100MHz, PE = 1 (prescaler enabled) see Fig. 4b mVrms 100MHz to 2·0GHz, PE = 0 (prescaler disabled) see Fig. 4b Ω pF 50 2 3 0 Units 10 10 mA µA VPORT = 0·7V VPORT = 13·2V ADC input voltage ADC input current 11 11 610 µA See Fig. 3 Table 5 VCC >VINPUT >VEE Address input current high Address input current low 4 4 1 20·5 mA mA Input voltage = VCC Input voltage = VEE NOTES 1. Maximum power consumption is 468mW with VCC = 5·5V and all ports off. 2. Resistance specified is maximum under all conditions including start up. 3. If the REF/COMP output is not used, it should be left open circuit or connected to VCC and disabled by setting RE to logic 0. 4. 6kHz loop bandwidth, phase comparator frequency 250kHZ. Figure measured at 1kHz offset DSB (within loop bandwidth). 2 SP5659 ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V Parameter Pin Supply voltage 12 Value Units Min. Max. 20·3 7 V RF input voltage 13,14 2·5 V p-p RF input DC offset 13, 14 VCC10·3 V Port voltage Total port current 7-10 20·3 14 V Port in off state 7-10 20·3 6 V Port in on state 50 mA 7-10 ADC input DC offset 11 20·3 VCC10·3 V REF/COMP output DC offset 3 20·3 VCC10·3 V Charge pump DC offset 1 20·3 VCC10·3 V Drive DC offset 16 20·3 VCC10·3 V Crystal oscillator DC offset 2 20·3 VCC10·3 V Address DC offset 4 20·3 VCC10·3 V 5, 6 20·3 6 V 255 1150 °C 1150 °C SDA, SCL input voltage Conditions Storage temperature Junction temperature 3 PROGRAMMABLE DIVIDER PREAMP FCOMP 13 RF IN 42/1 14 13-BIT COUNT 416/17 FPD REFERENCE DIVIDER (SEE TABLE 1) PHASE COMP 2 FREF LOCK DET 4-BIT COUNT 1 16 CHARGE PUMP PE C1, C0 1-BIT COUNT 2-BIT LATCH 17-BIT LATCH DIVIDE RATIO REF/COMP OSC 2-BIT LATCH MODE CONTROL CRYSTAL CHARGE PUMP DRIVE DISABLE 5-BIT LATCH AND MODE CONTROL LOGIC (SEE TABLE 6) ADDRESS SDA SCL ADC FPD/2 4 5 I 2C TRANSCEIVER 6 11 3-BIT ADC 3 FL P0 TEST CONTROL 4-BIT LATCH AND PORT INTERFACE 12 15 VCC VEE POWER ON DETECT 7 8 9 P3 P2 P1 10 P0 Fig. 2 Block diagram 3 SP5659 FUNCTIONAL DESCRIPTION The SP5659 contains all the elements necessary – with the exception of a frequency reference, loop filter and external high voltage transistor – to control a varactor tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic which enables the generation of a loop with good phase noise performance. The block diagram is shown in Fig. 2. The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces with a 17-bit fully programmable divider via a 42 prescaler. For applications up to 2·0GHz RF input, the prescaler can be disabled, so eliminating the degradation in phase noise due to prescaler action. The divider is of MN1A architecture, where N = 16 or 17, the M counter is 13 bits and the A counter is 4 bits. The output of the programmable divider, FPD, is fed to the phase comparator where it is compared in phase and frequency domains with the comparison frequency FCOMP. This frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. In either case, the reference frequency FREF is divided down to the comparison frequency by the reference divider, which is programmable to one of 15 ratios as detailed in Table 1. The output of the phase detector feeds a charge pump and loop amplifier section which, when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. By invoking the device test modes as described in Fig. 3, Table 6, the varactor drive output can be disabled, so switching the external transistor off. This allows an external voltage to be applied to the varactor line for tuner alignment purposes. Similarly, the charge can also be disabled to a high impedance state. The programmable divider output FPD/2 can be switched to port P0 by programming the device into test mode as set out in Table 6. PROGRAMMING The SP5659 is controlled by an I2C Bus. Data and Clock are fed in on the SDA and SCL lines respectively, as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. Tables 1 and 2 in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C Bus system. Table 4 in Fig. 3 shows how the address is selected by applying a voltage to the address input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. When the device is programmed into the read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. WRITE Mode (Frequency Synthesis) With reference to Table 2, bytes 2 and 3 contain frequency information bits 214 to 20 inclusive. Auxiliary frequency bits 216 and 215 are in byte 4. For most frequencies, only bytes 2 and 3 will be required. The remainder of byte 4 and byte 5 control the prescaler enable, reference divider ratio (see Fig. 3), output ports and test modes (see Table 6). After reception and acknowledgment of a valid address (byte 1), the first bit of the following byte determines whether the byte is interpreted as byte 2 (logic ‘0’) or byte 4 (logic ‘1’); 4 the next data byte is then interpreted as byte 3 or byte 5, respectively. After two complete data bytes have been received, additional data bytes can be entered, where byte interpretation follows the same procedure without readdressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte; if, however, it occurs during a byte transmission then the previous data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 17 bits of the data have been received or after the generation of a STOP condition. Repeatedly sending bytes 2 and 3 only will not change the frequency. A frequency change when one of the following data sequences is sent to an addressed device: Bytes 2, 3, 4, 5 Bytes 4, 5, 2, 3 or when a STOP condition follows valid data bytes thus: Bytes 2, 3, 4, STOP Bytes 4, 5, 2, STOP Bytes 2, 3, STOP Bytes 2, STOP Bytes 4, STOP It should be noted that the SP5569 must be addressed initially with both frequency AND control byte data, since the control byte contains reference divider information which must be provided before a chosen frequency can be synthesised. This implies that after initial turn on, bytes 2, 3 and 4 must be sent followed by a STOP condition as a minimum requirement. Alternatively, bytes 2, 3, 4 and 5 must be sent if port information is also required. READ Mode When the device is in read mode the status byte read from the device on the SDA line takes the form shown in Fig. 3, Table 3. Bit 1 (POR) is the power-on reset indicator and is set to a logic ‘1’ if the VCC supply to the device has dropped below 3V (at 25˚C), for example, when the device is initially turned on. R3 R2 R1 R0 Ratio Comparison frequency 0 0 0 0 2 2MHz 0 0 0 1 4 1MHz 0 0 1 0 8 500kHz 0 0 1 1 16 250kHz 0 1 0 0 32 125kHz 0 1 0 1 64 62·5kHz 0 1 1 0 128 31·25kHz 0 1 1 1 256 15·625kHz 1 0 0 0 Invalid 1 0 0 1 5 800kHz 1 0 1 0 10 400kHz 1 0 1 1 20 200kHz 1 1 0 0 40 100kHz 1 1 0 1 80 50kHz 1 1 1 0 160 25kHz 1 1 1 1 320 12·5kHz Table 1 Reference division ratios (4MHz external reference) SP5659 Charge pump current The charge pump current can be programmed by bits C1 and C0 in data byte 5, as defined in Fig. 3, Table 7. Test mode The test modes are invoked by setting bit RE to logic ‘0’ and bit RTS to logic ‘1’ within the programming data and are selected by bits TS2, TS1 and TS0 as shown in Fig. 3, Table 6. When TS2, TS1 and TS0 are received, the device retains previously P2, P1 and P0 data. Reference comparison frequency output The reference frequency FREF can be switched to the REF/ COMP output (pin 3) by setting byte 5 bit RE to logic ‘1’ and bit RTS to logic ‘0’. The comparison frequency FCOMP can be switched to the REF/COMP output by setting bit RE to logic ‘1’ and bit RTS to logic ‘1’. For RE set to logic ‘0’, the output is disabled and set to a high state. RE and RTS default to logic ‘1’ during power-up, thus enabling FCOMP at the REF/COMP output. The POR is reset to 0 when the read sequence is terminated by a STOP command. When POR is set high (at low VCC), the programmed information is lost and the output ports are all set to high impedance. Bit 2 (FL) indicates whether the device is phase locked, a logic ‘1’ is present if the device is locked, and a logic ‘0’ if the device is unlocked. Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of the ADC. The ADC can be used to feed AFC information to the microprocessor via the I 2C bus. Additional Programmable Features Prescaler enable The 42 prescaler is enabled by setting bit PE in byte 4 to a logic ‘1’. A logic ‘0’ disables the prescaler, directly passing the RF input to the 17-bit counter. Bit PE is a static select only. LSB MSB Address 1 1 0 0 0 Programmable divider 0 14 13 12 11 Programmable divider 7 2 2 2 2 6 Control data 1 216 Control data C1 C0 2 5 2 2 2 4 2 215 RE RTS PE MA0 MA1 2 3 10 2 R3 2 R2 2 9 2 1 R1 0 A Byte 1 2 8 A Byte 2 2 0 A Byte 3 R0 A Byte 4 A Byte 5 P3 P2/TS2 P1/TS1 P0/TS0 Table 1 Write data format (MSB transmitted first) Address 1 1 Status byte POR FL 0 0 0 X X X MA1 MA0 A2 A1 1 A Byte 1 A0 A Byte 2 Table 3 Read data format A2 A1 A0 Voltage on ADC input 1 0 0 0·6VCC to VCC 0 1 1 0·45VCC to 0·6VCC 0 0 0V to 0·1VCC 0 1 0 0·3VCC to 0·45VCC 0 1 Open circuit 0 0 1 0·15VCC to 0·3VCC 1 0 0·4VCC to 0·6VCC 0 0 0 0V to 0·15VCC 1 1 0·9VCC to VCC MA1 MA0 Table 4 ADC levels A MA1, MA0 216-20 PE R3, R2, R1, R0 C1, C0 RE RTS TS2, TS1, TS0 P0 P3, P2, P1 POR FL A2, A1, A0 X : : : : : : : : : : : : : : : Address input voltage level Table 5 Address selection Acknowledge bit Variable address bits (see Table 5) Programmable division ratio control bits Prescaler enable Reference division ratio select (see Table 1) Charge pump current select (see Table 7) Reference oscillator output enable REF/COMP select when RE = 1, Test mode enable when RE = 0 (see Table 6) Test mode control bits (valid when RE = 0 and RTS = 1,see Table 6) Port P0 output state (always valid except when RE = 0 and RTS = 1 (see Table 6) Ports P2, P1 and P0 output states Power on reset indicator Phase lock flag ADC data (see Table 4) Don’t care Fig. 3 Data formats cont… 5 SP5659 RE RTS TS2 TS1 TS0 REF/COMP O/P mode Test mode description 0 0 X X X Disabled to high state Normal operation 0 1 X 0 0 Disabled to high state Charge pump sink, status byte FL = 1 0 1 X 0 1 Disabled to high state Charge pump source, status byte FL = 0 0 1 X 1 0 Disabled to high state Charge pump disabled, status byte FL = 0 0 1 X 1 1 Disabled to high state Port P0 = FPD/2 0 1 1 X X Disabled to high state Varactor drive output disabled 1 0 X X X FREF switched Normal operation 1 1 X X X FCOMP switched Normal operation Table 6 REF/COMP output mode and test modes Current (µA) C1 C0 byte 5, bit 1 byte 5, bit 2 Min. Typ. Max. 0 0 690 6120 6150 0 1 6195 6260 6325 1 0 6416 6555 6694 1 1 6900 61200 61500 Table 7 Charge pump current Fig. 3 Data formats (continued) 300 VIN (mV RMS INTO 50 Ω ) VIN (mV RMS INTO 50 Ω ) 300 100 OPERATING WINDOW 100 OPERATING WINDOW 40 40 10 10 100 1000 2000 3000 3500 100 300 FREQUENCY (MHz) 2000 2700 3000 FREQUENCY (MHz) Fig. 4a Prescaler disabled, PE = 0 Fig. 4 Typical input sensitivity 6 1000 Fig. 4b Prescaler enabled, PE = 1 3500 SP5659 DOUBLE CONVERSION TUNER SYSTEMS The high 2·7GHz maximum operating frequency and excellent noise characteristics of the SP5659 allow the construction of double conversion high IF tuners. A typical as shown in Fig. 5 uses the SP5659 as the first local oscillator control for full band up conversion to an IF of greater than 1GHz. The wide range of reference division ratios allows the SP5659 to be used for both the up converter local oscillator with a high phase comparison frequency (hence low phase noise) and the down converter which uses the device in a lower comparison frequency mode, which gives a fine step size. 1·6GHz 50-900MHz 38·9MHz 1650-2700MHz REFERENCE CLOCK SP8659 FIRST LO SP8659 SECOND LO Fig. 5 Example of double conversion from VHF/UHF frequencies to TV IF 1 4MHz 18p 130V 2 SP5659 3 REF 10n REF/COMP CONTROL MICRO ADDRESS 16k 15n Optional application using on-chip crystal controlled oscillator 13·3k 1 16 2 15 3 14 4 13 BCW31 2·2n 1n 1n OSCILLATOR OUTPUT 15V 5 12 6 11 ADC P3 7 10 P0 P2 8 9 P1 SCL 47k TUNER SP5659 SDA 112V 22k 68p 10n Fig. 6 Typical application APPLICATION NOTES An application note, AN168, is available for designing with synthesisers such as the SP5659. It covers aspects such as loop filter design and decoupling. The application note is published in the Mitel Semiconductor Media IC Handbook. A generic test/demonstration board has been produced, which can be used for the SP5659. A circuit diagram and layout for the board are shown in Figs. 7 and 8. The board can be used for the following purposes: (A) Measuring RF sensitivity performance (B) Indicating port function (C) Synthesising a voltage controlled oscillator (D) Testing external reference sources The programming codes relevant to these tests are given in Fig. 3. 7 SP5659 EXTERNAL REFERENCE 15V 130V 112V P2 SK2 C7 100n C6 10n (NOT FITTED, SEE NOTE 3) C8 100n C9 100n C3 68p C2 15n R8 22k R8 16k R9 47k P3 R6 13·3k X1 4MHz C1 18p 1 16 2 15 DISABLE/REF 3 14 ENABLE 4 13 DATA/SDA 5 12 CLOCK/SCL 6 11 7 10 8 9 P1 VAR GND C12 2·2n TR1 2N3904 C5 1n SK1 RFINPUT C4 1n 15V C10 1n R4 4·7k R5 4·7k R1 4·7k NOTES 1. The circuit diagram shown is designed for use with a number of synthesisers. P4 2. The LED connected to pin 11 is redundant when an SP5659 is used in this board. 3. To use an external reference, D1 capacitor C6 must be fitted and capacitor C1 removed from the board. R3 4·7k C14 100p R2 4·7k C13 100p D2 D3 D4 D5 112V C11 1n Fig. 7 Test board circuit diagram RJM51 BOTTOM SILK SCREEN COMPONENT LOCATION Fig. 8 Test board layout 8 SP5659 LOOP BANDWIDTH Assuming the phase comparator noise floor is flat regardless of sampling frequency, this means that the best performance will be achieved when the overall local oscillator to phase comparator division ratio is a minimum. The are two ways of achieving a higher phase comparator sampling frequency: Most applications for which the SP5659 is intended require a loop filter bandwidth of between 2kHz and 10kHz. Typically, the VCO phase noise will be specified at both 1kHz and 10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. The phase noise therefore depends on the synthesiser comparator noise floor rather than the VCO The 10kHz offset figure should depend on the VCO provided that the loop has been designed correctly and is not underdamped. 1. Reduce the division ratio between the reference source and the phase comparator 2. Use a higher reference source frequency The second approach may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. REFERENCE SOURCE The SP5659 offers optimal local oscillator phase noise performance when operated with a large step size. This is because the local oscillator phase noise within the loop bandwidth is: FLO Phase comparator noise floor 120log10 FCOMP DRIVING TWO SP5659s FROM A COMMON REFERENCE The REF/COMP output on pin 3 allows two synthesisers to be driven from a common reference. To do this, the first device should be programmed by setting RE = 1 and RTS = 0. The driven device should be programmed for normal operation with RE = 0 and RTS = 0. The two devices should be connected as shown in Fig. 9. where FLO is the local oscillator frequency and FCOMP is the phase comparator frequency. 4MHz 18p 1 16 1 16 2 3 15 2 15 14 3 14 13 4 12 5 6 11 6 11 7 10 7 10 8 9 8 9 4 1n SP5659 5 13 SP5659 12 Fig. 9 Two SP5659 devices using a common reference j1 j 0.5 j2 j 0.2 j5 0 0.2 0.5 1 2 5 2j 5 2j 0.2 S11:ZO = 50Ω NORMALISED TO 50Ω 2j 2 2j 0.5 2j 1 FREQUENCY MARKERS AT 100MHz, 500MHz, 1GHz AND 2·7GHz Fig. 10 Typical RF input impedance 9 SP5659 VCC VREF 1 CHARGE PUMP 500 500 13 RF INPUT RF INPUT 14 200 100 16 DRIVE OUTPUT OS (O/P DISABLE) Loop amplifier RF inputs VCC VCC 30k 3k 3k ADDRESS SCL/SDA/ADC 4 10k * ACK * ON SDA ONLY Address input SDA, SCL and ADC VCC VCC PORT 3 REF/COMP ENABLE/ DISABLE 2 CRYSTAL Reference oscillator Output ports Fig. 11 Input/output interface circuits 10 REF/COMP output SP5659 11 SP5659 PACKAGE DETAILS Dimensions are shown thus: mm (in). 9·80/10·01 (0·386/0·394) 16 SPOT REF. 0·18/0·25 (0·007/0·010) 0·25/0·51 (0·010/0·020) 5·80/6·20 3·80/4·00 ×45° (0·150/0·157) (0·228/0·244) CHAMFER REF. PIN 1 0-8° 0·35/0·49 (0·014/0·019) 0·41/1·27 (0·016/0·050) 0·69 (0·027) MAX 16 LEADS AT 1·27 (0·050) NOM SPACING 0·10/0·25 1·35/1·91 (0·004/0·010) (0·053/0·075) NOTES 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your MITEL Customer Service Centre for further information. 16-LEAD MINIATURE PLASTIC DIL - MP16 Internet: http://www.mitelsemi.com CUSTOMER SERVICE CENTRES ● FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax: (1) 64 46 06 07 ● GERMANY Munich Tel: (089) 419508-20 Fax: (089) 419508-55 ● ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993 ● JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 ● KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933 ● NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 5576/6231 ● ● ● ● SOUTH EAST ASIA Singapore Tel:(65) 333 6193 Fax: (65) 333 6192 SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 TAIWAN, ROC Taipei Tel: 886 2 25461260 Fax: 886 2 27190260 UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 726666 Fax : (01793) 518582 These are supported by Agents and Distributors in major countries worldwide. © Mitel 1998 Publication No. DS4206 Issue No. 2.0 June 1998 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. 12