MOSEL V53C832L40

MOSEL VITELIC
PRELIMINARY
V53C832L
HIGH PERFORMANCE
3.3 VOLT 256K X 32 EDO PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
30
35
40
Max. RAS Access Time, (tRAC)
30 ns
35 ns
40 ns
Max. Column Address Access Time, (tCAA)
16 ns
18 ns
20 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC)
12 ns
14 ns
15 ns
Min. Read/Write Cycle Time, (tRC)
65 ns
70 ns
75 ns
Features
Description
■ 256K x 32-bit organization
■ EDO Page Mode for a sustained data rate of
83 MHz
■ RAS access time: 30, 35, 40 ns
■ Four CAS Inputs for Byte Read and Byte Write
Control
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
■ Refresh Interval: 512 cycles/8 ms
■ Available in 100-pin PQFP and 100-pin LQFP
packages
■ Single +3.3V ± 0.3V Power Supply
■ TTL Interface
The V53C832L is a high speed 262,144 x 32 bit
high performance CMOS dynamic random access
memory. The V53C832L offers a combination of
unique features including: EDO Page Mode operation for higher sustained bandwidth with Page Mode
cycle times as short as 12ns. All inputs are TTL
compatible. Input and output capacitance is significantly lowered to increase performance and minimize loading. These features make the V53C832L
ideally suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
V53C832L Rev. 1.6 August 1999
Package Outline
Access Time (ns)
Power
Q
TQ
30
35
40
Std.
•
•
•
•
•
•
1
Temperature
Mark
Blank
V53C832L
MOSEL VITELIC
V
5
3
C
8
FAMILY
Description
Pkg.
Pin Count
PQFP
Q
100
TQFP
TQ
100
3
2
L
DEVICE
PKG
SPEED
( t RAC)
Q (PQFP)
TQ (TQFP)
TEMP.
PWR.
BLANK (0°C to 70°C)
BLANK (NORMAL)
30 (30 ns)
35 (35 ns)
40 (40 ns)
832L-01
Pin Table
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
I/O3
VSS
I/O2
I/O1
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
I/O32
I/O31
VSS
I/O30
100-Pin PQFP/TQFP
PIN CONFIGURATION
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O29
VCC
I/O28
I/O27
VSS
I/O26
I/O25
VCC
I/O16
I/O15
VSS
I/O14
I/O13
VCC
VSS
VCC
I/O12
I/O11
VSS
I/O10
I/O9
VCC
NC
CAS3
CAS1
NC
NC
OE
NC
A8
A0
A1
A2
A3
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
A4
A5
A6
A7
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O4
VCC
I/O5
I/O6
VSS
I/O7
I/O8
VCC
I/O17
I/O18
VSS
I/O19
I/O20
VCC
VCC
VSS
I/O21
I/O22
VSS
I/O23
I/O24
VCC
CAS0
CAS2
WE
NC
NC
RAS
NC
NC
V53C832L Rev. 1.6 August 1999
832H-02
2
A0–A8
Address Inputs
RAS
Row Address Strobe
CAS0
Column Address Strobe for First
Byte (I/O1–I/O8)
CAS1
Column Address Strobe for Second
Byte (I/O9–I/O16)
CAS2
Column Address Strobe for Third
Byte (I/O17–I/O24)
CAS3
Column Address Strobe for Fourth
Byte (I/O25–I/O32)
WE
Write Enable
OE
Output Enable
I/O1–I/O32
Data Input, Output
VCC
+3.3V Supply
VSS
0V Supply
NC
No Connect
V53C832L
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
TA = 25°C, VCC = 3.3V ± 0.3V, VSS = 0 V
Ambient Temperature
Under Bias ................................. –10°C to +80°C
Storage Temperature (plastic) ..... –55°C to +125°C
Voltage Relative to VSS ..................–1.0 V to +4.6V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
Symbol
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Parameter
Typ.
Max.
Unit
CIN1
Address Input
3
4
pF
CIN2
RAS, CAS, WE, OE
4
5
pF
COUT
Data Input/Output
5
7
pF
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
256K x 32
OE
WE
CAS0
CAS1
CAS2
CAS3
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
DATA I/O BUS
COLUMN DECODERS
Y0 -Y8
SENSE AMPLIFIERS
REFRESH
COUNTER
512 x 32
A1
•
•
•
A7
A8
X0 -X 8
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
9
512
MEMORY
ARRAY
512 x 512 x 32
I/O
BUFFER
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
832L-03
V53C832L Rev. 1.6 August 1999
3
V53C832L
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V, VSS = 0 V, unless otherwise specified.
V53C832L
Symbol
Parameter
Time
Min.
Typ.
Max.
Unit
Test Conditions
Notes
ILI
Input Leakage Current
(any input pin)
–10
10
µA
VSS ≤ VIN ≤ VCC
ILO
Output Leakage Current
(for High-Z State)
–10
10
µA
VSS ≤ VOUT ≤ VCC
RAS, CAS at VIH
ICC1
VCC Supply Current,
Operating
30
130
mA
tRC = tRC (min.)
35
120
40
110
4
mA
RAS, CAS at VIH
other inputs ≥ VSS
30
130
mA
tRC = tRC (min.)
2
35
120
40
110
30
120
mA
Minimum Cycle
1, 2
35
110
40
100
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
ICC4
VCC Supply Current,
EDO Page Mode Operation
1, 2
ICC5
VCC Supply Current,
Standby, Output Enabled
2.0
mA
RAS=VIH, CAS=VIL
ICC6
VCC Supply Current,
CMOS Standby
2.0
mA
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC– 0.2 V,
All other inputs ≥ VSS
VCC
Supply Voltage
3.0
3.6
V
VIL
Input Low Voltage
–1
0.8
V
3
VIH
Input High Voltage
2.4
VCC+1
V
3
VOL
Output Low Voltage
0.4
V
IOL = 2 mA
VOH
Output High Voltage
V
IOH = –2 mA
V53C832L Rev. 1.6 August 1999
3.3
2.4
4
1
V53C832L
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
30
#
Symbol
Parameter
35
40
Min. Max. Min. Max. Min. Max. Unit
1
tRAS
RAS Pulse Width
30
2
tRC
Read or Write Cycle Time
65
70
75
ns
3
tRP
RAS Precharge Time
25
25
25
ns
4
tCSH
CAS Hold Time
30
35
40
ns
5
tCAS
CAS Pulse Width
5
6
7
ns
6
tRCD
RAS to CAS Delay
15
7
tRCS
Read Command Setup Time
0
0
0
ns
8
tASR
Row Address Setup Time
0
0
0
ns
9
tRAH
Row Address Hold Time
5
6
7
ns
10
tASC
Column Address Setup Time
0
0
0
ns
11
tCAH
Column Address Hold Time
5
5
5
ns
12
tRSH (R)
RAS Hold Time (Read Cycle)
10
10
10
ns
13
tCRP
CAS to RAS Precharge Time
5
5
5
ns
14
tRCH
Read Command Hold Time
Referenced to CAS
0
0
0
ns
5
15
tRRH
Read Command Hold Time Referenced to RAS
0
0
0
ns
5
16
tROH
RAS Hold Time Referenced to OE
6
7
8
ns
17
tOAC
Access Time from OE
10
11
12
ns
12
18
tCAC
Access Time from CAS
10
11
12
ns
6,7,14
19
tRAC
Access Time from RAS
30
35
40
ns
6, 8, 9
20
tCAA
Access Time from Column Address
16
18
20
ns
6,7,10
21
tLZ
OE or CAS to Low-Z Output
0
ns
16
22
tHZ
OE or CAS to High-Z Output
0
ns
16
23
tAR
Column Address Hold Time fromRAS
26
24
tRAD
RAS to Column Address Delay Time
10
25
tRSH (W)
RAS or CAS Hold Time in Write Cycle
10
10
10
ns
26
tCWL
Write Command to CAS Lead Time
10
11
12
ns
27
tWCS
Write Command Setup Time
0
0
0
ns
28
tWCH
Write Command Hold Time
5
5
5
ns
29
tWP
Write Pulse Width
5
5
5
ns
30
tWCR
Write Command Hold Time from RAS
26
28
30
ns
31
tRWL
Write Command to RAS Lead Time
10
11
12
ns
32
tDS
Data in Setup Time
0
0
0
ns
14
33
tDH
Data in Hold Time
5
5
5
ns
14
V53C832L Rev. 1.6 August 1999
5
75K
20
35
16
75K
24
0
5
0
11
17
75K
28
0
6
28
14
40
Notes
0
6
30
17
12
ns
ns
4
ns
20
ns
11
12, 13
V53C832L
MOSEL VITELIC
AC Characteristics (Cont’d)
30
#
Symbol
Parameter
35
40
Min. Max. Min. Max. Min. Max. Unit
Notes
34
tWOH
Write to OE Hold Time
5
5
6
ns
14
35
tOED
OE to Data Delay Time
5
5
6
ns
14
36
tRWC
Read-Modify-Write Cycle Time
100
105
110
ns
37
tRRW
Read-Modify-Write Cycle
RAS Pulse Width
65
70
75
ns
38
tCWD
CAS to WE Delay
26
28
30
ns
12
39
tRWD
RAS to WE Delay in ReadModify-Write Cycle
50
54
58
ns
12
40
tCRW
CAS Pulse Width (RMW)
44
46
48
ns
41
tAWD
Col. Address to WE Delay
32
35
38
ns
42
tPC
EDO Fast Page Mode Read
or Write Cycle Time
12
14
15
ns
43
tCP
CAS Precharge Time
3
4
5
ns
44
tCAR
Column Address to RAS Setup Time
16
18
20
ns
45
tCAP
Access Time from Column Precharge
46
tDHR
Data in Hold Time Referenced to RAS
26
28
30
ns
47
tCSR
CAS Setup Time CAS- before-RASRefresh
10
10
10
ns
48
tRPC
RAS to CAS Precharge Time
0
0
0
ns
49
tCHR
CAS Hold Time CAS-before-RAS Refresh
7
8
8
ns
50
tPCM
EDO Page Mode Read-Modify-Write Cycle Time
56
58
60
ns
51
tCOH
Output Hold After CAS Low
5
5
5
ns
52
tOES
OE Low to CAS HIGH setup time
5
5
5
ns
53
tOEH
OE Hold Time from WE during Read-Modify Write
Cycle
10
10
10
ns
54
tOEP
OE High Pulse Width
10
10
10
ns
55
tT
Transition Time (Rise and Fall)
1.5
56
tREF
Refresh Interval (512 Cycles)
V53C832L Rev. 1.6 August 1999
19
50
8
6
21
1.5
50
8
23
1.5
ns
12
7
50
ns
15
8
ms
17
V53C832L
MOSEL VITELIC
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with
the output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum
of two transitions per address cycle in EDO Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL inputs and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C832L Rev. 1.6 August 1999
7
V53C832L
MOSEL VITELIC
Truth Table
Function
RAS
CAS0 CAS1 CAS2 CAS3 WE
OE
ADDRESS I/O
Notes
Standby
H
H
H
H
H
X
X
X
High-Z
Read: Double Word
L
L
L
L
L
H
L
ROW/COL
Data Out
Read: First Byte
L
L
H
H
H
H
L
ROW/COL
I/O1–I/O8 = Data Out
I/O9–I/O32 = High-Z
Read: Second Byte
L
H
L
H
H
H
L
ROW/COL
I/O1–I/O8 = High-Z
I/O9–I/O16 = Data Out
I/O17–I/O32 = High-Z
Read: Third Byte
L
H
H
L
H
H
L
ROW/COL
I/O1–I/O16 = High-Z
I/O17–I/O23 = Data Out
I/O24–I/O32 = High-Z
Read: Fourth Byte
L
H
H
H
L
H
L
ROW/COL
I/O1–I/O23 = High-Z
I/O24–I/O32 = Data Out
Write: Double Word
(Early-Write)
L
L
L
L
L
L
X
ROW/COL
Data In
Write: First Byte
(Early)
L
L
H
H
H
L
X
ROW/COL
I/O1–I/O8 = Data In
I/O9–I/O32 = X
Write: Second Byte
(Early)
L
H
L
H
H
L
X
ROW/COL
I/O1–I/O8 = X
I/O9–I/O16 = Data In
I/O17–I/O32 = X
Write: Third Byte
(Early)
L
H
H
L
H
L
X
ROW/COL
I/O1–I/O16 = X
I/O17–I/O23 = Data In
I/O24–I/O32 = X
Write: Fourth Byte
(Early)
L
H
H
H
L
L
X
ROW/COL
I/O1–I/O23 = X
I/O24–I/O32 = Data In
Read-Write
L
L
L
L
L
H→L
EDO Page-Mode Read
First Cycle
L
H→L
H→L
H→L
H→L
H
L
ROW/COL
Data Out
2
EDO Page-Mode Read
Subsequent Cycles
L
H→L
H→L
H→L
H→L
H
L
COL
Data Out
2
EDO Page-Mode Write
First Cycle
L
H→L
H→L
H→L
H→L
L
X
ROW/COL
Data In
2
EDO Page-Mode Write
Subsequent Cycles
L
H→L
H→L
H→L
H→L
L
X
COL
Data In
2
EDO Page-Mode
Read-Write
First Cycles
L
H→L
H→L
H→L
H→L
H→L
L→H ROW/COL
Data Out, Data In
2
EDO Page-Mode
Read-Write
Subsequent Cycles
L
H→L
H→L
H→L
H→L
H→L
L→H COL
Data Out, Data In
2
L→H→L
L
L
L
L
H
L
ROW/COL
Data-Out
2
L
H
H
H
H
X
X
ROW
High-Z
H→L
L
L
L
L
X
X
X
High-Z
Hidden Refresh Read
RAS-Only Refresh
CBR Refresh
L→H ROW/COL
Notes:
1. Byte Write cycles CAS0, CAS1, CAS2, or CAS3 active.
2. Byte Read cycles CAS0, CAS1, CAS2, or CAS3 active.
3. Only one of the four CAS (CAS0, CAS1, CAS2, or CAS3) must be active.
V53C832L Rev. 1.6 August 1999
8
Data Out, Data In
1,2
3
V53C832L
MOSEL VITELIC
Waveforms of Read Cycle
RAS
t AR (23)
VIH
t CSH (4)
t RCD (6)
VIL
t CRP (13)
t RAD (24)
t RAH (9)
VIH
ROW ADDRESS
VIL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
WE
t RP (3)
t RSH (R)(12)
t CAS (5)
VIH
t ASR (8)
ADDRESS
t RC (2)
VIL
t CRP (13)
CAS
CAS0-CAS3
t RAS (1)
t RRH (15)
VIH
VIL
t ROH (16)
t CAA (20)
OE
t OAC (17)
VIH
VIL
t OES (52)
I/O1-I/O32
t CAC (18)
t RAC (19)
VOH
t HZ (22)
t HZ (22)
VALID DATA-OUT
VOL
t LZ (21)
832L-04
Waveforms of Early Write Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
t AR (23)
V IH
V IL
t CSH (4)
t CRP (13)
CAS0-CAS3
t RCD (6)
t RSH (W)(25)
t CAS (5)
V IH
V IL
t CAR (44)
t CAH (11)
t RAH (9)
t ASR (8)
ADDRESS
V IH
V IL
t ASC (10)
ROW ADDRESS
COLUMN ADDRESS
t RAD (24)
WE
t CRP (13)
t CWL (26)
t WCH (28)
t WP (29)
t WCS (27)
V IH
V IL
t WCR (30)
t RWL (31)
OE
V IH
V IL
t DHR (46)
t DS (32)
I/O1-I/O32
V IH
V IL
t DH (33)
VALID DATA-IN
HIGH-Z
832L-05
Don’t Care
V53C832L Rev. 1.6 August 1999
9
Undefined
V53C832L
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
RAS
t AR (23)
V IH
t CSH (4)
t RCD (6)
t RSH (W)(12)
t CAS (5)
V IH
t CRP (13)
V IL
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RP (3)
V IL
t CRP (13)
CAS0-CAS3
t RC (2)
t RAS (1)
V IH
ROW ADDRESS
V IL
t CAR (44)
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP (29)
WE
V IH
V IL
t WOH (34)
OE
V IH
V IL
t OED (35)
I/O1-I/O32
t DH (33)
t DS (32)
V IH
VALID DATA-IN
V IL
832L-06
Waveforms of Read-Modify-Write Cycle
t RWC (36)
tRRW (37)
RAS
t RP (3)
t AR (23)
VIH
VIL
t CSH (4)
t CRP (13)
CAS
CAS0-CAS3
t RCD (6)
t RSH (W)(25)
t CRW (40)
VIH
VIL
t
t RAH (9)
VIH
ROW
ADDRESS
VIL
COLUMN
ADDRESS
t RAD (24)
t ACS
WE
OE
CAH (11)
t ASC (10)
t ASR (8)
ADDRESS
t CRP (13)
t RWD (39)
t AWD (41)
t CWD (38)
t RWL (31)
t WP (29)
VIH
VIL
t CAA (20)
t OAC (17)
VIH
t OEH (53)
VIL
t OED (35)
t CAC (18)
t RAC (19)
I/O1-I/O32
t CWL (26)
VIH
VOH
VIL
VOL
t DH (33)
t HZ (22)
t DS (32)
VALID
DATA-OUT
VALID
DATA-IN
t LZ (21)
832L-07
Don’t Care
V53C832L Rev. 1.6 August 1999
10
Undefined
V53C832L
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
RAS
V IL
t PC (42)
t CP (43)
t RAH (9)
V IH
t CSH (4)
t ASC (10)
ROW
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCS (7)
t RCS (7)
t RCH (14)
V IH
V IL
t CAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
t RRH (15)
t OAC (17)
t OES (52)
V IH
V IL
t RAC (19)
t CAC (18)
t LZ (21)
t OEP (54)
t CAC (18)
t CAC (18)
t COH (5)
I/O1-I/O32
t CAR (44)
t ASC (10)
t CAH (11)
t RCS (7)
OE
t CRP (13)
t CAS (5)
t CAS (5)
V IL
V IL
WE
t RSH (R)(12)
t CAS (5)
V IH
t ASR (8)
ADDRESS
RP (3)
t RCD (6)
t CRP (13)
CAS0-CAS3
t
t RAS (1)
t AR (23)
V IH
V OH
t HZ (22)
VALID
DATA OUT
V OL
t HZ (22)
t HZ (22)
t HZ (22)
VALID
DATA OUT
VALID
DATA OUT
t LZ
832L-08
Waveforms of EDO Page Mode Write Cycle
t RP (3)
t AR (23)
RAS
V IL
t CRP (13)
t RCD (6)
CAS0-CAS3
t RAS (1)
V IH
t PC (42)
t CP (43)
t CAS (5)
V IH
t CSH (4)
t ASC (10)
t ASR (8)
V IH
ROW
ADD
V IL
COLUMN
ADDRESS
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28)
t RWL (31)
t WCH (28)
t WP (29)
t WP (29)
V IH
V IL
VIH
V IL
t DH (33)
t DS (32)
I/O1-I/O32
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WP (29)
OE
t CRP (13)
t CAR (44)
t ASC (10)
t CAH (11)
t RAD (24)
WE
t CAS (5)
t CAS (5)
V IL
t RAH (9)
ADDRESS
t RSH (W)(25)
V IH
V IL
VALID
DATA IN
t DS (32)
t DH (33)
VALID
DATA IN
OPEN
t DS (32)
t DH (33)
VALID
DATA IN
OPEN
832L-09
Don’t Care
V53C832L Rev. 1.6 August 1999
11
Undefined
V53C832L
MOSEL VITELIC
Waveforms of EDO Page Mode Read-Write Cycle
t RAS (1)
VIH
RAS
V
IL
t CSH (4)
t RCD (6)
t PCM (50)
IH
V
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP (43)
t CAS (5)
V
CAS0-CAS3
t RP (3)
t CAS (5)
t RAD (24)
IL
t RAH (9)
t ASC (10)
t ASR (8)
V
IH
ADDRESS
V
IL
ROW
ADD
t ASC (10)
t CAH (11)
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RWD (39)
t CWL (26)
t CWD (38)
t CAR (44)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CWD (38)
t CWD (38)
t RWL (31)
t CWL (26)
t CWL (26)
V
IH
WE
V
IL
t CAA (20)
t OAC (17)
t AWD (41)
t AWD (41)
t AWD (41)
t WP (29)
t WP (29)
t WP (29)
t OAC (17)
t OAC (17)
V
IH
OE
V
t OEH (53)
IL
t CAA (20)
t OED (35)
t CAC (18)
t RAC (19)
t CAP (43)
t CAP (43)
t CAA (20)
t OED (35)
t CAC (18)
t HZ (22)
t HZ (22)
t DH (33)
t DH (33)
t DS (32)
t DS (32)
I/O1-I/O32
V I/OH
OUT
V I/OL
OUT
IN
t OED (35)
t CAC (18)
t HZ (22)
t DH (33)
t DS (32)
OUT
IN
IN
832L-10
t LZ (21)
t LZ
t LZ
Waveforms of RAS-Only Refresh Cycle
tRC (2)
RAS
t RAS (1)
VIH
tRP (3)
V IL
t CRP (13)
CAS0-CAS3
VIH
V IL
tASR (8)
ADDRESS
VIH
V IL
t RAH (9)
ROW ADD
832L-11
NOTE: WE, OE = Don’t care
Don’t Care
V53C832L Rev. 1.6 August 1999
12
Undefined
V53C832L
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
t RP (3)
V IH
V IL
t CSR (47)
CAS0-CAS3
ADDRESS
t CHR (49)
t RSH (W)(25)
t CAS (5)
t CP (43)
V IH
V IL
V IH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
V IH
V IL
t ROH (16)
t OAC (17)
OE
V IH
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O1-I/O32
V IH
DOUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
WE
OE
V IL
V IH
V IL
t
I/O1-I/O32
t WCH (28)
t WCS (27)
V IH
t DH (33)
DS (32)
V IH
D IN
V IL
832L-12
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2)
t RP (3)
RAS
V IL
t CP (43)
CAS0-CAS3
t RAS (1)
t RP (3)
V IH
t RPC (48)
t CHR (49)
t CSR (47)
V IH
V IL
t HZ (22)
I/O1-I/O32
V OH
V OL
832L-13
NOTE: WE, OE, A0–A8 = Don’t care
Don’t Care
V53C832L Rev. 1.6 August 1999
13
Undefined
V53C832L
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2)
RAS
V IH
t RSH (R)(12)
t CRP (13)
V IL
V IH
t RAD (24)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
t RCS (7)
WE
t CHR (49)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RP (3)
t RAS (1)
V IL
t RCD (6)
t CRP (13)
CAS0-CAS3
t RC (2)
tRP (3)
t RAS (1)
t AR (23)
t RRH (15)
V IH
V IL
t CAA (20)
t OAC (17)
OE
V IH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
I/O1-I/O32
t HZ (22)
t HZ (22)
V OH
VALID DATA
V OL
832L-14
Waveforms of Hidden Refresh Cycle (Write)
t RC (2)
RAS
V IH
t RSH (12)
V IH
t CAH (11)
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
V IH
V IL
V IH
V IL
t DS (32)
I/O1-I/O32
t CRP (13)
t RAD (24)
t ASC (10)
t WCS (27)
OE
t CHR (49)
V IL
V IL
WE
t RP (3)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RAS (1)
V IL
t RCD (6)
t CRP (13)
CAS0-CAS3
t RC (2)
t RP (3)
t RAS (1)
t AR (23)
V IH
V IL
t DH (33)
VALID DATA-IN
t DHR (46)
832L-15
Don’t Care
V53C832L Rev. 1.6 August 1999
14
Undefined
V53C832L
MOSEL VITELIC
Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
tRAS
tRP
V IH
RAS
V IL
tCSH
tCRP
CAS0-CAS3
tPC
tRCD
tPC
tCAS
tCP
tCAS
tRSH
tCP
tCAS
tCP
V IH
V IL
tAR
tCAR
tRAD
tASR
ADDRESS
V IH
V IL
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
COLUMN
ADDRESS
COLUMN
ADDRESS
tWCS
tWCH
tCAA
tCAA
tCAP
tCAC
tCAC
V IH
V IL
tCAH
tRCH
tRAC
OE
tASC
COLUMN
ADDRESS
tRCS
V IH
WE
V IL
tCAH
tDS
tDH
tOE
tCOH
I/O1-I/O32
VOH
VOL
VALID
DATA OUT
VALID
DATA OUT
VALID
DATA IN
832L-16
Don’t Care
Undefined
Functional Description
Read Cycle
The V53C832L is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C832L reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address.
The V53C832L has four CAS inputs. CAS0 controls I/O1–I/O8; CAS1 controls I/O9–I/O16; CAS2
controls I/O 17 –I/O 24 ; and CAS3 controls I/O 23 –
I/O 32 . These four CAS inputs control Byte Read and
Byte Write.
The row address is latched by the Row Address
Strobe (RAS). The column address “flows through”
an internal address buffer and is latched by the
Column Address Strobe (CAS). Because access
time is primarily dependent on a valid column
address rather than the precise time that the CAS
edge occurs, the delay time from RAS to CAS has
little effect on the access time.
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS
operation. The column address must be held for a
minimum specified by tAR. Data Out becomes valid
only when tOAC, tRAC, tCAA and tCAC are all satisifed.
As a result, the access time is dependent on the
timing relationships between these parameters. For
example, the access time is limited by tCAA when
tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS
low during a RAS operation. The column address is
latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE
or CAS falls later. Consequently, the input data must
be valid at or before the falling edge of WE or CAS,
whichever occurs last. In the CAS-controlled Write
Cycle, when the leading edge of WE occurs prior to
the CAS low transition, the I/O data pins will be in the
High-Z state at the beginning of the Write function.
Ending the Write with RAS or CAS will maintain the
output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum tRAS time has
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
V53C832L Rev. 1.6 August 1999
15
V53C832L
MOSEL VITELIC
Extended Data Output Page Mode
EDO Page operation permits all 512 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the
falling edge of CAS, eliminating tASC and tT from the
critical timing path. CAS latches the address into the
column address buffer. During EDO operation,
Read, Write, Read-Modify-Write or Read-WriteRead cycles are possible at random addresses within a row. Following the initial entry cycle into Hyper
Page Mode, access is tCAA or tCAP controlled. If the
column address is valid prior to the rising edge of
CAS, the access time is referenced to the CAS rising
edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is
timed from the occurrence of a valid address and is
specified by tCAA. In both cases, the falling edge of
CAS latches the address and enables the output.
EDO provides a sustained data rate of 83 MHz for
applications that require high bandwidth such as bitmapped graphics or high-speed signal processing.
The following equation can be used to calculate the
maximum data rate:
OE signal has no effect on any data stored in the
output latches. A WE low level can also disable the
output drivers when CAS is low. During a Write
cycle, if WE goes low at a time in relationship to CAS
that would normally cause the outputs to be active,
it is necessary to use OE to disable the output
drivers prior to the WE low transition to allow Data In
Setup Time (tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C832L is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and ICC will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
Table 1. V53C832L Data Output
Operation for Various Cycle Types
512
Data Rate = ---------------------------------------t RC + 511 × t PC
Data Output Operation
The V53C832L Input/Output is controlled by OE,
CAS, WE and RAS. A RAS low transition enables
the transfer of data to and from the selected row
address in the Memory Array. A RAS high transition
disables data transfer and latches the output data if
the output is enabled. After a memory cycle is
initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level
disables the I/O path and the output driver if it is
enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output
drivers. The output drivers, when otherwise
enabled, can be disabled by holding OE high. The
V53C832L Rev. 1.6 August 1999
16
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
EDO Read Cycle
Data from Addressed
Memory Cell
EDO Write Cycle
(Early Write)
High-Z
EDO Read-Modify-Write
Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C832L
MOSEL VITELIC
Package Outlines
100-pin PQFP
FOOTPRINT 3.2mm (14x20mm)
0.134 MAX.
[3.404 MAX.]
TOP VIEW
0.026 TYP.
[0.65 TYP.]
Unit in inches [mm]
0.010 MIN.
[0.254 MIN.]
81
100
1
80
0.012
0.787±0.004
[19.990±0.102]
+0.003
–0.002
[0.305
+0.076
]
–0.051
+0.008
–0.007
+0.203
[23.190
]
–0.178
0.913
30
51
31
50
0.551±0.004
[13.995±0.102]
0.113 MAX
[2.87 MAX]
0.677±0.008
[17.195±0.203]
DETAIL “F”
0.004 MIN.
[0.102 MIN.]
GAGE PLANE
SEATING PLANE
0.035 ±0.006
[0.889 ±0.152]
SEE DETAIL “F”
0.063 TYP.
[1.600 TYP.]
100-pin TQFP
Dimensions in Millimeters
17.2 ±
0.25
14.00 ±
Pin #1 Index
0.20
#100
#1
23.2 ±
0.25
20.00 ±
A
0.30 ±
0.15 ±
0.65
0.08
1.00 ±
1.20 MAX
0.05
GAGE PLANE
0.80 ±
0.10 ± 0.05
1.60
REF
SECTION: A-A
V53C832L Rev. 1.6 August 1999
17
0.20
A
0.15
0.05
MOSEL VITELIC
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V53C832L
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