MOSEL V53C8128H50

MOSEL-VITELIC
V53C8128H
PRELIMINARY
V53C8128H
ULTRA-HIGH PERFORMANCE,
128K X 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
35
40
45
50
Max. RAS Access Time, (tRAC)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (tCAA)
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode With EDO Cycle Time, (tPC)
14 ns
15 ns
17 ns
19 ns
Min. Read/Write Cycle Time, (tRC)
70 ns
75 ns
80 ns
90 ns
Features
Description
■ 128K x 8-bit organization
■ RAS access time: 35, 40, 45, 50 ns
■ EDO Page Mode supports sustained I/O data
rates up to 71.5 MHz
■ Low power dissipation
• V53C8128H-50
— Operating Current – 135 mA max
— TTL Standby Current – 2.0 mA max
■ Low CMOS Standby Current
• V53C8128H – 1.0 mA max
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
■ Refresh Interval
• V53C8128H – 512 cycles/8 ms
■ Available in 26/24 pin 300 mil SOJ package
The V53C8128H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8128H offers a combination of features: EDO
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with extended data out operation allows random
access of up to 256 columns (x8) bits within a row
with cycle times as short as 14 ns. Because of static
circuitry, the CAS clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements for fast usable speed.
These features make the V53C8128H ideally suited
for graphics, digital signal processing and high
performance Peripherals.
Device Usage Chart
Operating
Temperature
Range
Package Outline
K
35
40
45
50
Std.
0°C to 70 °C
•
•
•
•
•
•
V53C8128H Rev. 1.1 November 1997
Access Time (ns)
1
Power
Temperature
Mark
Blank
V53C8128H
MOSEL-VITELIC
V
5
3
C
8
1
FAMILY
2
8
H
DEVICE
PKG
SPEED
( t RAC)
TEMP.
PWR.
Description
SOJ
Pkg.
Pin Count
K
26/24
35
40
45
50
RAS
A0
A1
A2
A3
VCC
8
9
10
11
12
13
300 mil
1
2
3
4
5
6
26
25
24
23
22
21
V SS
I/O8
I/O7
I/O6
I/O5
CAS
19
18
17
16
15
14
OE
A8
A7
A6
A5
A4
(35 ns)
(40 ns)
(45 ns)
(50 ns)
3838 01
Pin Names
26/24 Lead SOJ
PIN CONFIGURATION
Top View
VSS
I/O1
I/O2
I/O3
I/O4
WE
BLANK (0°C to 70°C)
BLANK (NORMAL)
K (SOJ)
A0–A8
Address Inputs (A8: Row
Address only)
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O1–I/O8
Data Input, Output
VCC
+5V Supply
VSS
0V Supply
3838 02
Absolute Maximum Ratings*
Capacitance*
Ambient Temperature
Under Bias ............................. –10°C to +80°C
Storage Temperature (plastic) .... –55°C to +125°C
Voltage Relative to VSS .................... –1.0 V to +7.0 V
Data Output Current .................................... 50 mA
Power Dissipation ......................................... 1.0 W
TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V
Symbol
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
V53C8128H Rev. 1.1 November 1997
Parameter
Typ. Max.
CIN1
Address Input
3
4
pF
CIN2
RAS, CAS, WE, OE
4
5
pF
COUT
Data Input/Output
5
7
pF
* Note: Capacitance is sampled and not 100% tested
2
Unit
V53C8128H
MOSEL-VITELIC
Block Diagram
128K x 8
OE
WE
CAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
I/O 1
DATA I/O BUS
I/O2
COLUMN DECODERS
Y0–Y7
I/O3
I/O
BUFFER
I/O4
I/O 5
SENSE AMPLIFIERS
I/O6
REFRESH
COUNTER
I/O7
I/O8
256 x 8
A1
•
•
•
A7
A8
V53C8128H Rev. 1.1 November 1997
X0–X8
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
9
512
MEMORY
ARRAY
3838 03
3
V53C8128H
MOSEL-VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
V53C8128H
Access
Time Min. Typ. Max.
Unit
Test Conditions
ILI
Input Leakage Current
(any input pin)
–10
10
µA
VSS ≤ VIN ≤ VCC
ILO
Output Leakage Current
–10
10
µA
VSS≤ VOUT ≤ VCC
RAS, CAS at VIH
(for High-Z State)
ICC1
VCC Supply Current,
Operating
ICC2
ICC3
ICC4
35
160
40
150
45
145
50
135
VCC Supply Current,
TTL Standby
VCC Supply Current,
RAS-Only Refresh
VCC Supply Current,
EDO Page Mode
Operation
ICC5
VCC Supply Current,
Standby, Output Enabled
ICC6
VCC Supply Current,
CMOS Standby
Notes
mA
tRC = tRC (min.)
mA
RAS, CAS at VIH
other inputs ≥ VSS
mA
tRC = tRC (min.)
2
mA
Minimum cycle
1, 2
2
mA
RAS=VIH, CAS=VIL
other inputs ≥ VSS
1
mA
4
35
160
40
150
45
145
50
135
35
95
40
90
45
85
50
80
1, 2
1
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC – 0.2 V,
All other inputs ≥ VSS
VIL
Input Low Voltage
–1
0.8
V
3
VIH
Input High Voltage
2.4
VCC+1
V
3
VOL
Output Low Voltage
0.4
V
IOL = 4.2 mA
VOH
Output High Voltage
V
IOH = –5 mA
V53C8128H Rev. 1.1 November 1997
2.4
4
V53C8128H
MOSEL-VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
35
40
45
50
#
JEDEC
Symbol
Symbol
Parameter
1
tRL1RH1
tRAS
RAS Pulse Width
35
2
tRL2RL2
tRC
Read or Write Cycle Time
70
75
80
90
ns
3
tRH2RL2
tRP
RAS Precharge Time
25
25
25
30
ns
4
tRL1CH1
tCSH
CAS Hold Time
35
40
45
50
ns
5
tCL1CH1
tCAS
CAS Pulse Width
7
8
9
9
ns
6
tRL1CL1
tRCD
RAS to CAS Delay
16
7
tWH2CL2
tRCS
Read Command Setup Time
0
0
0
0
ns
8
tAVRL2
tASR
Row Address Setup Time
0
0
0
0
ns
9
tRL1AX
tRAH
Row Address Hold Time
6
7
8
9
ns
10
tAVCL2
tASC
Column Address Setup Time
0
0
0
0
ns
11
tCL1AX
tCAH
Column Address Hold Time
4
5
6
7
ns
12
tCL1RH1(R) tRSH (R)
RAS Hold Time (Read Cycle)
14
14
15
15
ns
13
tCH2RL2
tCRP
CAS to RAS Precharge Time
5
5
5
5
ns
14
tCH2WX
tRCH
Read Command Hold Time
Referenced to CAS
0
0
0
0
ns
5
15
tRH2WX
tRRH
Read Command Hold Time
Referenced to RAS
0
0
0
0
ns
5
16
tOEL1RH2
tROH
RAS Hold Time
Referenced to OE
8
8
9
10
ns
17
tGL1QV
tOAC
Access Time from OE
12
12
13
14
ns
18
tCL1QV
tCAC
Access Time from CAS (EDO)
12
12
13
14
ns
6, 7
19
tRL1QV
tRAC
Access Time from RAS
35
40
45
50
ns
6, 8, 9
20
tAVQV
tCAA
Access Time from Column
Address
18
20
22
24
ns
6, 7, 10
21
tCL1QX
tLZ
CAS to Low-Z Output
0
ns
16
22
tCH2QZ
tHZ
Output buffer turn-off delay time
0
ns
16
23
tRL1AX
tAR
Column Address Hold Time
from RAS
28
24
tRL1AV
tRAD
RAS to Column Address
Delay Time
11
25
tCL1RH1(W) tRSH (W)
RAS or CAS Hold Time
in Write Cycle
12
12
13
14
ns
26
tWL1CH1
Write Command to CAS
Lead Time
12
12
13
14
ns
tCWL
V53C8128H Rev. 1.1 November 1997
Min. Max. Min. Max. Min. Max. Min. Max. Unit
5
75K
23
40
17
75K
28
0
6
0
12
18
75K
32
0
6
30
17
45
0
13
19
75K
36
0
7
35
20
50
0
8
40
23
14
Notes
ns
ns
4
ns
26
ns
11
V53C8128H
MOSEL-VITELIC
AC Characteristics (continued)
35
40
45
50
#
JEDEC
Symbol
Symbol
Parameter
27
tWL1CL2
tWCS
Write Command Setup Time
0
0
0
0
ns
28
tCL1WH1
tWCH
Write Command Hold Time
5
5
6
7
ns
29
tWL1WH1
tWP
Write Pulse Width
5
5
6
7
ns
30
tRL1WH1
tWCR
Write Command Hold Time
from RAS
28
30
35
40
ns
31
tWL1RH1
tRWL
Write Command to RAS
Lead Time
12
12
13
14
ns
32
tDVWL2
tDS
Data in Setup Time
0
0
0
0
ns
14
33
tWL1DX
tDH
Data in Hold Time
4
5
6
7
ns
14
34
tWL1GL2
tWOH
Write to OE Hold Time
5
6
7
8
ns
14
35
tGH2DX
tOED
OE to Data Delay Time
5
6
7
8
ns
14
36
tRL2RL2
tRWC
Read-Modify-Write
Cycle Time
105
110
115
130
ns
tRRW
Read-Modify-Write Cycle
RAS Pulse Width
70
75
80
87
ns
(RMW)
37
tRL1RH1
(RMW)
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Notes
12, 13
38
tCL1WL2
tCWD
CAS to WE Delay
28
30
32
34
ns
12
39
tRL1WL2
tRWD
RAS to WE Delay in
Read-Modify-Write Cycle
54
58
62
68
ns
12
40
tCL1CH1
tCRW
CAS Pulse Width (RMW)
46
48
50
52
ns
41
tAVWL2
tAWD
Col. Address to WE Delay
35
38
41
42
ns
42
tCL2CL2
tPC
EDO Page Mode
Read or Write Cycle Time
14
15
17
19
ns
43
tCH2CL2
tCP
CAS Precharge Time
4
5
6
7
ns
44
tAVRH1
tCAR
Column Address to RAS
Setup Time
18
20
22
24
ns
45
tCH2QV
tCAP
Access Time from
Column Precharge
46
tRL1DX
tDHR
Data in Hold Time
Referenced to RAS
28
30
35
40
ns
47
tCL1RL2
tCSR
CAS Setup Time
CAS-before-RAS Refresh
10
10
10
10
ns
48
tRH2CL2
tRPC
RAS to CAS Precharge Time
0
0
0
0
ns
49
tRL1CH1
tCHR
CAS Hold Time
CAS-before-RAS Refresh
8
8
10
12
ns
50
tCL2CL2
(RMW)
tPCM
EDO Page Mode ReadModify-Write Cycle Time
58
60
65
70
ns
V53C8128H Rev. 1.1 November 1997
21
6
23
25
27
ns
12
7
V53C8128H
MOSEL-VITELIC
AC Characteristics (continued)
35
40
45
#
JEDEC
Symbol
Symbol
Parameter
51
tT
tT
Transition Time (Rise and Fall)
52
tREF
Refresh Interval (512 Cycles)
8
8
53
tCOH
Output Hold After CAS Low
5
5
V53C8128H Rev. 1.1 November 1997
50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
3
7
50
3
50
3
50
3
50
ns
8
8
ms
5
5
ns
Notes
15
V53C8128H
MOSEL-VITELIC
Notes:
1.
ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2.
ICC is dependent upon the number of address transitions. Specified IDD (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3.
Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period not
to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VDD.
4.
tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.)
can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5.
Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6.
Measured with a load equivalent to two TTL inputs and 50 pF.
7.
Access time is determined by the longest of tCAA, tCAC and tCAP.
8.
Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds
tRAD (max.).
9.
Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds
tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C8128H Rev. 1.1 November 1997
8
V53C8128H
MOSEL-VITELIC
Waveforms of Read Cycle
t AR (23)
VIH
RAS
t RAS (1)
t RC (2)
t RP (3)
VIL
t CRP (13)
t CSH (4)
t RCD (6)
t RSH (R)(12)
t CAS (5)
VIH
CAS
VIL
t RAD (24)
t RAH (9)
t ASR (8)
VIH
ADDRESS
t CRP (13)
ROW ADDRESS
VIL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
t RRH (15)
VIH
WE
VIL
t ROH (16)
t HZ (22)
t CAA (20)
t OAC (17)
VIH
OE
VIL
t CAC (18)
t RAC (19)
t HZ (22)
VOH
I/O
t HZ (22)
VALID DATA-OUT
VOL
2736 05
t LZ (21)
Waveforms of Early Write Cycle
RAS
t AR (23)
V IH
t CSH (4)
t RCD (6)
t RAH (9)
V IH
ROW ADDRESS
V IL
t WSR
t ASC (10)
t RWH
V IH
t CWL (26)
t WCH (28)
t WP (29)
t WCS (27)
V IL
t RWL (31)
V IH
V IL
t DS (32)
I/O
t CAR (44)
t CAH (11)
COLUMN ADDRESS
t WCR (30)
OE
t CRP (13)
V IL
t RAD (24)
WE
t RSH (W)(25)
t CAS (5)
V IH
t ASR (8)
ADDRESS
t RP (3)
V IL
t CRP (13)
CAS
t RC (2)
t RAS (1)
V IH
V IL
t DHR (46)
t DH (33)
VALID DATA-IN
HIGH-Z
2736 06
V53C8128H Rev. 1.1 November 1997
9
V53C8128H
MOSEL-VITELIC
Waveforms of OE-Controlled Write Cycle
RAS
t AR (23)
V IH
t CSH (4)
t RCD (6)
t RSH (W)(12)
t CAS (5)
V IH
t CRP (13)
V IL
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RP (3)
V IL
t CRP (13)
CAS
t RC (2)
t RAS (1)
V IH
ROW ADDRESS
V IL
t CAR (44)
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP (29)
WE
V IH
V IL
t WOH (34)
OE
V IH
V IL
t OED (35)
I/O
t DH (33)
t DS (32)
V IH
VALID DATA-IN
V IL
2736 07
Waveforms of Read-Modify-Write Cycle
RAS
t AR (23)
VIH
t CSH (4)
t RCD (6)
t RP (3)
t RSH (W)(25)
t CRW (40)
VIH
t CRP (13)
VIL
t
t RAH (9)
t ASC (10)
t ASR (8)
ADDRESS
t RWC (36)
VIL
t CRP (13)
CAS
tRRW (37)
VIH
ROW
ADDRESS
VIL
CAH (11)
COLUMN
ADDRESS
t AWD (41)
t CWD (38)
t RAD (24)
t RWL (31)
t RWD (39)
t WP (29)
t RCS (17)
WE
t CWL (26)
VIH
VIL
t CAA (20)
t OAC (17)
OE
VIH
VIL
t OED (35)
t CAC (18)
t RAC (19)
I/O
VIH
VOH
VIL
VOL
t HZ (22)
VALID
DATA-OUT
t LZ (21)
V53C8128H Rev. 1.1 November 1997
t DH (33)
t DS (32)
VALID
DATA-IN
2736 08
10
V53C8128H
MOSEL-VITELIC
Waveforms of EDO Page Mode Read Cycle
V IH
RAS
RP (3)
t RCD (6)
V IL
t PC (42)
t CP (43)
t CRP (13)
t RSH (R)(12)
t CAS (5)
V IH
CAS
t
t RAS (1)
t AR (23)
t CRP (13)
t CAS (5)
t CAS (5)
V IL
t RAH (9)
t ASR (8)
V IH
ADDRESS
t CSH (4)
t ASC (10)
ROW
ADDRESS
V IL
t CAR (44)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t RCS (7)
t CAH (11)
COLUMN
ADDRESS
t RCS (7)
t RCS (7)
t RCH (14)
V IH
WE
V IL
t CAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
t RRH (15)
t OAC (17)
V IH
OE
V IL
t RAC (19)
t CAC (18)
t LZ (21)
t CAC (18)
t CAC (18)
t COH
V OH
I/O
t HZ (22)
VALID
DATA OUT
V OL
VALID
DATA OUT
VALID
DATA OUT
2736 09
t LZ
Waveforms of EDO Page Mode Write Cycle
t RP (3)
t AR (23)
RAS
t HZ (22)
t HZ (22)
t HZ (22)
t RAS (1)
V IH
V IL
t CRP (13)
t RCD (6)
CAS
t PC (42)
t CP (43)
t CAS (5)
V IH
t RSH (W)(25)
t CAS (5)
t CAS (5)
t CRP (13)
V IL
t CSH (4)
t RAH (9)
t ASC (10)
t ASR (8)
ADDRESS
V IH
ROW
ADD
V IL
t CAH (11)
COLUMN
ADDRESS
t RAD (24)
t WCS (27)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCH (28)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCS (27)
t CWL (26)
t WCH (28)
t RWL (31)
t WCH (28)
t WP (29)
t WP (29)
t WP (29)
WE
t CAR (44)
t ASC (10)
V IH
V IL
OE
VIH
V IL
t DH (33)
t DS (32)
I/O
V IH
V IL
V53C8128H Rev. 1.1 November 1997
VALID
DATA IN
t DS (32)
t DH (33)
VALID
DATA IN
OPEN
t DS (32)
t DH (33)
VALID
DATA IN
OPEN
2736 10
11
V53C8128H
MOSEL-VITELIC
Waveforms of EDO Page Mode Read-Write Cycle
t RAS (1)
VIH
RAS
V
IL
t CSH (4)
t RCD (6)
t PCM (50)
IH
t CAS (5)
t RAD (24)
V
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP (43)
t CAS (5)
V
CAS
t RP (3)
IL
t RAH (9)
t ASC (10)
t ASR (8)
V
IH
ADDRESS
ROW
ADD
V
IL
t ASC (10)
t CAH (11)
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RWD (39)
t RCS (7)
t CWL (26)
t CWD (38)
t CAR (44)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CWD (38)
t CWD (38)
t RWL (31)
t CWL (26)
t CWL (26)
V
IH
WE
V
IL
t CAA (20)
t OAC (17)
t WSR
t AWD (41)
t AWD (41)
t AWD (41)
t WP (29)
t WP (29)
t WP (29)
t OAC (17)
t OAC (17)
V
IH
OE
V
IL
t EMS
t EMH
t CAA (20)
t OED (35)
t CAC (18)
t RAC (19)
t CAP (43)
t CAP (43)
t CAA (20)
t OED (35)
t CAC (18)
t HZ (22)
t HZ (22)
t DH (33)
t DH (33)
t DS (32)
t DS (32)
I/O
V I/OH
OUT
V I/OL
OUT
IN
t OED (35)
t CAC (18)
t HZ (22)
t DH (33)
t DS (32)
OUT
IN
IN
2736 11
t LZ (21)
t LZ
t LZ
Waveforms of RAS-Only Refresh Cycle
t RC (2)
RAS
t RAS (1)
V IH
t RP (3)
V IL
t CRP (13)
CAS
V IH
V IL
t ASR (8)
ADDRESS
V IH
t RAH (9)
ROW ADD
V IL
2736 12
NOTE:
WE, OE = Don’t care
V53C8128H Rev. 1.1 November 1997
12
V53C8128H
MOSEL-VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
t RP (3)
V IH
V IL
t CSR (47)
t CHR (49)
t RSH (W)(25)
t CAS (5)
t CP (43)
V IH
CAS
V IL
ADDRESS
V IH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
V IH
V IL
t ROH (16)
t OAC (17)
V IH
OE
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O
V IH
DOUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
t WCH (28)
t WCS (27)
WE
t HZ (22)
V IH
V IL
OE
V IH
V IL
t
I/O
t DH (33)
DS (32)
V IH
D IN
V IL
2736 13
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2)
t RP (3)
RAS
V IL
t CP (43)
CAS
t RAS (1)
t RP (3)
V IH
t RPC (48)
t CSR (47)
t CHR (49)
V IH
V IL
t HZ (22)
I/O
V OH
V OL
2736 14
NOTE: WE, OE, A 0 –A 78 = Don’t care
V53C8128H Rev. 1.1 November 1997
13
V53C8128H
MOSEL-VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2)
RAS
V IH
t RC (2)
tRP (3)
t RAS (1)
t AR (23)
t RAS (1)
t RP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t CRP (13)
V IL
V IH
t RAD (24)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
t RCS (7)
WE
t CHR (49)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RSH (R)(12)
t RRH (15)
V IH
V IL
t CAA (20)
OE
t HZ (22)
t OAC (17)
V IH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
I/O
t HZ (22)
V OH
t HZ (22)
VALID DATA
V OL
2736 15
Waveforms of Hidden Refresh Cycle (Write)
t RC (2)
RAS
V IH
t RC (2)
t RAS (1)
t RP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t RP (3)
t RAS (1)
t AR (23)
t RSH (12)
t CHR (49)
t CRP (13)
V IH
V IL
t RAD (24)
t ASC (10)
t ASR (8)
t RAH (9)
ADDRESS
V IH
V IL
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
t WCS (27)
WE
t CAH (11)
V IH
V IL
V IH
OE
V IL
t DS (32)
I/O
V IH
V IL
t DH (33)
VALID DATA-IN
2736 16
t DHR (46)
V53C8128H Rev. 1.1 November 1997
14
V53C8128H
MOSEL-VITELIC
Functional Description
Write Cycle
The V53C8128H is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C8128H reads and writes
data by multiplexing an 17-bit address into a 9-bit
row and an 8-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column
address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum tRAS time has
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
Refresh Cycle
To retain data, 512 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 512 row addresses (A0
through A8) with RAS at least once every 8 ms.
Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row.
2. Using a CAS-before-RAS Refresh Cycle. If CAS
makes a transition from low to high to low after
the previous cycle and before RAS falls, CASbefore-RAS refresh is activated. The
V53C8128H uses the output of an internal 9-bit
counter as the source of row addresses and
ignore external address inputs.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS
operation. The column address must be held for a
minimum specified by tAR. Data Out becomes valid
only when tOAC, tRAC, tCAA and tCAC are all satisifed.
As a result, the access time is dependent on the
timing relationships between these parameters. For
example, the access time is limited by tCAA when
tRAC, tCAC and tOAC are all satisfied.
V53C8128H Rev. 1.1 November 1997
CAS-before-RAS is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the
cycle. A CAS-before-RAS counter test mode is
provided to ensure reliable operation of the internal
refresh counter.
15
V53C8128H
MOSEL-VITELIC
Extended Data Out Page Mode
Power-On
The V53C8128H offers fast access within a row.
Unlike ordinary fast page mode DRAM, the
V53C8128H output remains active and valid even
after CAS goes high and it will stay valid for 5ns after
CAS changes low. The feature allows the
V53C8128H to CAS cycle faster than ordinary page
mode DRAM since the cycle time be short as data
access time.
The outputs are disabled at the tHZ time after RAS
and CAS are high. The tHZ time is referenced from
rising edge of RAS or CAS whichever occurs last. In
addition, high on OE input and activation of the writecycle will also disable the outputs.
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C8128H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and ICC will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
The following equation can be used to calculate the
maximum data rate:
256
Table 1. V53C8128H Data Output
Data Rate =
Operation for Various Cycle Types
tRC + 255 x tPC
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
Fast Page Mode
Read
Data from Addressed
Memory Cell
Fast Page Mode Write
Cycle (Early Write)
High-Z
Fast Page Mode ReadModify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
Data Output Operation
The V53C8128H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition
enables the transfer of data to and from the
selected row address in the Memory Array. A RAS
high transition disables data transfer and latches
the output data if the output is enabled. After a
memory cycle is initiated with a RAS low transition,
a CAS low transition or CAS low level enables the
internal I/O path. A CAS high transition or a CAS
high level disables the I/O path and the output driver
if it is enabled. A CAS low transition while RAS is
high has no effect on the I/O data path or on the
output drivers. The output drivers, when otherwise
enabled, can be disabled by holding OE high. The
OE signal has no effect on any data stored in the
output latches. A WE low level can also disable the
output drivers when CAS is low. During a Write
cycle, if WE goes low at a time in relationship to
CAS that would normally cause the outputs to be
active, it is necessary to use OE to disable the
output drivers prior to the WE low transition to allow
Data In Setup Time (tDS) to be satisfied.
V53C8128H Rev. 1.1 November 1997
16
V53C8128H
MOSEL-VITELIC
Package Outlines
24-pin 300 mil PDIP
0.300/0.330
1.310 Max.
.180 Max.
0.250/0.300
0.005/0.050
0.110/0.140
.008/.013
0.320/0.390
.100 Typ,
0.018./0.024
0.048/0.065
26/24-pin 300 mil SOJ
0.332/0.342
0.296/0.304
0.665/0.698
0.125/0.135
0.082/0.093
0.028 Typ.
V53C8128H Rev. 1.1 November 1997
0.05 Typ.
0.018 Typ.
17
0.025 Min.
0.255/0.275
V53C8128H
MOSEL-VITELIC
V53C8128H Rev. 1.1 November 1997
18
V53C8128H
MOSEL-VITELIC
V53C8128H Rev. 1.1 November 1997
19
MOSEL-VITELIC
V53C8128H
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© Copyright 1996, Vitelic Corporation
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL-VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial
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provide 100% product quality assurance and does not assume
any liability for consequential or incidental arising from any use of
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MOSEL
VITELIC 3910 N. First Street, San Jose, CA 95134-1501
V53C8128H Rev. 1.1 November 1997
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