MOSEL V54C316162VC-55

MOSEL VITELIC
V54C316162VC
V54C316162VC
200/183/166/143 MHz 3.3 VOLT, 2K REFRESH
ULTRA HIGH PERFORMANCE
1M X 16 SDRAM 2 BANKS X 512Kbit X 16
-5
-55
-6
-7
Unit
200
183
166
143
MHz
Latency
3
3
3
3
clocks
Cycle Time (tCK)
5
5.5
6
7
ns
Access Time (tAC )
5
5.3
5.5
5.5
ns
Clock Frequency (tCK)
Features
Description
■ JEDEC Standard 3.3V Power Supply
■ The V54C316162VC is ideally suited for high
performance graphics peripheral applications
■ Single Pulsed RAS Interface
■ Programmable CAS Latency: 2, 3
■ All Inputs are sampled at the positive going edge
of clock
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave
■ UDQM & LDQM for byte masking
■ Auto & Self Refresh
■ 2K Refresh Cycles/32 ms
■ Burst Read with Single Write Operation
The V54C316162VC is a 16,777,216 bits synchronous high data rate DRAM organized as 2 x
524,288 words by 16 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation.
V54C316162VC Rev. 1.4 December 2001
1
MOSEL VITELIC
V54C316162VC
50 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VCC
I/O1
I/O2
VSSQ
I/O3
I/O4
VCCQ
I/O5
I/O6
VSSQ
I/O7
I/O8
VCCQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
VCC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin Names
VSS
I/O16
I/O15
VSSQ
I/O14
I/O13
VCCQ
I/O12
I/O11
VSSQ
I/O10
I/O9
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
V54C316162V-01
V54C316162VC Rev. 1.4 December 2001
2
CLK
Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
A0–A10
Address Inputs
BA
Bank Select
I/O1–I/O16
Data Input/Output
LDQM, UDQM
Data Mask
VCC
Power (+3.3V)
VSS
Ground
VCCQ
Power for I/O’s (+3.3V)
VSSQ
Ground for I/O’s
NC
Not connected
MOSEL VITELIC
V54C316162VC
Block Diagram
MUX
Input
Buffer
Write
Control
Logic
Row
Decoder
Sense Amplifier
Memory Array
Bank 0
512k x 16
UDQM
LDQM
I/O1-I/O16
Memory Array
Bank 1
512k x 16
Output
Buffer
CAS
WE
DQMi
Column Decoder
RAS
Timing
Register
CLK
CKE
CS
Sense Amplifier
Column Decoder
DQMi
Row
Decoder
Row Address
Buffer
Refresh
Counter
Address
Latency 8
Burst Length
CLK
Programming
Register
Column Address
Counter
A0-A10, BA
Row Addresses
Column Address
Buffer
A0-A7, BA
Column Addresses
V54C316162V-02
V54C316162VC Rev. 1.4 December 2001
3
MOSEL VITELIC
V54C316162VC
Signal Pin Description
Pin
Name
Input Function
CLK
Clock Input
System clock input. Active on the positive rising edge to sample all inptus
CKE
Clock Enable
Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self
refresh mode
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
RAS
Row Address Strobe
Latches row addresses on the positive edge of CLK with RAS low.
Enables row access & precharge
CAS
Column Address Strobe
Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
WE
Write Enable
Enables write operation
A0-A10
Address
During a bank activate command, A0-A10 defines the row address.
During a read or write command, A0-A7 defines the column address. In
addition to the column address A10 is used to invoke auto precharge BA
define the bank to be precharged. A10 is low, auto precharge is disabled
during a precharge cycle, If A10 is high, both bank will be precharged ,
if A10 is low, the BA is used to decide which bank to precharge. If A10 is
high, all banks will be precharged.
BA
Bank Select
Selects which bank to activate. BA low select bank A and high selects
bank B
I/O1-I/O16
Data Input/Output
Data inputs/output are multiplexed on the same pins
UDQM, LDQM
Data Input/Output Mask
Makes data output Hi-Z. Blocks data input when DQM is active
VDD/VSS
Power Supply/Ground
Power Supply. +3.3V ± 0.3V/ground
VDDQ/VSSQ
Data Output Power/Ground
Provides isolated power/ground to DQs for improved noise immunity
NC
No Connection
V54C316162VC Rev. 1.4 December 2001
4
MOSEL VITELIC
V54C316162VC
Address Input for Mode Set (Mode Register Operation)
A10 A9
Write Burst Length
Write Burst Length
A9
Length
0
Burst
1
Single Bit
A8
A7
Test
Mode
A6
A5
A4
A3
A2
CAS Latency
BT
Burst Length
0
0
0
A5
0
0
1
Address Bus (Ax)
A0
Mode Register
Burst Type
Test Mode
A8
A7
Mode
A3
Type
0
0
Mode Reg
Set
0
Sequential
1
Interleave
Burst Length
CAS Latency
A6
A1
A4
0
1
0
Length
Latency
A2
A1
A0
Reserve
Sequential
Interleave
0
0
0
1
1
2
0
0
1
2
2
1
0
4
4
Reserve
0
1
1
3
0
1
0
1
Reserve
0
1
1
8
8
1
1
0
Reserve
1
0
0
Reserve
Reserve
1
1
1
Reserve
1
0
1
Reserve
Reserve
1
1
0
Reserve
Reserve
1
1
1
Full Page
Reserve
Power On and Initialization
Programming the Mode Register
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
The Mode register designates the operation
mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst
cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between normal
operation (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate command after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in precharged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is
required. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set
operation. Address input data at this timing defines
parameters to be set as shown in the previous table.
V54C316162VC Rev. 1.4 December 2001
5
MOSEL VITELIC
V54C316162VC
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle
latches the sense amplifiers. The maximum tRAS or
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more
banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, tRCD, from the
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 166 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial
data accesses are done within this boundary. The
first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are
generated automatically by the programmed burst
length and its sequence. For example, in a burst
length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3,
0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using
the sequential burst type and page length is a function of the I/O organisation and column addressing.
Full page burst operation do not self terminate once
the burst length has been reached. In other words,
unlike burst length of 2, 4 or 8, full page burst continues until it is terminated using another command.
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any refresh mode. An on-chip address counter increments
the word and the bank addresses and no bank information is required for both refresh modes.
Burst Length and Sequence:
Burst Starting Address
Length
(A2 A1 A0)
2
xx0
xx1
4
x00
x01
x10
x11
8
000
001
010
011
100
101
110
111
Full
Page
nnn
V54C316162VC Rev. 1.4 December 2001
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
0, 1
1, 0
0,
1,
2,
3,
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
0, 1
1, 0
1,
2,
3,
0,
2,
3,
0,
1,
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
0,
1,
2,
3,
3
0
1
2
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
Cn, Cn+1, Cn+2,.....
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
1,
0,
3,
2,
2,
3,
0,
1,
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
3
2
1
0
5
4
7
6
1
0
3
2
not supported
6
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
MOSEL VITELIC
V54C316162VC
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay
is required prior to any access command.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, A10, to determine whether the chip restores or not after the
operation. If A10 is high when a Read Command is
issued, the Read with Auto-Precharge function is
initiated. The SDRAM automatically enters the precharge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3.
If A10 is high when a Write Command is issued, the
Write with Auto-Precharge function is initiated.
The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery
time) after the last data in.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. With A10 being low, the BA is used select
bank to precharge. The precharge command can be
imposed one clock before the last data out for CAS
latency = 2, two clocks before the last data out for
CAS latency = 3. Writes require a time delay twr
from the last data out to apply the precharge command. If A10 is high, all banks will be precharged.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ ). It also provides
a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
DQM is used for device selection, byte selection
and bus control in a memory system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These
methods include using another Read or Write Command to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Command to terminate the existing burst operation but
leave the bank open for future Read or Write Commands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh operations, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for
mode entry and exit.
V54C316162VC Rev. 1.4 December 2001
7
MOSEL VITELIC
V54C316162VC
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70 °C
Storage temperature range ............... -55 to 150 °C
Input/output voltage .................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ............................................. 1 W
Data out current (short circuit) ...................... 50 mA
*Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Recommended Operation and Characteristics
TA = 0 to 70 °C; VSS = 0 V; VCC,VCCQ = 3.3 V ± 0.3 V
Limit Values
Parameter
Symbol
Min.
Max.
Unit
Notes
Input high voltage
VIH
2.0
Vcc+0.3
V
1, 2
Input low voltage
VIL
– 0.3
0.8
V
1, 2
Output high voltage (IOUT = – 2.0 mA)
VOH
2.4
–
V
Output low voltage (IOUT = 2.0 mA)
VOL
–
0.4
V
Input leakage current, any input
(0 V < V IN < 3.6 V, all other inputs = 0 V)
II(L)
–5
5
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC )
IO(L)
–5
5
µA
Capacitance
VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200mV
Pin
Symbol
Min.
Max.
Unit
Clock
CCLK
2
4
pF
RAS, CAS, WE, CS, CKE, L(U)DQM
CIN
2
4
pF
A0–A10
CADD
2
4
pF
DQ0–DQ 15
COUT
3
5
pF
Note:
1. All voltages are referenced to VSS.
2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with
3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
V54C316162VC Rev. 1.4 December 2001
8
MOSEL VITELIC
V54C316162VC
Operating Currents (TA = 0 to 70°C, VCC = 3.3V ± 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Max.
Symbol
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
Parameter & Test Condition
-5
-55
-6
-7
Unit Note
125
120
115
105
mA
3
Operating Current
Active-precharge command cycling,
without Burst Operation
1 bank operation
tRC = tRCMIN., tCK = tCKMIN
CL = 3
Precharge Standby Current
in Power Down Mode
tCK = min.
2
2
2
2
mA
3
tCK = Infinity
2
2
2
2
mA
3
tCK = min.
15
15
15
15
mA
tCK = Infinity
5
5
5
5
mA
Active Standby Current in
Power-down mode
CKE=<VIL(max), tck = min
3
3
3
3
mA
CKE =< VIL(max), tck = infinity
3
3
3
3
mA
Active Standby Current in
non Power-down mode
CKE=>VIL(max), tck = min
45
45
45
45
mA
CKE => VIL(max), tck = infinity
40
40
40
40
mA
Burst Operating Current
Read/Write command cycling
CL = 3 tCK = min.
160
155
150
140
mA
CL = 2 tCK = min.
160
155
150
140
mA
CL = 3
tCK = min.
110
105
100
90
mA
1
1
1
1
mA
CS =VIH, CKE≤ VIL(max)
Precharge Standby Current
in Non-Power Down Mode
CS =VIH, CKE≥ VIL(max)
ICC5
Auto Refresh Current
Auto Refresh command cycling
ICC6
Self Refresh Current
Self Refresh Mode, CKE=<0.2V
3, 4
3
Notes:
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK except for ICC6 and for standby current when tCK = infinity.
4. These parameter are measured with continuous data stream during read access and all DQ toggling.
V54C316162VC Rev. 1.4 December 2001
9
MOSEL VITELIC
V54C316162VC
AC Characteristics (1,2,3)
TA = 0 to 70°C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-5
# Symbol Parameter
-55
-6
-7
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
5
10
–
–
5.5
10
–
–
6
10
–
–
7
10
–
–
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
200
100
–
–
183
100
–
–
166
100
–
–
143
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
–
5
7
–
–
5.3
7
–
–
5.5
7
–
–
5.5
7
ns
ns
tCH
Clock High Pulse Width
2.5
–
2.5
–
2.5
–
2.5
–
ns
tCL
Clock Low Pulse Width
2.5
–
2.5
–
2.5
–
2.5
–
ns
tT
Transition time
1
10
1
10
1
10
1
10
ns
Clock and Clock Enable
tCK
tCK
tAC
2
3
Setup and Hold Times
tCMDS
Command Setup Time
2
–
2
–
2
–
2
–
ns
4
tAS
Address Setup Time
2
–
2
–
2
–
2
–
ns
4
tDS
Data In Setup Time
2
–
2
–
2
–
2
–
ns
4
tCKS
CKE Setup Time
2
–
2
–
2
–
2
–
ns
4
tCMDH
Command Hold Time
1
–
1
–
1
–
1
–
ns
4
tAH
Address Hold Time
1
–
1
–
1
–
1
–
ns
4
tDH
Data In Hold Time
1
–
1
–
1
–
1
–
ns
4
tCKH
CKE Hold Time
1
–
1
–
1
–
1
–
ns
4
Common Parameters
tRCD
Row to Column Delay Time
15
–
16.5
–
18
–
18
–
ns
5
tRAS
Row Active Time
40
100K
45
100K
48
100K
48
100K
ns
5
tRC
Row Cycle Time
60
–
63
–
66
–
70
–
ns
5
tRP
Row Precharge Time
15
–
17
–
18
–
21
–
ns
5
tRRD
Activate(a) to Activate(b) Command
period
10
–
11
–
12
–
14
–
ns
5
tCCD
CAS(a) to CAS(b) Command period
1
–
1
–
1
–
1
–
CLK
tRCS
Mode Register Set-up time
10
–
11
–
12
–
14
–
ns
tSB
Power Down Mode Entry Time
0
5
0
5.5
0
6
0
7
ns
tCDL
Last data in to new column address delay
5
–
5.5
–
6
–
7
–
ns
V54C316162VC Rev. 1.4 December 2001
10
MOSEL VITELIC
V54C316162VC
AC Characteristics (1,2,3) (Continued)
TA = 0 to 70°C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-5
# Symbol Parameter
tBDL
Last data in to burst stop
-55
-6
-7
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
5
–
5.5
–
6
–
7
–
ns
–
32
–
32
–
32
–
32
ms
Refresh Cycle
tREF
Refresh Period (2048 cycles)
tSREX
Self Refresh Exit Time
2 CLK + tRC
tOH
Data Out Hold Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
tHZ
CAS Latency = 3
CAS Latency = 2
–
–
5
7
–
–
5.3
7
–
–
5.5
7
–
–
5.5
7
ns
tDQZ
DQM Data Out Disable Latency
2
–
2
–
2
–
2
–
CLK
tLZ
Data Out Low-Z time
–
1
–
1
–
1
–
1
ns
Write Recovery Time
CAS Latency = 3
CAS Latency = 2
5
10
–
–
5.5
10
–
–
6
10
–
–
7
10
–
–
ns
ns
0
–
0
–
0
–
0
–
CLK
10
–
11
–
12
–
14
–
ns
2 CLK + tRC
6
Read Cycle
Write Cycle
tWR
tDQW
DQM Write Mask Latency
tRDL
Last data in to row precharge
V54C316162VC Rev. 1.4 December 2001
11
MOSEL VITELIC
V54C316162VC
Notes for AC Parameters:
1.For proper power-up see the operation section of this data sheet.
2.AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and V IL. All AC measurements assume tT = 1ns with the AC output load circuit shown
in Figure 1
tCK
VIH
CLK
VIL
+ 1.4 V
tT
tCS
tCH
50 Ohm
1.4V
COMMAND
Z=50 Ohm
tAC
tLZ
I/O
tAC
50 pF
tOH
1.4V
OUTPUT
tHZ
Figure 1.
3.If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
4.If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
5.These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
6.Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
V54C316162VC Rev. 1.4 December 2001
12
MOSEL VITELIC
V54C316162VC
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
5.1 Burst Write to Precharge
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Full Page Burst Write Operation
8.2 Termination of a Full Page Burst Write Operation
V54C316162VC Rev. 1.4 December 2001
13
MOSEL VITELIC
V54C316162VC
1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
..........
ADDRESS
Bank A
Col. Addr.
Bank A
Row Addr.
..........
Bank A
Row Addr.
Bank B
Row Addr.
tRCD
COMMAND
Bank A
Activate
NOP
tRRD
Write A
with Auto
Precharge
NOP
..........
Bank B
Activate
Bank A
Activate
NOP
: “H” or “L”
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
V54C316162VC Rev. 1.4 December 2001
NOP
DOUT A0
NOP
NOP
DOUT A1
DOUT A2
DOUT A0
14
DOUT A1
NOP
NOP
DOUT A3
DOUT A2
DOUT A3
NOP
NOP
MOSEL VITELIC
V54C316162VC
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
READ A
READ B
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 2
NOP
DOUT A0
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
NOP
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
T3
T4
T5
T6
NOP
NOP
DOUT B3
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T7
T8
CLK
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
I/O’s
NOP
NOP
NOP
WRITE B
DIN B0
DOUT A0
Must be Hi-Z before
the Write Command
: “H” or “L”
V54C316162VC Rev. 1.4 December 2001
NOP
15
NOP
NOP
DIN B1
DIN B2
MOSEL VITELIC
V54C316162VC
4.2 Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
1 Clk Interval
COMMAND
NOP
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
CAS latency = 2
DIN A0
tCK2, I/O’s
: “H” or “L”
4.3 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
DIN B0
DIN B1
DIN B2
DIN B0
DIN B1
DIN B2
CLK
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
CAS latency = 2
tCK1, I/O’s
DOUT A0
DOUT A1
Must be Hi-Z before
the Write Command
CAS latency = 3
DOUT A0
tCK2, I/O’s
: “H” or “L”
V54C316162VC Rev. 1.4 December 2001
16
MOSEL VITELIC
V54C316162VC
5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
I/O’s
WRITE A
DIN A0
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
The first data element and the Write
are registered on the same clock edge.
NOP
NOP
NOP
NOP
don’t care
Extra data is ignored after
termination of a Burst.
5.1 Write to Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
NOP
NOP
T6
T7
T8
tRDL
I/O’S
DIN A0
DIN A1
DIN A2
DIN A3
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
WRITE A
WRITE B
T3
T4
T5
CLK
COMMAND
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
tCDL
I/O’s
DIN A0
V54C316162VC Rev. 1.4 December 2001
DIN B0
17
NOP
NOP
NOP
MOSEL VITELIC
V54C316162VC
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
WRITE A
READ B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
DIN A0
don’t care
DIN A0
don’t care
NOP
NOP
NOP
DOUT B0
don’t care
NOP
NOP
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
NOP
DOUT B3
Input data must be removed from the I/O’s at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
BANK A
ACTIVE
NOP
NOP
WRITE A
NOP
Auto-Precharge
NOP
tWR
CAS latency = 2
I/O’s
DIN A0
DIN A1
tWR
CAS latency = 3
I/O’s
DIN A0
DIN A1
NOP
NOP
tRP
*
tRP
*
*
Begin Autoprecharge
Bank can be reactivated after trp
V54C316162VC Rev. 1.4 December 2001
18
NOP
MOSEL VITELIC
V54C316162VC
7.2 Burst Read with Auto-Precharge
Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
NOP
DOUT A0
NOP
NOP
*
DOUT A1
NOP
*
DOUT A1
*
NOP
NOP
t RP
DOUT A2
DOUT A0
NOP
DOUT A3
t RP
DOUT A2
DOUT A3
*
Begin Autoprecharge
Bank can be reactivated after tRP
V54C316162VC Rev. 1.4 December 2001
19
MOSEL VITELIC
V54C316162VC
8.1 Termination of a Full Page Burst Read Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, I/O’s
NOP
NOP
Burst
Stop
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
CAS latency = 3
tCK3, I/O’s
NOP
NOP
NOP
NOP
DOUT A3
The burst ends after a delay equal to the CAS latency.
8.2 Termination of a Full Page Burst Write Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
NOP
Burst
Stop
NOP
NOP
tBDL
CAS latency = 2,3
I/O’s
DIN A0
DIN A1
don’t care
DIN A2
Input data for the Write is masked.
V54C316162VC Rev. 1.4 December 2001
20
NOP
NOP
NOP
MOSEL VITELIC
V54C316162VC
Package Diagram
50-Pin Plastic TSOP-II (400 mil)
0.039 ± 0.002
[1 ± 0.05]
0.004±0.002
[0.1±0.05]
0.031 [0.8]
0.016 +0.002
–0.004
0.047 Max
[1.2 Max]
0.004 [0.1]
0.008 [0.2] M 44x
0.4 ± 0.005
[10.16 ± 0.13]
+0.003
0.006 –0.001
+0.08
0.15 –0.03
0.020±0.004
[0.5 ± 0.1]
0.463±0.008
[11.76 ± 0.2]
0.4 +0.05
–0.1
50
26
1
25
1
0.825±0.005
[20.95±0.13]
1
Unit in inches [mm]
Does not include plastic or metal protrusion of 0.010 [0.25] max. per side
V54C316162VC Rev. 1.4 December 2001
21
MOSEL VITELIC
WORLDWIDE OFFICES
V54C316162VC
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U.S. SALES OFFICES
NORTHWESTERN
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302 N. EL CAMINO REAL #200
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PHONE: 949-361-7873
FAX: 949-361-7807
© Copyright, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
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personal injury might occur from failure, purchaser must do its
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