TI TUSB1310AZAYR

TUSB1310A
USB 3.0 Transceiver
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLLSE32D
November 2010 – Revised May 2011
TUSB1310A
SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011
www.ti.com
Contents
1
2
3
4
2
......................................................................................................... 7
1.1
Features ...................................................................................................................... 7
1.2
Target Applications ......................................................................................................... 7
1.3
Introduction .................................................................................................................. 8
1.4
Functional Block Diagram .................................................................................................. 8
PIN DESCRIPTIONS ........................................................................................................... 10
2.1
Configuration Pins ......................................................................................................... 10
2.2
PIPE ......................................................................................................................... 10
2.3
ULPI ......................................................................................................................... 13
2.3.1
ULPI Modes ..................................................................................................... 13
2.4
Clocking ..................................................................................................................... 14
2.5
JTAG Interface ............................................................................................................. 14
2.6
Reset and Output Control Interface ..................................................................................... 14
2.7
Strap Options .............................................................................................................. 14
2.8
USB Interfaces ............................................................................................................. 15
2.9
Special Connect ........................................................................................................... 15
2.10 Power and Ground ........................................................................................................ 16
FUNCTIONAL DESCRIPTION ............................................................................................... 18
3.1
Power On and Reset ...................................................................................................... 18
3.1.1
RESETN and PHY_RESETN – Hardware Reset .......................................................... 18
3.1.2
ULPI Reset – Software Reset ................................................................................. 18
3.1.3
OUT_ENABLE - Output Enable .............................................................................. 18
3.1.4
Power Up Sequence ........................................................................................... 18
3.2
Clocks ....................................................................................................................... 19
3.2.1
Clock Distribution ............................................................................................... 19
3.2.2
Output Clock .................................................................................................... 19
3.3
Power Management ....................................................................................................... 19
3.3.1
USB Power Management ...................................................................................... 20
3.4
Receiver Status ............................................................................................................ 21
3.4.1
Clock Tolerance Compensation .............................................................................. 21
3.4.2
Receiver Detection ............................................................................................. 21
3.4.3
8b/10b Decode Errors .......................................................................................... 22
3.4.4
Elastic Buffer Errors ............................................................................................ 22
3.4.5
Disparity Errors ................................................................................................. 22
3.5
Loopback ................................................................................................................... 22
3.6
Adaptive Equalizer ........................................................................................................ 23
REGISTERS ...................................................................................................................... 24
4.1
Register Definitions ........................................................................................................ 24
4.2
Register Map ............................................................................................................... 24
4.2.1
Vendor ID and Product ID (00h-03h) ........................................................................ 24
4.2.2
Function Control (04h-06h) .................................................................................... 25
4.2.3
Interface Control (07h-09h) .................................................................................... 26
4.2.4
OTG Control ..................................................................................................... 26
4.2.5
USB Interrupt Enable Rising (0Dh-0Fh) ..................................................................... 26
4.2.6
USB Interrupt Enable Falling (10h-12h) ..................................................................... 27
PRODUCT OVERVIEW
Contents
Copyright © 2010–2011, Texas Instruments Incorporated
TUSB1310A
SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011
www.ti.com
5
6
.................................................................................... 27
..................................................................................... 27
4.2.9
Debug (15h) ..................................................................................................... 27
4.2.10 Scratch Register (16-18h) ..................................................................................... 27
DESIGN GUIDELINES ......................................................................................................... 28
5.1
Chip Connection on PCB ................................................................................................. 28
5.1.1
USB Connector Pins Connection ............................................................................. 28
5.1.2
Clock Connections .............................................................................................. 29
5.2
Clock Source Requirements ............................................................................................. 30
5.2.1
Clock Source Selection Guide ................................................................................ 30
5.2.2
Oscillator ......................................................................................................... 30
5.2.3
Crystal ............................................................................................................ 31
ELECTRICAL SPECIFICATIONS .......................................................................................... 32
6.1
ABSOLUTE MAXIMUM RATINGS ...................................................................................... 32
6.2
RECOMMENDED OPERATING CONDITIONS ....................................................................... 32
6.3
DC CHARACTERISTICS for 1.8-V DIGITAL IO ....................................................................... 32
6.4
DEVICE POWER CONSUMPTION ..................................................................................... 33
6.5
AC Characteristics ......................................................................................................... 33
6.5.1
Power Up and Reset Timing .................................................................................. 33
6.5.2
PIPE Transmit ................................................................................................... 34
6.5.3
PIPE Receive ................................................................................................... 35
6.5.4
ULPI Parameters ............................................................................................... 35
6.5.5
ULPI Clock ....................................................................................................... 35
6.5.6
ULPI Transmit ................................................................................................... 36
6.5.7
ULPI Receive Timing ........................................................................................... 36
6.5.8
Power State Transition Time .................................................................................. 37
4.2.7
USB Interrupt Status (13h)
4.2.8
USB Interrupt Latch (14h)
Copyright © 2010–2011, Texas Instruments Incorporated
Contents
3
TUSB1310A
SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011
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List of Figures
1-1
Typical Application ................................................................................................................. 8
1-2
Functional Block Diagram
3-1
5-1
5-2
5-3
5-4
6-1
6-2
6-3
6-4
6-5
4
........................................................................................................
Power-Up Sequence .............................................................................................................
Analog Pin Connections .........................................................................................................
USB Standard-A Connector Pin Connection .................................................................................
USB Standard-B Connector Pin Connection .................................................................................
Typical Crystal Connections ....................................................................................................
Power Up and Reset Timing ....................................................................................................
PIPE Transmit Timing ...........................................................................................................
PIPE Receive Timing ............................................................................................................
ULPI Transmit Timing............................................................................................................
ULPI Receive Timing ............................................................................................................
List of Figures
9
19
28
29
29
30
34
34
35
36
36
Copyright © 2010–2011, Texas Instruments Incorporated
TUSB1310A
SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011
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List of Tables
2-1
Configuration Pins ................................................................................................................ 10
2-2
PIPE Signal Description ......................................................................................................... 10
2-3
ULPI Signal Description ......................................................................................................... 13
2-4
ULPI Synchronous and Low Power Mode Functions ........................................................................ 13
2-5
Clock Signal Name Description
2-6
JTAG Signal Name Description ................................................................................................ 14
2-7
Reset and Output Control Signal Description
2-8
2-9
2-10
2-11
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
5-2
6-1
6-2
6-3
6-4
6-5
6-6
6-7
................................................................................................
................................................................................
Strapping Options ................................................................................................................
USB Interface Signal Name Descriptions .....................................................................................
Special Connect Signal Descriptions ..........................................................................................
Power/Ground Signal Descriptions ............................................................................................
Pin States in Chip Reset ........................................................................................................
Power States ......................................................................................................................
PIPE Control Pin Matrix .........................................................................................................
RX_STATUS - SKP ..............................................................................................................
RX_STATUS - Receiver Detection.............................................................................................
8b/10b Decode Errors ...........................................................................................................
Elastic Buffer Errors ..............................................................................................................
Disparity Errors ...................................................................................................................
Register Definitions ..............................................................................................................
Register Map ......................................................................................................................
Vendor ID and Product ID .......................................................................................................
Function Control ..................................................................................................................
Interface Control ..................................................................................................................
OTG Control Register............................................................................................................
USB Interrupt Enable Rising ....................................................................................................
USB Interrupt Enable Falling ...................................................................................................
USB Interrupt Status .............................................................................................................
USB Interrupt Latch ..............................................................................................................
Debug ..............................................................................................................................
Scratch Register ..................................................................................................................
Oscillator Specification ..........................................................................................................
Crystal Specification .............................................................................................................
Power Up and Reset Timing ....................................................................................................
PIPE Transmit Timing ...........................................................................................................
PIPE Receive Timing ............................................................................................................
ULPI Parameters .................................................................................................................
ULPI Clock Parameters .........................................................................................................
ULPI Transmit Timing............................................................................................................
ULPI Receive Timing ............................................................................................................
Copyright © 2010–2011, Texas Instruments Incorporated
List of Tables
14
14
14
15
15
16
18
20
20
21
21
22
22
22
24
24
24
25
26
26
26
27
27
27
27
27
30
31
34
34
35
35
35
36
36
5
TUSB1310A
SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011
6
List of Tables
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Copyright © 2010–2011, Texas Instruments Incorporated
TUSB1310A
SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011
www.ti.com
USB 3.0 Transceiver
Check for Samples: TUSB1310A
1
PRODUCT OVERVIEW
1.1
Features
• Universal Serial Bus (USB)
– Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver
• One 5.0-Gbps SuperSpeed Connection
• One 480-Mbps HS/FS/LS Connection
– Fully Compliant with USB 3.0 Specification, Revision 1.0
– Supports 3+ Meters USB 3.0 Cable Length
– Fully Adaptive Equalizer to Optimize Receiver Sensitivity
– PIPE to Link Layer Controller
• Supports 16-Bit SDR Mode at 250 MHz
• Compliant With PHY Interface for the USB Architectures (PIPE), Version 3.0
– ULPI to Link Layer Controller
• Supports 8-Bit SDR Mode at 60 MHz
• Supports Synchronous Mode and Low Power Mode
• Compliant with UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1
• General Features
– IEEE 1149.1 JTAG Support
– IEEE 1149.6 JTAG support for the SuperSpeed Port
– Operates on a Single Reference Clock of 40 MHz
– 3.3-, 1.8-, and 1.1-V Supply Voltages
– 1.8-V PIPE and ULPI I/O
– Available in Lead-Free 175-Ball 12- x 12-nF BGA Package (175ZAY)
1
1.2
•
•
•
•
•
•
•
•
•
•
Target Applications
Surveillance Cameras
Multimedia Handset
Smartphone
Digital Still Camera
Portable Media Player
Personal Navigation Device
Audio Dock
Video IP Phone
Wireless IP Phone
Software Defined Radio
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TUSB1310A
SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011
1.3
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Introduction
The TUSB1310A is a single port, 5.0-Gbps USB 3.0 physical layer transceiver operating off of a single
reference clock provided by either a crystal or an external reference clock. The reference clock
frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310A provides the clock to the USB
controller. The use of a single reference clock allows the TUSB1310A to provide a cost effective USB 3.0
solution with few external components and a low implementation cost.
The USB controller interfaces to the TUSB1310A via a PIPE (SuperSpeed) and a ULPI (USB2.0)
interface. The 16-bit PIPE operates off of a 250-MHz interface clock. The ULPI supports 8-bit operations
with a 60-MHz interface clock.
USB 3.0 reduces active and idle power consumption with improved power management features. The
TUSB1310A low power states are controlled by the USB controller via the PIPE interface.
SuperSpeed USB uses existing USB software infrastructure by keeping the existing software interfaces
and software drivers intact. In addition, SuperSpeed USB retains backward compatibility with USB 2.0
based products by using the same form-factor Type-A connector and cables. Existing USB 2.0 devices will
work with new USB 3.0 hosts and new USB 3.0 devices with work with legacy USB 2.0 hosts.
MCU/CPU
Link Controller
Crystal
PIPE
(16 bit 250 MHz)
TUSB1310A
SSTX P/N
SSRX P/N
5.0 Gbps
ULPI
DP/DM
(8 bit 60 MHz)
CLKOUT
Figure 1-1. Typical Application
1.4
Functional Block Diagram
The USB physical layer handles the low level USB protocol and signaling. This includes data serialization
and deserialization, 8b/10b encoding, analog buffers, elastic buffers and receiver detection. It shifts the
clock domain of the data from the USB rate to one that is compatible with the link layer controller.
The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXP differential pairs and uses the PIPE
to communicate with the link layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and
communicates with the link layer controller via the ULPI. The TUSB1310A reference clock is connected to
an internal crystal oscillator, spread spectrum clock and PLL which provides clocks to all functional blocks
and to the CLKOUT pin for the link layer controller.
A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan.
8
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Figure 1-2. Functional Block Diagram
PRODUCT OVERVIEW
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PIN DESCRIPTIONS
TYPE
DESCRIPTION
I
Input
O
Output
I/O
Input/output
PD, PU
2.1
Internal pull-down / pull-up
S
Strapping pin
P
Power Supply
G
Ground
Configuration Pins
The configuration pins are not latched by RESETN.
Table 2-1. Configuration Pins
SIGNAL NAME
TYPE
PIN NO.
MODE NAME
PHY_MODE1
I, PD
H12
USB
Must be set to 0. Operates as USB 3.0 transceiver.
PHY_MODE0
I, PU
J12
USB
Must be set to 1. Operates as USB 3.0 transceiver.
2.2
DESCRIPTION
PIPE
The TUSB1310A supports 16-bit SDR mode with a 250-MHz clock.
Table 2-2. PIPE Signal Description
SIGNAL NAME
TX_CLK
TYPE
I
BALL NO.
DESCRIPTION
K1
TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is
the same as PCLK frequency. The rising edge of the clock is the reference for all signals.
TX_DATA15
G2
TX_DATA14
H2
TX_DATA13
H1
TX_DATA12
J2
TX_DATA11
L3
TX_DATA10
L2
TX_DATA9
M2
TX_DATA8
TX_DATA7
I
M1
N1
TX_DATA6
P1
TX_DATA5
N2
TX_DATA4
P2
TX_DATA3
N3
TX_DATA2
P3
TX_DATA1
N4
TX_DATA0
P5
TX_DATAK1
G1
TX_DATAK0
PCLK
10
I
O
J1
A6
Parallel USB SuperSpeed data input bus.
The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to
be transmitted, and TX_DATA15-8 is the second symbol.
Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of
TX_DATA, TX_DATAK1 to the upper byte.
Parallel interface data clock. All data movement across the parallel PIPE is synchronous
to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference
for all signals.
PIN DESCRIPTIONS
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Table 2-2. PIPE Signal Description (continued)
SIGNAL NAME
TYPE
BALL NO.
RX_DATA15
B9
RX_DATA14
A9
RX_DATA13
A8
RX_DATA12
B8
RX_DATA11
B5
RX_DATA10
B4
RX_DATA9
A4
RX_DATA8
RX_DATA7
O
B3
A3
RX_DATA6
A2
RX_DATA5
B1
RX_DATA4
C2
RX_DATA3
C1
RX_DATA2
D1
RX_DATA1
D2
RX_DATA0
E2
RX_DATAK1
RX_DATAK0
RX_VALID
B7
O
O
DESCRIPTION
Parallel USB SuperSpeed data output bus.
The 16 bits represent 2 symbols of receive data where RX_DATA7-0 is the first symbol
received, and RX_DATA15-8 is the second.
A7
Data/Control for the symbols of receive data. RX_DATAK0 corresponds to the low-byte of
RX_DATA, RX_DATAK1 to the upper byte. A value of zero indicates a data byte; a value
of 1 indicates a control byte.
F1
Active High. Indicates symbol lock and valid data on RX_DATA and RX_DATAK.
CONTROL AND STATUS SIGNALS
PHY_RESETN
I, PU
J3
Active Low. Resets the transmitter and receiver. This signal is asynchronous.
TX_DETRX_LPBK
I, PD
M6
Active High. Used to tell the PHY to begin a receiver detection operation or to begin
loopback.
TX_ELECIDLE
I
K3
Active High. Forces TX output to electrical idle depending on the power state.
RX_ELECIDLE
S, I/O,
PD
F3
Active High. While de-asserted with the PHY in P0, P1, P2, or P3, indicates detection of
LFPS.
C7
Encodes receiver status and error codes for the received data stream when receiving
data.
RX_STATUS2
RX_STATUS1
O
RX_STATUS0
POWER_DOWN1
POWER_DOWN0
I
C6
BIT 2
BIT 1
BIT 0
C5
0
0
0
Received data OK
0
0
1
1 SKP ordered set added
0
1
0
1 SKP ordered set removed
0
1
1
Receiver detected
1
0
0
8B/10B decode error
1
0
1
Elastic buffer overflow
1
1
0
Elastic buffer underflow.
This error code is not used if the elasticity buffer is
operating in the nominal buffer empty mode.
1
1
1
Receive disparity error
G3
H3
DESCRIPTION
Power up and down the transceiver power states.
BIT 1
BIT 0
DESCRIPTION
0
0
P0, normal operation
0
1
P1, low recovery time latency, power saving state
1
0
P2, longer recovery time latency, low power state
1
1
P3, lowest power state
When transitioning from P3 to P0, the signaling is asynchronous.
PIN DESCRIPTIONS
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Table 2-2. PIPE Signal Description (continued)
SIGNAL NAME
TYPE
BALL NO.
DESCRIPTION
Active High. Used to communicate completion of several PHY functions including power
management state transitions, rate change, and receiver detection. When this signal
transitions during entry and exit from P3 and PCLK is not running, then the signaling is
asynchronous.
PHY_STATUS
S, I/O,
PD
E3
PWRPRESENT
O
H11
Indicates the presence of VBUS
I, PD
M4
Active High. Used only when transmitting USB compliance pat-terns CP7 or CP8. Causes
the transmitter to transmit an alternating sequence of 50 - 250 ones and 50 - 250 zeros –
regardless of the state of the TX_DATA interface.
K11
Selects transmitter de-emphasis. When the MAC changes, the TUSB1310A starts to
transmit with the new setting within 128 ns.
CONFIGURATION PINS
TX_ONESZEROS
TX_DEEMPH1
I, PD, PU
TX_DEEMPH0
L11
TX_MARGIN2
TX_MARGIN1
M11
I, PD
TX_MARGIN0
BIT 1
BIT 0
DESCRIPTION
0
0
-6 dB de-emphasis
0
1
-3.5 dB de-emphasis
1
0
No de-emphasis
1
1
Reserved
Selects transmitter voltage levels
M10
BIT 2
BIT 1
BIT 0
TX_SWING
M9
0
0
0
0
Normal operating range
800 mV - 1200 mV
0
0
0
1
Normal operating range
400 mV - 700 mV
0
0
1
0
800 mV - 1200 mV
1
400 mV - 700 mV
0
700 mV - 900 mV
1
300 mV - 500 mV
0
400 mV - 600 mV
1
200 mV - 400 mV
0
200 mV - 400 mV
1
100 mV - 200 mV
0
0
1
1
1
1
0
1
Don't care
DESCRIPTION
Controls transmitter voltage swing level
TX_SWING
I, PD
M5
0 Full swing
1 Half swing
Active High. Tells PHY to do a polarity inversion on the received data. Inverted data show
up on RX_DATA15-0 within 20 PCLK clocks after RX_POLARITY is asserted.
RX_POLARITY
I, PD
C8
0 PHY does no polarity inversion.
1 PHY does polarity inversion.
Controls presence of receiver terminations
RX_TERMINATION
I, PD
D3
0 Terminations removed
1 Terminations present
RATE
I, PU
L6
ELAS_BUF_MODE
I, PD
C9
Controls the link signaling rate
The RATE is always 1.
Selects elasticity buffer operating mode
0 Nominal half full buffer mode
1 Nominal empty buffer mode
12
PIN DESCRIPTIONS
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2.3
ULPI
The ULPI (ultra low pin count interface) is a low pin count USB PHY to a link layer controller interface. The
ULPI consists of the interface and the ULPI registers. The TUSB1310A is always the master of the ULPI
bus.
Table 2-3. ULPI Signal Description
SIGNAL NAME
ULPI_CLK
TYPE
O
ULPI_DATA7
BALL NO.
DESCRIPTION
P11
60-MHz interface clock. All ULPI signals are synchronous to ULPI_CLK. The ULPI_CLK is
always a 60-MHz output of the TUSB1310A. In low power mode, the ULPI_CLK is not driven.
N6
ULPI_DATA6
P6
ULPI_DATA5
N7
ULPI_DATA4
ULPI_DATA3
S, I/O, PD
ULPI_DATA2
P7
N8
Data bus. Driven to 00h by the Link when the ULPI bus is idle.
8-bit data timed on rising edge of ULPI_CLK
P8
ULPI_DATA1
P9
ULPI_DATA0
N9
Controls the direction of the ULPI_DATA bus
ULPI_DIR
O
M7
0 ULPI_DATA lines are inputs
1 ULPI_DATA lines are outputs
ULPI_STP
S, I, PU
M8
Active High. The Link must assert ULPI_STP to signal the end of a USB transmit packet or a
register write operation. The ULPI_STP signal must be asserted in the cycle after the last data
byte is presented on the bus. The ULPI_STP has an internal weak pull-up to safeguard
against false commands on the ULPI_DATA lines.
ULPI_NXT
O
N11
Active High. The PHY asserts ULPI_NXT to throttle all data types, except register read data
and the RX CMD. The PHY also asserts ULPI_NXT and ULPI_DIR simultaneously to indicate
USB receive activity, if ULPI_DIR was previously low. The PHY is not allowed to assert
ULPI_NXT during the first cycle of the TX CMD driven by the Link.
2.3.1
ULPI Modes
The TUSB1310A supports synchronous mode and low power mode. The default mode is synchronous
mode.
The synchronous mode is a normal operation mode. The ULPI_DATA are synchronous to ULPI_CLK. The
low power mode is used during power down and no ULPI_CLK. The TUSB1310A sets ULPI_DIR to output
and drives LineState signals and interrupts.
Table 2-4. ULPI Synchronous and Low Power Mode Functions
SYNCHRONOUS
LOW POWER
ULPI_CLK(OUT)
ULPI_DATA7(I/O)
ULPI_DATA6(I/O)
ULPI_DATA5(I/O)
ULPI_DATA4(I/O)
ULPI_DATA3(I/O)
ULPI_INT (OUT)
ULPI_DATA2(I/O)
ULPI_DATA1(I/O)
ULPI_LINESTATE1(OUT)
ULPI_DATA0(I/O)
ULPI_LINE_STATE0 (OUT)
ULPI_DIR(OUT)
ULPI_STP(IN)
ULPI_NXT(OUT)
PIN DESCRIPTIONS
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2.4
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Clocking
Table 2-5. Clock Signal Name Description
SIGNAL NAME
TYPE
DESCRIPTION
A12
Crystal Input. This pin is the clock reference input for the TUSB1310A. The
TUSB1310A supports either a crystal unit, or a 1.8-V clock input. Frequencies
supported are 20, 25, 30, or 40 MHz.
O
A11
Crystal output. If a 1.8-V clock input is connected to XI, XO must be left open.
O
D10
OOBCLK is driven in U3 mode.
XI
I
XO
CLKOUT
2.5
BALL NO.
JTAG Interface
The JTAG Interface is used for board-level boundary scan. All digital IO support IEEE1149.1 boundary
scan and SuperSpeed differential pairs support IEEE1149.6 boundary scan.
Table 2-6. JTAG Signal Name Description
SIGNAL NAME
TYPE
BALL NO.
JTAG_TCK
I, PU
G11
JTAG test clock
JTAG_TMS
I, PU
D11
JTAG test mode select
JTAG_TDI
I, PU
E11
JTAG test data input
JTAG_TRSTN
I, PD
E12
JTAG test asynchronous reset. Active Low.
O
F11
JTAG test data output
JTAG_TDO
2.6
DESCRIPTION
Reset and Output Control Interface
Table 2-7. Reset and Output Control Signal Description
SIGNAL NAME
RESETN
OUT_ENABLE
2.7
TYPE
BALL NO.
I
J11
Active Low. Resets the transmitter and receiver. This signal is asynchronous.
L10
Active High. This can be connected to a 1.8-V power on reset signal on the PCB in
order to avoid static current and signal contention during power up.
0: Disable all driver outputs while IO powers are supplied, but internal control circuit
powers are not present during power up.
1: Enable all driver outputs during normal operation.
I
DESCRIPTION
Strap Options
Strapping pins are latched by reset de-assertion in the TUSB1310A.
Table 2-8. Strapping Options
SIGNAL NAME
TYPE
BALL NO.
DESCRIPTION
Selects an input clock source
XTAL_DIS
(RX_ELECIDLE)
S, I/O, PD
F3
0
Crystal Input
1
Clock Input
Spread spectrum clocking disable
SSC_DIS
(TX_MARGIN0)
S, I, PD
M9
0
SSC enable
1
SSC disable
Selects PIPE
PIPE_16BIT
(PHY_STATUS)
S, I/O, PD
E3
0
16-bit PIPE SDR mode
Must be 0 at reset.
14
PIN DESCRIPTIONS
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Table 2-8. Strapping Options (continued)
SIGNAL NAME
ISO_START
(ULPI_DATA7)
TYPE
S, I/O, PD
BALL NO.
DESCRIPTION
N6
Active High. Puts PIPE into isolate mode. When in the isolate mode, TUSB1310A does
not respond to packet data present at TX_DATA15-0, TXDATAK1-0 inputs and presents
a high impedance on the PCLK, RX_DATA15-0, RX_DATAK1-0, RX_VALID outputs.
When in the isolate mode, the TUSB1310A will continue to respond to ULPI. Once the
isolate mode bit in ULPI register is cleared, the USB interfaces will start transmitting
packet data on TX_DATA15-0 and driving PCLK, RX_DATA15-0, RX_DATA1-0, and
RX_VALID.
Selects ULPI data bus bit width
ULPI_8BIT
(ULPI_DATA6)
S, I/O, PD
P6
0
8-bit ULPI SDR mode
Must be set to 0.
Select input reference clock frequency for on-chip oscillator
REFCLKSEL1,
REFCLKSEL0
(ULPI_DATA5,
ULPI_DATA4)
2.8
S, I/O, PD
N7
P7
00
20 MHz on XI
01
25 MHz on XI
10
30 MHz on XI
11
40 MHz on XI
USB Interfaces
Table 2-9. USB Interface Signal Name Descriptions
SIGNAL NAME
SSTXP
SSTXM
TYPE
O
SSRXP
I
SSRXM
DP
I/O
DM
VBUS
2.9
I
BALL NO.
H14
J14
E14
F14
P14
P13
N12
DESCRIPTION
USB SuperSpeed transmitter differential pair
USB SuperSpeed receiver differential pair
USB non-SuperSpeed differential pair
USB VBUS pin
Connected through an external voltage divider.
Special Connect
Table 2-10. Special Connect Signal Descriptions
SIGNAL NAME
TYPE
BALL NO.
DESCRIPTION
R1EXT
O
L14
High precision external resistor used for calibration. The R1 value shall be 10 kΩ ±1%
accuracy.
R1EXTRTN
I
L13
R1 ground reference. This pin is not connected to board ground.
VDDA1P1
P
M14
Needs a 1-µF bypass capacitor
D6
D5
C13
RSVD
I/O
C14
Must be left open.
K4
J4
A14
PIN DESCRIPTIONS
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2.10 Power and Ground
Table 2-11. Power/Ground Signal Descriptions
SIGNAL NAME
TYPE
BALL NO.
VDDA3P3
P
P12
VDDA1P8
P
DESCRIPTION
Analog 3.3-V power supply
N14
A13
Analog 1.8-V power supply
C10
C12
K14
VDDA1P1
G13
P
Analog 1.1-V power supply
G14
D14
C11
VDD1P8
VDD1P1
P
P
B2
C3
D4
D7
D8
D9
E4
F4
G4
H4
L5
L4
M3
L7
L8
L9
A5
A10
B6
B10
E1
F2
K2
L1
N5
P4
N10
P10
K13
D13
Digital IO 1.8-V power supply
Digital 1.1-V power supply
C4
VSSA
G
B14
B13
J13
H13
F13
E13
K12
L12
G12
Analog ground
D12
N13
M12
M13
VSSOSC
16
G
B12
Oscillator ground
If using a crystal, this should not be connected to PCB ground plane.
See Chapter 5 for guidelines.
If using an oscillator, this should be connected to PCB ground.
PIN DESCRIPTIONS
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Table 2-11. Power/Ground Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL NO.
F6
VSS
G
DESCRIPTION
F7
F8
F9
G6
G7
G8
G9
J6
J7
H6
H7
H8
H9
J8
J9
B11
F12
Digital ground
PIN DESCRIPTIONS
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3
FUNCTIONAL DESCRIPTION
3.1
Power On and Reset
The TUSB1310A has two hardware reset pins, a chip reset RESETN and a logic reset PHY_RESETN.
The RESETN is used only at Power On. The PHY_RESETN can be used as a functional reset. The ULPI
register also has a software reset.
Until all power sources are supplied, the OUT_ENABLE pin can control the output driver enable. After all
power sources are supplied, the chip reset RESETN and a ULPI soft reset will be asserted by the Link
Layer. The power up sequence is described in section 3.1.4
3.1.1
RESETN and PHY_RESETN – Hardware Reset
The RESETN sets all internal states to initial values. The Link Layer needs to hold the PHY in reset via
the RESETN until all power sources and the reference clock to the TUSB1310A are stable. All pins used
for strapping options must be set before RESETN de-assertion as they are latched by reset de-assertion.
All strapping option pins have internal pull-up or pull-down to set default values, but if any non-default
values are desired, they need to be controlled externally by the Link Layer Controller.
Table 3-1. Pin States in Chip Reset
3.1.2
PIPE CONTROL PIN NAME
STATE
VALUE
TX_DETRX_LPBK
Inactive
0
TX_ELECIDLE
Active
1
TX_ONESZEROS
Inactive
0
RX_POLARITY
Inactive
0
POWER_DOWN
U2
10b
TX_MARGIN2-0
Normal operating range
000b
TX_DEEMP
-3.5 dB
1
RATE
5.0 Gbps
1
TX_SWING
Full swing or half swing
0 or 1
RX_TERMINATION
Appropriate state
0 or 1
ULPI Reset – Software Reset
After power-up, the Link Layer Controller must set the Reset bit in ULPI register. It resets the core but
does not reset the ULPI interface or the ULPI registers.
During the ULPI reset, the ULPI_DIR is de-asserted. After the reset, the ULPI_DIR is asserted again and
the TUSB1310A sends an RX CMD update to the Link Layer. During the reset, the link should ignore
signals on the ULPI_DATA7-0 and must not access the TUSB1310A.
3.1.3
OUT_ENABLE - Output Enable
Digital IO buffers use two power supplies, core VDD1P1 and IO VDD1P8. During power up,
OUT_ENABLE must be asserted low for proper operation.
3.1.4
Power Up Sequence
The power up sequence is shown in Figure 3-1.
18
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Power Supplies
XI
RESETN
Internal latched
strapping pin states
Latched data
Internal resetn/
PLL_EN/SUSPENDM
PCLK
ULPI_CLK
PHY_STATUS/
ULPI_DIR
300 µs
Figure 3-1. Power-Up Sequence
After proper power supply sequencing, the reference clock on XI starts to operate. On the RESETN
deassertion, REFCLKSEL1-0 is determined depending on the PHY_MODE pins, PLL is locked and the
valid ULPI_CLK and the valid PCLK are driven.
After all stable clocks are provided, the TUSB1310A allows the Link Layer Controller to access by
deasserting the ULPI_DIR. The Link Layer Controller sets the Reset bit in the ULPI register. At the PIPE
interface, the PHY_STATUS changes from high to low in order to indicate the TUSB1310A is in the power
state specified by the POWER_DOWN signal. After the PHY_STATUS change, the TUSB1310A is ready
for PIPE transactions.
3.2
3.2.1
Clocks
Clock Distribution
A source clock should be provided via XI/XO from an external crystal or from a square wave clock. The
USB3.0 PLL provides a clock to the PIPE which drives 250 MHz. The USB2.0 PLL provides a 60-MHz
clock to the ULPI.
3.2.2
Output Clock
The CLKOUT is used by the Link Layer Controller or the MAC in low power mode. A 120-MHz clock is
available on the CLKOUT pin only in the USB U3 power state.
3.3
Power Management
The SuperSpeed USB power state transition is controlled by the PIPE POWER_DOWN[1-0] and the
Non-SuperSpeed USB power state is transitioned by setting suspendM bit in the ULPI Function control
register via the ULPI or by asserting the ULPI_STP.
FUNCTIONAL DESCRIPTION
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USB Power Management
The USB 3.0 specification improves power consumption by defining 4 power states, U0, U1, U2, and U3
while the PIPE specification defines P0, P1, P2 and P3. The POWER_DOWN pin states are mapped to
LTSSM states as described in Table 3-2. For all power state transitions, the Link Layer Controller must not
begin any operational sequences or further power state transitions until the TUSB1310A has indicated that
the internal state transition is completed.
Table 3-2. Power States
PIPE
POWER
STATE
USB POWER STATE
PCLK
PLL
TRANSMITTING
RECEIVING
PHY_STATUS
P0
U0, all other LTSSM
states
On
On
Active or Idle or LFPS
Active or Idle
A single cycle assertion
P1
U1
On
On
Idle or LFPS
Idle
A single cycle assertion
P2
U2, RxDetect,
SS.Inactive
On
On
Idle or LFPS or
RxDetect
Idle
A single cycle assertion
U3, SS.disabled
Off. The PIPE is in
an asynchronous
mode
Idle
PHY_STATUS is
asserted before PCLK is
turned off and
de-asserted when PCLK
is fully off.
P3
Off
LFPS or RxDetect
When the Link Layer Controller wants to transmit LFPS in P1, P2, or P3 state, it must de-assert
TX_ELECIDLE. The TUSB1310A generates valid LFPS until the TX_ELECIDLE is asserted. The Link
Layer Controller must assert TX_ELECIDLE before transitioning to P0.
When RX_ELECIDLE is de-asserted in P0, P1, P2, or P3, the TUSB1310A receiver monitors for LFPS
except during reset or when RX_TERMINATION is removed for electrical idle.
When the TUSB1310A is in P0 and is actively transmitting; only RX_POLARITY can be asserted.
Table 3-3. PIPE Control Pin Matrix
POWER STATE
P0
P1
P2
P3
20
TX_DETRX_LPBK
TX_ELECIDLE
DESCRIPTION
0
0
Transmitting data on TX_DATA.
0
1
Not transmitting and is in electrical idle
1
0
Goes into loopback mode
1
1
Transmits LFPS signaling
0
Transmits LFPS signaling
Don’t care
1
Not transmitting and is in electrical idle
Don’t care
0
Transmits LFPS signaling
0
1
Idle
1
1
Does a receiver detection operation
Don’t care
0
Transmits LFPS signaling
1
Does a receiver detection operation
FUNCTIONAL DESCRIPTION
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3.4
Receiver Status
The TUSB1310A has an elastic buffer for clock tolerance compensation, the Link Partner detection, and
some received data error detections. The receive data status from SSRXP/SSRXN differential pair
presents on RX_STATUS2-0. If an error occurs during a SKP ordered-set, the error signaling has
precedence. If more than one error occurs on a received byte, the errors have the priority below.
1. 8B/10B decode error
2. Elastic buffer overflow
3. Elastic buffer underflow (Can not occur in Nominal Empty buffer model)
4. Disparity error
3.4.1
Clock Tolerance Compensation
The receiver contains an elastic buffer used to compensate for differences in frequencies between bit
rates at the two ends of a Link. The elastic buffer must be capable of holding enough symbols to handle
worst case differences in frequency and worst case intervals between SKP ordered-sets. A SKP order-set
is a set of symbols transmitted as a group. The SKP ordered-sets allows the receiver to adjust the data
stream being received prevent the elastic buffer from either overflowing or under-flowing due to any clock
tolerance differences.
The TUSB1310A supports two models, Nominal Half Full buffer model and Nominal Empty buffer mode.
For the Nominal Half Full buffer model, the TUSB1310A monitors the receive data stream. When a Skip
ordered-set is received, the TUSB1310A adds or removes one SKP order set from each SKP to manage
its elastic buffer to keep the buffer as close to half full as possible. Only full SKP ordered sets are added
or removed. When a SKP order set is added, the TUSB1310A asserts an “Add SKP” code (001b) on the
RX_STATUS for one clock cycle. When a SKP order set is removed, the RX_STATUS is has a “Remove
SHP” code (010b).
For the Nominal Empty buffer model the TUSB1310A attempts to keep the elasticity buffer as close to
empty as possible. When no SKP ordered sets have been received, the TUSB1310A will be required to
insert SKP ordered sets into the received data stream.
Table 3-4. RX_STATUS - SKP
3.4.2
RX_STATUS2-0
SKP ADDITION OR REMOVAL
001b
1 SKP Ordered Set added
010b
1 SKP Ordered Set removed
LENGTH
One clock cycle
Receiver Detection
TX_DETRX_LPBK starts a receiver detection operation to determine if there is a receiver at the other end
of the link. When the receiver detect sequence completes, the PHY_STATUS is asserted for one clock
and drives the RX_STATUS signals to the appropriate code. Once the TX_DETRX_LPBK signal is
asserted, the Link Layer Controller must leave the signal asserted until the PHY_STATUS pulse. When
receiver detection is performed in P3, the PHY_STATUS shows the appropriate receiver detect value until
the TX_DETRX_LPBK is de-asserted.
Table 3-5. RX_STATUS - Receiver Detection
RX_STATUS2-0
DETECTED CONDITION
000b
Receiver not present
011b
Receiver present
LENGTH
One clock cycle
FUNCTIONAL DESCRIPTION
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8b/10b Decode Errors
When the TUSB1310A detects an 8b/10b decode error, it will assert a SUB symbol in the data on the
RX_DATA where the bad byte occurred. In the same clock cycle that the SUB symbol is asserted on the
RX_DATA, the 8b/10b decode error code (100b) will be asserted on the RX_STATUS. 8b/10b Decoding
error has priority over all other receiver error codes and could mask out a disparity error occurring on the
other byte of data being clocked onto the RX_DATA with the SUB symbol.
Table 3-6. 8b/10b Decode Errors
RX_STATUS2-0
100b
3.4.4
DETECTED ERROR
LENGTH
8B/10B Decode Error
Clock cycles during the ef fected byte is transferred on
RX_DATA15-0
Elastic Buffer Errors
When the elastic buffer overflows, data is lost during the reception of the data. The elastic buffer overflow
error code (101b) will be asserted on the RX_STATUS on the PCLK cycle the omitted data would have
been asserted. The data asserted on the RX_DATA is still valid data, the elastic buffer overflow error code
on the RX_STATUS just marks a discontinuity point in the data stream being received.
When the elastic buffer underflows, SUB symbols are inserted into the data stream on the RX_DATA to fill
the holes created by the gaps between valid data. For every PCLK cycle a SUB symbol is asserted on the
RX_DATA, an elastic buffer underflow error code (111b) is asserted on the RX_STATUS. In Nominal
Empty buffer mode, SKP ordered sets are transferred on RX_DATA and the underflow is not signaled.
Table 3-7. Elastic Buffer Errors
3.4.5
RX_STATUS2-0
DETECTED ERROR
LENGTH
101b
Elastic Buffer overflow
Clock cycles the omitted data would have appeared
110b
Elastic Buffer underflow.
Clock cycles during the SUB symbol presence on
RX_DATA15-0
Disparity Errors
When the TUSB1310A detects a disparity error, it will assert a disparity error code (111b) on the
RX_STATUS in the same PCLK cycle it asserts the erroneous data on the RX_DATA. The disparity code
does not discern which byte on the RX_DATA is the erroneous data.
Table 3-8. Disparity Errors
3.5
RX_STATUS2-0
DETECTED ERROR
LENGTH
111b
Disparity Error
Clock cycles during the ef fected byte is transferred
on RX_DATA15-0
Loopback
The TUSB1310A begins an internal loopback operation from SSRXP/SSRXN differential pairs to
SSTXP/SSTXN differential pairs when the TX_DETRX_LPBK is asserted while holding TX_ELECIDLE
de-asserted. The TUSB1310A will stop transmitting data to the SSTXP/SSTXN signaling pair from the
TX_DATA and begin transmitting on the SSTXP/SSTXN signaling pair the data received at the
SSRXP/SSRXN signaling pair. This data is not routed through the 8b/10b coding/encoding paths. While in
the loopback operation, the received data is still sent to the RX_DATA. The data sent to the RX_DATA is
routed through the 10b/8b decoder.
The TX_DETRX_LPBK de-assertion will terminate the loopback operation and return to transmitting
TX_DATA over the SSTXP/SSTXN signaling pair. The TUSB1310A only transitions out of loopback on
detection of LFPS signaling by transitioning to P2 state and starting the LFPS handshake.
22
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3.6
Adaptive Equalizer
The adaptive equalizer dynamically adjusts the forward gain and peaking of the analog equalizer to
minimize the jitter at the cross over point of the eye diagram. This allows for greater jitter tolerance in the
RX.
FUNCTIONAL DESCRIPTION
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4
REGISTERS
4.1
Register Definitions
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Table 4-1. Register Definitions
ACCESS CODE
EXPANDED NAME
Rd
Read
Register can be read. Read-only if this is the only mode given.
Wr
Write
Pattern on the data bus will be written over all bits of the register.
S
Set
Pattern on the data bus is OR’s with and written into the register.
C
Clear
4.2
DESCRIPTION
Pattern on the data bus is a mask. If a bit in the mask is set, then the
corresponding register bit will be set to zero (cleared).
Register Map
The TUSB1310A contains the ULPI registers consisting of an immediate register set and an extended
register set.
Table 4-2. Register Map
ADDRESS (6 BITS)
REGISTER NAME
Rd
Wr
Set
Clr
04h
05h
06h
IMMEDIATE REGISTER SET
Vendor ID Low
00h
Vendor ID High
01h
Product ID Low
02h
Product ID High
03h
Function Control
04h-06h
Interface Control
07h-09h
07h
08h
09h
OTG Control
0Ah-0Ch
0Ah
0Bh
0Ch
USB Interrupt Enable Rising
0Dh-0Fh
0Dh
0Eh
0Fh
USB Interrupt Enable Falling
10h-12h
10h
11h
12h
USB Interrupt Status
13h
13h
USB Interrupt Latch
14h
14h
Debug
15h
17h
18h
Scratch Register
16h-18h
Reserved
19h-2Eh
4.2.1
16h
Vendor ID and Product ID (00h-03h)
Table 4-3. Vendor ID and Product ID
24
ADDRESS
BITS
NAME
ACCESS
RESET
00h
01h
DESCRIPTION
7:00
Vendor ID Low
Rd
51h
Lower byte of Vendor ID supplied by USB-IF
7:00
Vendor ID High
Rd
04h
Upper byte of Vendor ID supplied by USB-IF
02h
7:00
Product ID Low
Rd
10h
Lower byte of Vendor ID supplied by Vendor
03h
7:00
Product ID High
Rd
13h
Upper byte of Vendor ID supplied by Vendor
REGISTERS
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4.2.2
Function Control (04h-06h)
Address: 04h-06h (Read), 04h (Write), 05h (Set), 06h (Clear)
Table 4-4. Function Control
BITS
1:0
2
4:3
5
NAME
XcvrSelect
TermSelect
OpMode
Reset
ACCESS
Rd/Wr/S/C
Rd/Wr/S/C
Rd/Wr/S/C
Rd/Wr/S/C
RESET
DESCRIPTION
1h
Selects the required transceiver speed 00b : Enable HS
transceiver
01b: Enable FS transceiver
10b: Enable LS transceiver
11b: Enable FS transceiver for LS packets
(FS preamble is automatically pre-pended)
0
Controls the internal 1.5-kΩ pullup resister and 45-Ω HS
terminations. Control over bus resistors changes depending
on XcvrSelect, OpMode, DpPulldown and DmPulldown. Since
low speed peripherals never support full speed or hi-speed,
providing the 1.5 kΩ on DM for low speed is optional.
00
Selects the required bit encoding style during transmit
00 : Normal operation
01: Non-driving
10: Disable bit-stuff and NRZI encoding
11: Do not automatically add SYNC and EOP when
transmitting. Must be used only for HS packets.
0
Active High transceiver reset. After the Link sets this bit, the
TUSB1310A must assert the ULPI_DIR and reset the ULPI.
When the reset is completed, the PHY de-asserts the
ULPI_DIR and automatically clears this bit. After de-asserting
the ULPI_DIR, the PHY must re-assert the ULPI_DIR and
send an RX CMD update on the Link Layer Controller. The
Link Layer Controller must wait for the ULPI_DIR to deassert before using the ULPI bus. Does not reset the ULPI or
ULPI register set.
6
SuspendM
Rd/Wr/S/C
1h
Active low PHY suspend. Put the TUSB1310A into Low
Power Mode. The PHY can power down all blocks except the
full speed receiver, OTG com-parators, and the ULPI pins.
The PHY must auto-matically set this bit to 1 when Low
Power Mode is exited.
0: Low Power Mode
1: Powered
7
Reserved
Rd
0
Reserved
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Interface Control (07h-09h)
Address: 07-09h (Read), 07h (Write), 08h (Set), 09h (Clear)
Table 4-5. Interface Control
BITS
NAME
ACCESS
RESET
0
Reserved
Rd
0b
Reserved, only write a 0 to this bit.
DESCRIPTION
1
Reserved
Rd
0b
Reserved, only write a 0 to this bit.
2
Reserved
Rd
0h
Reserved
3
ClockSuspendM
Rd/Wr/S/C
0b
Active low clock suspend. Valid only in Serial Mode. Powers
down the internal clock circuitry only. Valid only when
SuspendM = 1. The TUSB1310A must ignore ClockSuspend
when SuspendM = 0. By default, the clock will not be
powered in Serial Mode.
0 : Clock will not be powered in Serial Mode
1 : Clock will be powered in Serial Mode
6:4
Reserved
Rd
0h
Reserved
7
Interface
Protect Disable
0
Controls internal pullups and pulldowns on the ULPI_STP and
the ULPI_DATA for protecting the ULPI when the Link Layer
Controller tri-states the signals.
0 Enables the pullup and pulldown
1 Disables the pullup and pulldown
4.2.4
Rd/Wr/S/C
OTG Control
Address: 0Ah-0Ch (Read), 0Ah (Write), 0Bh (Set), 0Ch (Clear). Controls UTMI+ OTG functions of the
PHY.
Table 4-6. OTG Control Register
BITS
NAME
ACCESS
RESET
0
Reserved
Rd
0b
This bit is not implemented and returns a 0b when read.
1
DpPulldown
Rd/Wr/S/C
1b
Enables the 15-kΩ pull-down resistor on D+.
0 Pull-down resistor not connected to D+
1 Pull-down resistor connected to D+
2
DmPulldown
Rd/Wr/S/C
1h
Enables the 15-kΩ pull-down resistor on D-.
0 Pull-down resistor not connected to D1 Pull-down resistor connected to D-
7:3
Reserved
Rd
0h
These bits are not implemented and return zeros when read.
4.2.5
DESCRIPTION
USB Interrupt Enable Rising (0Dh-0Fh)
Address: 0D-0Fh (Read), 0Dh (Write), 0Eh (Set), 0Fh (Clear)
Table 4-7. USB Interrupt Enable Rising
BITS
0
26
NAME
Hostdisconnect Rise
ACCESS
Rd/Wr/S/C
RESET
DESCRIPTION
1b
Generate an interrupt event notification when Hostdisconnect
changes from low to high Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
REGISTERS
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4.2.6
USB Interrupt Enable Falling (10h-12h)
Address: 10-12h (Read), 10h (Write), 11h (Set), 12h (Clear)
Table 4-8. USB Interrupt Enable Falling
BITS
0
NAME
Hostdisconnect Fall
4.2.7
ACCESS
Rd/Wr/S/C
RESET
DESCRIPTION
1b
Generate an interrupt event notification when Host-disconnect
changes from high to low. Applicable only in host.
USB Interrupt Status (13h)
Address: 13h (Read-only)
Table 4-9. USB Interrupt Status
BITS
0
NAME
Hostdisconnect Fall
4.2.8
ACCESS
Rd/Wr/S/C
RESET
DESCRIPTION
1b
Generate an interrupt event notification when Host-disconnect
changes from high to low. Applicable only in host.
USB Interrupt Latch (14h)
Address: 14h (Read-only with auto-clear)
Table 4-10. USB Interrupt Latch
BITS
NAME
ACCESS
RESET
0
Hostdisconnect Fall
Rd/Wr/S/C
1b
4.2.9
DESCRIPTION
Set to 1b by the PHY when an unmasked event occurs on
Hostdisconnect. Cleared when this register is read.
Applicable only in host mode.
Debug (15h)
Address: 15h (Read-only)
Table 4-11. Debug
BITS
NAME
ACCESS
RESET
0
LineState0
Rd
0
Contains the current value of LineState0
DESCRIPTION
1
LineState1
Rd
0
Contains the current value of LineState1
7:2
Reserved
Rd
0
Reserved
4.2.10 Scratch Register (16-18h)
Address: 16-18h (Read), 16h (Write), 17h (Set), 18h (Clear)
Table 4-12. Scratch Register
BITS
7:0
NAME
Scratch
ACCESS
Rd/Wr/S/C
RESET
00
DESCRIPTION
Empty register byte for testing purposes. Software can read,
write, set, and clear this register and the TUSB1310A
functionality will not be affected.
REGISTERS
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5
DESIGN GUIDELINES
5.1
Chip Connection on PCB
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Components should be placed close to the TUSB1310A to reduce the trace length of the interface
between the components and the TUSB1310A. If external capacitors can not accommodate a close
placement, shielding to ground is recommended.
SSTXN
SSTXP
SSRXN
SSRXP
USB Connector
DP
DM
VBUS
90.9K W ± 1 %
10KW ± 1%
R1EXT
JTAG
JTAG
10KW ± 1%
R1 EXTRTN
XI
Crystal
Connection
VSSOSC
XO
PIPE RX
ULPI
PIPE TX
Link Controller
Figure 5-1. Analog Pin Connections
5.1.1
USB Connector Pins Connection
Differential pair signals, DP/DM, SSTXP/SSTXN, SSRXP/SSRXN, should be kept as short as possible.
The differential pair traces should be trace-length matched and parallelism should be maintained. They
also need to minimize vias and corners and should avoid crossing plane splits and stubs.
Figure 5-2 and Figure 5-3 are for visual reference only.
28
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90.9 kW ±1%
10 kW ±1%
Figure 5-2. USB Standard-A Connector Pin Connection
90.9 kW ±1%
10 kW ±1%
Figure 5-3. USB Standard-B Connector Pin Connection
5.1.2
Clock Connections
The TUSB1310A supports an external oscillator source or a crystal unit. If a clock is provided to XI instead
of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow the guidelines
below.
Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short
as possible and away from any switching leads. It is also recommended to minimize the capacitance
between XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external
capacitors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be
connected to PCB ground.
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Load capacitance (CLOAD) of the crystal varying with the crystal vendors is the total capacitance value of
the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and
CL2 in Figure 5-4. The trace length between the decoupling capacitors and the corresponding power pins
on the TUSB1310A needs to be minimized. It is also recommended that the trace length from the
capacitor pad to the power or ground plane be minimized.
VDDO1P1
VDD1P1
CL1
·
XI
·
VSSOSC
Crystal
·
XO
CL2
VDD1P8
VDDO1P8
VSSO
Figure 5-4. Typical Crystal Connections
5.2
Clock Source Requirements
5.2.1
Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the
transmit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing
system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock
detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter
reference clock is required to achieve compliance with supported USB3.0 standards. For example,
USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random
phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of
additional jitter components, the Reference Clock jitter must be considerably below the overall jitter
budget.
5.2.2
Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating.
Table 5-1. Oscillator Specification
MAX
UNITS
Frequency tolerance
PARAMETER
±50
ppm
Operational temperature
Frequency stability
±50
ppm
1 year aging
Rise/Fall time
6
nsec
20% - 80%
Reference clock RJ
with JTF (1 sigma) (1) (2)
(1)
(2)
30
MIN
TYP
0.8
CONDITION
psec
Sigma value assuming Gaussian distribution
After application of JTF
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Table 5-1. Oscillator Specification (continued)
PARAMETER
MIN
TYP
MAX
UNITS
Reference clock TJ
with JTF (total p-p) (2) (3)
25
psec
Reference clock jitter
(absolute p-p) (4)
50
psec
(3)
(4)
CONDITION
Calculated as 14.1 x RJ + DJ
Absolute phase jitter (p-p)
5.2.3
Crystal
Either a 20-MHz, 25-MHz, 30-MHz, or 40-MHz crystal can be selected. A parallel, 20-pF load crystal
should be used if a crystal source is used.
Table 5-2. Crystal Specification
PARAMETER
MIN
TYP
Frequency tolerance
Frequency stability
Load capacitance
12
20
MAX
UNITS
±50
ppm
Operational temperature
CONDITION
±50
ppm
1 year aging
24
pF
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6
ELECTRICAL SPECIFICATIONS
6.1
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDD1P1 steady-state supply voltage
–0.3 to 1.4
V
VDD1P8 steady-state supply voltage
–0.3 to 2.45
V
VDDA1P1 steady-state supply voltage
–0.3 to 1.4
V
VDDA1P8 steady-state supply voltage
–0.3 to 2.45
V
VDDA3P3 steady-state supply voltage
–0.3 to 3.8
V
6.2
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
2.97
3.3
3.63
V
Analog 1.8 supply voltage
1.71
1.8
1.98
V
Analog 1.1 supply voltage
1.045
1.1
1.155
V
1.62
1.8
1.98
V
1.045
1.1
1.155
V
VDDA3P3
Analog 3.3 supply voltage
VDDA1P8
VDDA1P1
VDD1P8
Digital IO 1.8 supply voltage
VDD1P1
Digital 1.1 supply voltage
VBUS
Voltage at VBUS PAD
TA
TJ
0
1.155
V
Operating free-air temperature range
-40
85
°C
Operating junction temperature range
-40
105
°C
Human body model (HBM)
ESD
6.3
2000
Charged device model (CDM)
V
500
DC CHARACTERISTICS for 1.8-V DIGITAL IO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
VOL
Vhys
MIN
TYP
MAX
0.65 VDDS
VDDS - 0.45
IO = -2 mA,
VDDS = 1.4 V to 1.6 V,
driver enabled, pullup or
pulldown disabled
0.75 VDDS
0.45
IO = 2 mA,
VDDS = 1.4 V to 1.6 V,
driver enabled, pullup or
pulldown disabled
0.25 VDDS
V
100
ELECTRICAL SPECIFICATIONS
V
V
IO = 2 mA,
VDDS = 1.62 V to 1.98 V,
driver enabled, pullup or
pulldown disabled
Any receiver, including those
with a pullup or pulldown. The
pullup or pulldown must be
disabled.
UNIT
V
0.35 VDDS
IO = -2 mA,
VDDS = 1.62 V to 1.98 V,
driver enabled, pullup or
pulldown disabled
Input hysteresis
II
32
TEST CONDITIONS
270
mV
±1
µA
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DC CHARACTERISTICS for 1.8-V DIGITAL IO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II(PUon)
IOZ
MIN
TYP
Receiver/pullup only, pullup
enabled (not inhibited),
VPAD = 0 V
-47 to -169
Receiver/pullup only, pullup
enabled (not inhibited)
–100
MAX
UNIT
µA
Driver only, driver disabled
(1)
±20
µA
±20
µA
IZ
See
VTX_DIFF_SS
SSTXP/SSTXN differential
p-p TX voltage swing
0.8
1.2
V
RTX_DIFF_DC
DC differential impedance
72
120
Ω
VTX_RCV_DET
The amount of voltage
change allowed during
receiver detection
0.6
V
CAC_COUPLING
AC coupling capacitor
75
200
nF
RRX_DC
Receiver DC common
mode impedance
18
30
Ω
RRX_DIFF_DC
DC differential impedance
72
120
Ω
VRX_LFPS_DET
LFPS detect threshold
100
300
mV
100
mV
10
mV
1200
mV
VCM_AC_LFPS
VCM_LFPS_active
VTX_DIFF_PP_LFPS
(1)
800
IZ is the total leakage current through the PAD connection of a driver/receiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
DEVICE POWER CONSUMPTION (1)
6.4
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VDDA3P3 power consumption
13
mW
VDDA1P8 power consumption
77
mW
VDDA1P1 power consumption
118
mW
VDD1P1 power consumption
98
mW
VDD1P8 power consumption
128
mW
(1)
Power consumption condition is transmitting and/or receiving (in U0) at 25°C and nominal voltages.
6.5
6.5.1
AC Characteristics
Power Up and Reset Timing
The TUSB1310A does not drive signals on any strapping pins before they are latched internally.
ELECTRICAL SPECIFICATIONS
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VDD1P8 and
Analog Power Supplies
XI
OUT_ENABLE
ULPI_DIR
VDD1P1
Tcfgin1
RESETN
Latch-In of Hardware
Strapping Pins
Tcfgin2
Drive Output
Strapping pins
Figure 6-1. Power Up and Reset Timing
Table 6-1. Power Up and Reset Timing
SYMBOL
MIN
Hardware configuration latch-in time from RESETN
DESCRIPTION
Tcfgin1
0
Time from RESETN to driver outputs on strapping pins
Tcfgin2
0
ns
1
µs
RESETN pulse width
RESETN to PHY_STATUS de-assertion
6.5.2
TYP
MAX
UNITS
ns
µs
300
PIPE Transmit
Figure 6-2. PIPE Transmit Timing
Table 6-2. PIPE Transmit Timing
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNITS
TX_CLK period
Tcyc2
4
TX_CLK duty cycle
Tdty2
50
Data setup to TX_CLK rise and TX_CLK fall (1)
Tsu2
1
ns
Data hold to TX_CLK rise and TX_CLK fall (1)
Thd2
0
ns
(1)
34
ns
%
This includes TX_DATA15-0, TX_DATAK1-0, TX_ONESZEROS, RATE, TX_DEEMPTH, TX_DETRX_LPBK, TX_ELECIDLE,
TX_MARGIN, TX_SWING, RX_POLARITY, POWER_DOWN1-0.
ELECTRICAL SPECIFICATIONS
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6.5.3
PIPE Receive
Tcyc3
PCLK
Tdly3
RX_DATA15-0
RX_DATAK1-0
RX_VALID
RX_STATUS2-0
PHY_STATUS
Valid Data
Figure 6-3. PIPE Receive Timing
Table 6-3. PIPE Receive Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
Tcyc3
PCLK Period
4
ns
Tdty3
PCLK Duty Cycle
50
%
Tdly3
PCLK rise and fall to RX_DATA15-0, RX_DATAK1-0, RX_VALID,
RX_STATUS2-0, PHY_STATUS Delay (1) (2)
(1)
(2)
1
2
ns
Output Load max = 10 pF, min = 5 pF
Timing is relative to the 50% transition point, not VIH/VIL.
6.5.4
ULPI Parameters
Table 6-4. ULPI Parameters
DESCRIPTION
NOTES
FS
LS
UNIT
RX CMD delay
2-4
2-4
2-4
clocks
TX start delay
1-2
1-10
1-10
clocks
TX end delay
PHY pipeline delays
2-5
clocks
RX start delay
3-8
RX end delay
3-8
17-18
122-123
clocks
Transmit-Transmit (host only)
15-24
7-18
77-247
clocks
1-14
7-18
77-247
clocks
Link decision times
Receive-Transmit (host or peripheral)
6.5.5
HS
clocks
ULPI Clock
Table 6-5. ULPI Clock Parameters
DESCRIPTION
SYMBOL
Frequency (first transition) ±10%
Fstart_8bit
Frequency (steady state) ±500 ppm
Fsteady
Duty cycle (first transition) ±10%
Dstart_8bit
MIN
TYP
MAX
UNITS
54
60
66
MHz
59.97
60
60.03
MHz
40
50
60
%
49.97 5
50
50.02 5
%
Duty cycle (steady state) ±500 ppm
Dsteady
Time to reach steady state frequency and duty cycle after
first transition
Tsteady
1.4
ms
Clock startup time after deassertion of SuspemdM –
Peripheral
Tstart_dev
5.6
ms
Clock startup time after deassertion of SuspemdM – Hold
Tstart_host
ms
PHY preparation time after first transition of input clock
Tprep
µs
Jitter
Tjitter
ps
ELECTRICAL SPECIFICATIONS
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Table 6-5. ULPI Clock Parameters (continued)
DESCRIPTION
SYMBOL
Rise and fall time
6.5.6
MIN
TYP
MAX
UNITS
Trise/Tfall
ns
ULPI Transmit
ULPI_CLK
Tsc8
Thc8
Tsd8
Thd8
ULPI_STP
ULPI_DATA7-0 In
(8-bit)
Valid Data
Tsdd8 Thdd8
Tsdd8 Thdd8
Figure 6-4. ULPI Transmit Timing
Table 6-6. ULPI Transmit Timing
DESCRIPTION
SYMBOL
ULPI_STP setup time
Tsc8, Tsd8
ULPI_STP hold time
Thc8, Thd8
6.5.7
MIN
TYP
MAX
UNITS
6
0
ns
ns
ULPI Receive Timing
ULPI_CLK
Tdc9
Tdc9
ULPI_DIR
ULPI_NXT
Tdd9
ULPI_DATA7-0 Out
Valid Data
(8-bit)
Tddd9
Tddd9
Figure 6-5. ULPI Receive Timing
Table 6-7. ULPI Receive Timing
DESCRIPTION
ULPI_DIR/ULPI_NXT/ULPI_DATA7-0
(1)
36
SYMBOL
(1)
Tdc9, Tdd9
MIN
TYP
MAX
UNITS
9
ns
Output Load max = 10 pF, min = 5 pF
ELECTRICAL SPECIFICATIONS
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6.5.8
Power State Transition Time
The P1 to P0 transition time is the amount of time for the TUSB1310A to return to P0 state, after having
been in the P1 state. This time is measured from when the MAC sets the POWER_DOWN signals to P0
until the TUSB1310A asserts PHY_STATUS. The TUSB1310A asserts PHY_STATUS when it is ready to
begin data transmission and reception.
The P2 to P0 transition time is the amount of time for the TUSB1310A to return to the P0 state, after
having been in the P2 state. This time is measured from when the MAC sets the POWER_DOWN signals
to P0 until the TUSB1310A asserts PHY_STATUS. The TUSB1310A asserts PHY_STATUS when it is
ready to begin data transmission and reception.
The P3 to P0 transition time is the amount of time for the TUSB1310A to go to P0 state, after having been
in the P3 state. Time is measured from when the MAC sets the POWER_DOWN signals to P0 until the
TUSB1310A deasserts PHY_STATUS. The TUSB1310A asserts PHY_STATUS when it is ready to begin
data transmission and reception.
ELECTRICAL SPECIFICATIONS
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PACKAGE OPTION ADDENDUM
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18-May-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TUSB1310AZAY
ACTIVE
NFBGA
ZAY
175
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TUSB1310AZAYR
ACTIVE
NFBGA
ZAY
175
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TUSB1310AZAYR
Package Package Pins
Type Drawing
NFBGA
ZAY
175
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
12.35
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
12.35
2.3
16.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB1310AZAYR
NFBGA
ZAY
175
1000
333.2
345.9
41.3
Pack Materials-Page 2
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www.ti.com/audio
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amplifier.ti.com
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www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
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Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
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www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
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www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
Wireless
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions
www.ti.com/lprf
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