SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 Dual Channel USB3.0 Redriver/Equalizer Check for Samples: SN65LVPE502 FEATURES 1 • • • • • • • Single Lane USB 3.0 Equalizer/Redriver Selectable Equalization, De-emphasis and Output Swing Control Integrated Termination Hot-Plug Capable Receiver Detect Low Power: – 315mW(TYP), VCC = 3.3V Auto Low Power Modes: – 5mW (TYP) When no Connection Detected – 70mW (TYP) When in U2/U3 Mode • • • Excellent Jitter and Loss Compensation Capability: to 24" – 24" of 6 mil Stripline on FR4 – 12" on Input and 4m, 26AWG USB 3.0 Cable on Output Small foot print – 24 Pin (4mm × 4mm) QFN Package High Protection Against ESD Transient – HBM: 5,000 V – CDM: 1,500 V – MM: 200 V APPLICATIONS • Notebooks, Desktops, Docking Stations, Backplane and Cabled Application DESCRIPTION The SN65LVPE502 is a dual channel, single lane USB 3.0 redriver and signal conditioner supporting data rates of 5.0Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes. Programmable EQ, De-Emphasis and Amplitude Swing The SN65LVPE502 is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The SN65LVPE502 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as shown in Table 2. Low Power Modes The device supports three low power modes as described below. 1. Sleep Mode Initiated anytime EN_RXD undergoes a high to low transition or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100µs max. 2. RX Detect Mode – When no remote device is connected Anytime SN65LVPE502 detects a break in link (i.e., when upstream device is disconnected) or after powerup fails to find a remote device, SN65LVPE502 goes to Rx Detect mode and conserves power by shutting down majority of the internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx Detect mode device power is <10mW(TYP) or less than 5% of its normal operating power This feature is useful in saving system power in mobile applications like notebook PC where battery life is critical. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to normal operating mode. This operation requires no setting to the device. 3. U2/U3 Mode With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3, in these modes link is in electrical idle state. SN65LVPE502 will selectively turn-off internal circuitry to save on power. Typical power saving is about 75% lower than normal operating mode. The device will automatically revert to active mode when signaling activity (LFPS) is detected. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED Receiver Detection RX.Detect cycle is performed by first setting Rx termination for each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of each TX. If receiver is detected on both channel: • The TX and RX terminations are switched to ZDIFF-TX, ZDIFF-RX, respectively If • • • no receiver is detected on one or both channels: The transmitter is pulled to Hi-Z The channel is put in low power mode Device attempts to detect Rx termination in 12 ms (TYP) interval until termination is found or the device is put in sleep mode. USB Compliance Mode The device enters USB compliance mode when both EN_RXD and CM pins are set H. This mode is used to test the transmitter for compliance to voltage and timing specifications per USB 3.0 compliance specs. In this mode each channel will maintain its low-impedance termination RDC-RX, while auto Rx detect operation in the device is disabled. Electrical Idle Support The electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE502 detects an electrical idle state when RX± voltage at the device pin falls below VRX_IDLE_DIFFpp min. After detection of an idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VRX_IDLE_DIFFpp max normal operation is restored and output start passing input signal. The electrical idle exit and entry time is specified at ≤6 ns. 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 Main PCB Redriver USB Host USB Connector 20" Main PCB USB Host Connector Device PCB Device Redriver 20" Cable 1"-6" Figure 1. Typical Application Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 3 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com CM/EN_RXD RX1- TX1+ Receiver/ Equalizer CHANNEL 1 Driver TX1- EQ1 EQ CNTRL EQ2 DE1 VTX_CM_DC DEMP CNTRL DE2 TX2+ CHANNEL 2 Driver Receiver/ Equalizer TX2VTX_CM_DC Detect Dual Termination RX1+ Dual Termination Detect RX2+ RX2- OS Cntrl. CM/EN_RXD OS1 OS2 Figure 2. Data FLow Block Diagram 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 BOTTOM VIEW VCC EQ1 DE1 OS1 EN_RXD GND 1 NC 6 SN65LVPE502 24 7 NC TX1- RX1CH1 RX1+ TX1+ Thermal Pad (must be soldered to GND plane) GND GND RX2- TX2CH2 12 TX2+ RX2+ 19 13 18 GND EQ2 DE2 OS2 CM VCC TOP VIEW GND EN_RXD OS1 DE1 EQ1 VCC 6 NC 1 SN65LVPE502 7 24 NC TX1- RX1CH1 RX1+ TX1+ Thermal Pad (must be soldered to GND plane) GND TX2TX2+ GND RX2- CH2 CH2 CH2 12 19 RX2+ 13 VCC CM 18 OS2 DE2 EQ2 GND Figure 3. Flow-Through Pin-Out Table 1. Pin Description PIN NUMBER NAME I/O TYPE DESCRIPTION HIGH SPEED DIFFERENTIAL I/O PINS 8 RX1– I, CML 9 RX1+ I, CML 20 RX2– I, CML 19 RX2+ I, CML 23 TX1– O, CML 22 TX1+ O, CML 11 TX2– O, CML 12 TX2+ O, CML Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an internal voltage bias by dual termination resistor circuit Non-inverting and inverting CML differential output for CH 1 and CH 2. These pins are internally tied to voltage bias by termination resistors Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 5 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com Table 1. Pin Description (continued) PIN DEVICE CONTROL PIN 5 EN_RXD I, LVCMOS Sets device operation modes per Table 2. Internally pulled to VCC 14 CM I, LVCMOS Sets device in compliance mode when pulled to VCC, internally pulled to GND 7,24 NC Pads not internally connected EQ CONTROL PINS (1) 3,16 DE1, DE2 I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 2. Internally tied to VCC/2 2,17 EQ1, EQ2 I, LVCMOS Selects equalization settings for CH 1 and CH 2 per Table 2. Internally tied to VCC/2 4, 15 OS1, OS2 I, LVCMOS Selects output amplitude for CH 1 and CH 2 per Table 2. Internally tied to VCC/2 1,13 VCC Power Positive supply should be 3.3V ± 10% 6,10,18,21 GND Power Supply ground POWER PINS (1) Internally biased to VCC/2 with >200kΩ pull-up/pull-down. When pins are left as NC board leakage at this pin pad must be < 1 µA otherwise drive to VCC/2 to assert mid-level state. Table 2. Signal Control Pin Setting OSx (1) TRANSITION BIT AMPLITUDE (TYP mVpp) NC (default) 1000 0 870 1 1085 EQx (1) EQUALIZATION dB NC (default) 0 0 7 1 DEx (1) (1) 15 OSx (1) = NC OSx (1) =0 OSx (1) = 1 NC –3.5 dB –2.2 dB –4.4 dB 0 –6.0 dB –5.2 dB –6.0 dB 1 –8.5 dB –8.9 dB –7.6 dB EN_RXD DEVICE FUNCTION 1 (default) Normal operating mode 0 Sleep mode CM DEVICE FUNCTION 0 (default) Normal Mode 1 Compliance mode Applies to Channel 1 and Channel 2 at 2.5 GHz. USB Device USB Host Device PCB 8"-20" 2"-6" Up to 3m (30AWG) 1"-6" Figure 4. Redriver Placement Example 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PCAKAGE SN65LVPE502RGER LVPE502 24-pin RGE Reel (large) SN65LVPE502RGET LVPE502 24-pin RGE Reel (small) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNITS / VALUES Supply Voltage Range (2) VCC –0.5 V to 4 V Differential I/O Voltage Range –0.5 V to 4 V Control I/O Electrostatic discharge –0.5 V to VCC + 0.5V Human Body Model (3) ±5000V Charged Device Model (4) ±1500V Machine Model (5) ±200V Continuous power dissipation (1) (2) (3) (4) (5) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101-A. Tested in accordance with JEDEC Standard 22, Test Method A115-A. PACKAGE CHARACTERIZATION over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN PD Device power dissipation CM, EN_RXD, EQ cntrl pins = NC, K28.5 pattern at 5 Gbps, VID = 1000 mVpp PSD Device power dissipation under low power mode EN_RXD= GND TYP MAX UNIT 330 450 mW 0.3 1 mW THERMAL INFORMATION SN65LVPE502 THERMAL METRIC (1) RGE UNITS 24 PINS qJA Junction-to-ambient thermal resistance (2) qJC(TOP) Junction-to-case(top) thermal resistance qJB Junction-to-board thermal resistance 46 (3) 42 (4) 13 (5) yJT Junction-to-top characterization parameter yJB Junction-to-board characterization parameter qJC(BOTTOM) (1) (2) (3) (4) (5) (6) (7) Junction-to-case(bottom) thermal resistance 0.5 (6) (7) °C/W 9 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 7 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC Supply Voltage CCOUPLING AC Coupling Capacitor Operating free-air temperature MIN TYP MAX 3 3.3 3.6 UNIT V 75 200 nF 0 85 °C DEVICE POWER The SN65LVPE502 is designed to operate from a single 3.3 V supply. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 100 120 UNIT DEVICE PARAMETERS EN_RXD, CM, EQ cntrl = NC, K28.5 pattern at 5 Gbps, VID = 1000 mVpp ICC ICCRx.Detect In Rx.Detect mode Supply Current ICCsleep EN_RXD = GND ICCU2-U3 Link in USB low power state 2 5 mA 0.1 21 Maximum Data Rate 5 tENB Device Enable Time Sleep mode exit time EN_RXD L→ H With Rx termination present tDIS Device Disable Time Sleep mode entry time EN_RXD H→ L TRX.DETECT Rx.Detect Start Event Power-up time Gbps 100 µs 2 µs 100 µs VCC V CONTROL LOGIC (under recommended operating conditions) VIH High level Input Voltage 1.4 VIL Low Level Input Voltage –0.3 VHYS Input Hysteresis 0.5 150 OSx, EQx, DEx = VCC IIH High Level Input Current 30 EN_RXD = VCC 1 CM = VCC IIL Low Level Input Current V mV µA 30 OSx, EQx, DEx = GND –30 EN_RXD = GND –30 CM = GND µA –1 RECEIVER AC/DC AC coupled differential RX peak to peak signal Vindiff_pp RX1, RX2 Input Voltage Swing VCM_RX RX1, RX2 Common Mode Voltage VinCOM_P RX1, RX2 AC Peak common mode voltage ZDC_RX DC common mode impedance 18 Zdiff_RX DC differential input impedance 72 1200 50 85 3.3 Measured at Rx pins with termination enabled Device in sleep mode Rx termination not powered. Measured with respect to GND over 500mV max ZRX_High_IMP+ DC Input High Impedance VRX-LFPS-DETpp Measured at receiver pin, below minimum Low Voltage Periodic Signaling (LFPS) output is squelched, above max input signal Detect Threshold is passed to output RLRX-DIFF Differential Return Loss RLRX-CM Common Mode Return Loss 8 100 mVP 26 30 Ω 80 120 Ω 100 kΩ 300 10 11 1.25 GHz – 2.5 GHz 6 7 11 13 Submit Documentation Feedback V 150 50 MHz – 1.25 GHz 50 MHz – 2.5 GHz mVpp mVpp dB dB Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX RL =100Ω +1%, DEx, OSx = NC, Transition Bit 800 1000 1200 UNIT TRANSMITTER AC/DC VTXDIFF_TB_PP Differential peak-to-peak Output Voltage (VID = 800, 1200 mVpp, 5Gbps) VTXDIFF_NTB_PP RL =100Ω +1%, DEx, OSx = GND Transition Bit 870 RL =100Ω +1%, DEx, OSx = VCC Transition Bit 1085 RL =100Ω +1%, DEx=NC, OSx = 0,1,NC Non-Transition Bit 665 RL =100Ω +1%, DEx=0, OSx = 0,1,NC Non-Transition Bit 510 RL =100Ω +1%, DEx=1 OSx = 0,1,NC Non-Transition Bit 375 mV –3.0 OS1,2 = NC (for OS1,2 = 1 and 0 see Table 2) De-Emphasis Level –3.5 –4.0 –6.0 dB –8.5 TDE De-Emphasis Width Zdiff_TX DC Differential Impedance 0.85 ZCM_TX DC Common Mode Impedance Measured w.r.t to AC ground over 0-500mV 90 120 Ω 30 Ω 18 23 f = 50 MHz – 1.25 GHz 9 10 f = 1.25 GHz – 2.5 GHz 6 7 11 12 RLdiff_TX Differential Return Loss RLCM_TX Common Mode Return Loss f = 50 MHz – 2.5 GHz ITX_SC TX short circuit current TX± shorted to GND VTX_CM_DC Transmitter DC common-mode voltage VTX_CM_AC_Active TX AC common mode voltage active VTX_idle_diff-AC-pp Electrical idle differential peak to peak output voltage VTX_CM_DeltaU1-U0 Absolute delta of DC CM voltage during active and idle states VTX_idle_diff-DC DC Electrical idle differential output voltage Voltage must be low pass filtered to remove any AC component Vdetect Voltage change to allow receiver detect Positive voltage to sense receiver termination tR,tF Output Rise/Fall time tRF_MM Output Rise/Fall time mismatch 20%-80% of differential voltage measure 1" from the output pin Tdiff_LH, Tdiff_HL Differential Propagation Delay De-Emphasis = –3.5dB (CH 0 and CH 1). Propagation delay between 50% level at input and output See Figure 5 tidleEntry tidleExit Idle entry and exit times See Figure 6 CTX Tx input capacitance to GND At 2.5 GHz UI 72 dB dB 60 2.0 HPF to remove DC 2.6 3.0 V 30 100 mVpp 10 mV 200 mV 10 mV 600 mV 0 35 0 30 mA 50 ps 20 ps 290 350 ps 4 6 ns 1.25 pF EQUALIZATION TTX-EYE (1) (2) DJTX (2) RJTX (2) (4) TTX-EYE (1) (2) (3) (4) 0.14 0.5 0.06 0.3 UIpp (3) Random Jitter (Rj) 0.08 0.2 Total Jitter (Tj) at point B 0.14 0.5 0.06 0.3 UIpp (3) 0.08 0.2 Deterministic Jitter (Dj) (1) (2) DJTX (2) RJTX Total Jitter (Tj) at point A (2) (4) Deterministic Jitter (Dj) Device setting: OS1 = L, DE1 = H, EQ1 = L Device setting: OS2 = H, DE2 = H, EQ2 = L Random Jitter (Rj) -12 Includes Rj at 10 Measured at the end of reference channel in Figure 8 with K28.5 pattern, VID=1000mVpp, 5Gbps, –3.5dB DE from source. UI = 200ps Rj calculated as 14.069 times the RMS random jitter for 10-12 BER Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 9 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com IN Tdiff_HL Tdiff_LH OUT Figure 5. Propagation Delay vertical spacer vertical spacer IN+ VEID_TH VCM INtidleEntry tidleExit OUT+ VCM OUT- Figure 6. Electrical Idle Mode Exit and Entry Delay vertical spacer vertical spacer 80 % 20 % tr tf Figure 7. Output RIse and Fall Times 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 Jitter Measurement CH1 A SN65LVPE502 1 2 AWG* CH1 Up to 3m (30AWG) 20" 1"-6" 4" B *Source Jitter Measurements Total Jitter Deterministic Jitter Random Jitter Jitter Measurement CH2 AWG* CH2 (ps) 21pp 8pp 0.95 rms Figure 8. Jitter Measurement Setup vertical spacer vertical spacer 1-bit 1 to N bits tDE 1-bit 1 to N bits EQx = NC -3.5dB -6dB EQx = 0 -8.5dB EQx = 1 VCM VTXDIFF_NTB_PP VTXDIFF_TB_PP tDE Figure 9. Output De-Emphasis Levels OSx = NC Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 11 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com Typical Eye Diagram and Performance Curves Input Signal Characteristics: Data Rate = 5 Gbps, VID = 1000 mVpp, DE = -3.5 dB, Pattern = K28.5 Device Operating Conditions: VCC = 3.3 V, Temp = 25°C Input Trace Length Held Constant and Output Cable Length Varied Figure 10. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 1 M vertical spacer vertical spacer Figure 11. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 2 M 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 Figure 12. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 3 M vertical spacer vertical spacer Figure 13. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 4 M Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 13 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com 25 Deterministic Jitter - ps - pk-pk 20 15 10 5 Output Deterministic Jitter vs Output USB3.0 Cable Length With Fixed 12” Input Trace 0 1 1.5 2 2.5 3 Output USB Cable Length - m 3.5 4 Figure 14. Jitter Performance Over Different Cable Lengths Input Trace Length Held Constant and Output Trace Varied Figure 15. Input Trace = 4 Inches, 6 mil and Output Trace = 4 Inches, 6 mil 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 Figure 16. Input Trace = 4 Inches, 6 mil and Output Trace = 8 Inches, 6 mil vertical spacer vertical spacer Figure 17. Input Trace = 4 Inches, 6 mil and Output Trace = 12 Inches, 6 mil Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 15 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com Figure 18. Input Trace = 4 Inches, 6 mil and Output Trace = 16 Inches, 6 mil vertical spacer vertical spacer Figure 19. Input Trace = 4 Inches, 6 mil and Output Trace = 20 Inches, 6 mil 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 10 9 Deterministic Jitter - ps - pk-pk 8 7 6 5 4 3 2 Output Deterministic Jitter vs Output Trace Length With Fixed 4” Input Trace 1 0 4 6 8 10 12 14 16 6 mil Output Trace Length - Inches 18 20 Figure 20. Jitter Performance Over Different Output Trace Lengths vertical spacer vertical spacer Output Trace Length Held Constant and Input Trace Length Varied Figure 21. Input Trace = 4 Inches, 6 mil and Output Trace = 4 Inches, 6 mil Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 17 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com Figure 22. Input Trace = 8 Inches, 6 mil and Output Trace = 4 Inches, 6 mil vertical spacer vertical spacer Figure 23. Input Trace = 12 Inches, 6 mil and Output Trace = 4 Inches, 6 mil 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 Figure 24. Input Trace = 16 Inches, 6 mil and Output Trace = 4 Inches, 6 mil vertical spacer vertical spacer Figure 25. Input Trace = 20 Inches, 6 mil and Output Trace = 4 Inches, 6 mil Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 19 SN65LVPE502 SLLSE29 – APRIL 2010 www.ti.com Figure 26. Input Trace = 28 Inches, 6 mil and Output Trace = 4 Inches, 6 mil vertical spacer vertical spacer Figure 27. Input Trace = 32 Inches, 6 mil and Output Trace = 4 Inches, 6 mil 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 14 Deterministic Jitter - ps - pk-pk 12 10 8 6 4 2 Output Deterministic Jitter vs Input Trace Length With Fixed 4” Output Trace 0 4 9 14 19 24 6 mil Input Trace Length - Inches 29 Figure 28. Jitter Performance Over Different Input Trace Lengths Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 21 PACKAGE OPTION ADDENDUM www.ti.com 26-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVPE502RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVPE502RGET ACTIVE VQFN RGE 24 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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