DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2450B N-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING 6 2 5 3 4 2.0±0.1 0.5±0.1 0.5±0.1 1 0.25 +0.1 -0.05 The µ PA2450B is a switching device, which can be driven directly by a 2.5 V power source. The µ PA2450B features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on. 1.85±0.1 PACKAGE DRAWING (Unit: mm) DESCRIPTION 0.8 MAX. 4.4±0.1 FEATURES 5.0±0.1 • 2.5 V drive available • Low on-state resistance RDS(on)1 = 17.5 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A) RDS(on)2 = 18.5 mΩ MAX. (VGS = 4.0 V, ID = 4.0 A) RDS(on)3 = 22.0 mΩ MAX. (VGS = 3.1 V, ID = 4.0 A) RDS(on)4 = 27.5 mΩ MAX. (VGS = 2.5 V, ID = 4.0 A) • Built-in G-S protection diode against ESD 0.05 +0 -0.05 (0.15) 0.145±0.05 7 (1.45) (0.9) ORDERING INFORMATION PART NUMBER PACKAGE (0.5) µ PA2450BTL (2.2) 6PIN HWSON (4521) Each lead has same dimensions. 5,6: Source 2 1,2: Source 1 4: Gate 2 3: Gate 1 7: Drain ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 20.0 V Gate to Source Voltage (VDS = 0 V) VGSS ±12.0 V Drain Current (DC) Note1 ID(DC) ±8.6 A Note2 ID(pulse) ±80.0 A Note1 PT1 2.5 W Total Power Dissipation (2 units) Note3 PT2 0.7 W Drain Current (pulse) Total Power Dissipation (2 units) Channel Temperature Tch 150 °C Storage Temperature Tstg −55 to +150 °C EQUIVALENT CIRCUIT Drain1 Gate1 Drain2 Body Diode Gate2 Gate Protection Diode Source1 Body Diode Gate Protection Diode Source2 Notes 1. Mounted on ceramic board of 50 cm2 x 1.1 mm 2. PW ≤ 10 µs, Duty Cycle ≤ 1% 2 3. Mounted on FR-4 board of 50 cm x 1.1 mm Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G16635EJ1V0DS00 (1st edition) Date Published January 2004 NS CP(K) Printed in Japan 2004 µ PA2450B ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 20.0 V, VGS = 0 V 1.0 µA Gate Leakage Current IGSS VGS = ±12.0 V, VDS = 0 V ±10.0 µA VGS(off) VDS = 10.0 V, ID = 1.0 mA 0.50 1.50 V | yfs | VDS = 10.0 V, ID = 4.0 A 3.5 RDS(on)1 VGS = 4.5 V, ID = 4.0 A 11.0 12.5 17.5 mΩ RDS(on)2 VGS = 4.0 V, ID = 4.0 A 11.5 13.0 18.5 mΩ RDS(on)3 VGS = 3.1 V, ID = 4.0 A 12.0 14.5 22.0 mΩ RDS(on)4 VGS = 2.5 V, ID = 4.0 A 15.3 18.0 27.5 mΩ Gate Cut-off Voltage Forward Transfer Admittance Note Drain to Source On-state Resistance Note S Input Capacitance Ciss VDS = 10.0 V 520 pF Output Capacitance Coss VGS = 0 V 133 pF Reverse Transfer Capacitance Crss f = 1.0 MHz 92 pF Turn-on Delay Time td(on) VDD = 10.0 V 21 ns ID = 4.0 A 86 ns VGS = 4.0 V 124 ns RG = 6 Ω 107 ns Rise Time tr Turn-off Delay Time td(off) Fall Time tf Total Gate Charge QG VDD = 16.0 V 8.0 nC Gate to Source Charge QGS VGS = 4.0 V 1.3 nC QGD ID = 8.6 A 3.3 nC VF(S-D) IF = 8.6 A, VGS = 0 V 0.83 V Reverse Recovery Time trr IF = 8.6 A, VGS = 0 V 128 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 129 nC Gate to Drain Charge Body Diode Forward Voltage Note Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2% TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE D.U.T. D.U.T. VGS RL VGS RG PG. Wave Form VDD 0 VGS 10% PG. 90% τ τ = 1 µs Duty Cycle ≤ 1% 2 90% VDS VDS 10% 0 10% Wave Form td(on) tr ton RL 50 Ω VDD 90% VDS VGS 0 IG = 2 mA td(off) tf toff Data Sheet G16635EJ1V0DS µ PA2450B ELECTRICAL CHARACTERISTICS (TA = 25°C) TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 3 120 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 Mounted on ceramic board of 50 cm2 x 1.1 mm, 2 units 2.5 Mounted on FR-4 board of 50 cm2 x 1.1 mm, 2 units 2 1.5 1 0.5 0 0 0 25 50 75 100 125 150 0 175 TA - Ambient Temperature - °C 25 50 75 100 125 150 175 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA RDS(on) Limited (at VGS = 4.5 V) 100 ID(pulse) PW = 10 µs 100 µs 10 ID(DC) 1 ms 1 DC (2 units) 10 ms 30 ms 0.1 Single pulse Mounted on ceramic board of 2 0.01 50 cm x 1.1 mm PD (FET1) : PD (FET2) = 1:1 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(ch-A) - Transient Thermal Resistance - °C/W ID - Drain Current - A 1000 1000 Mounted on FR-4 board of 50 cm2 x 1.1 mm 100 Mounted on ceramic board of 50 cm2 x 1.1 mm 10 1 Single pulse PD (FET1) : PD (FET2) = 1:1 0.1 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G16635EJ1V0DS 3 µ PA2450B DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 40 30 100 Pulsed VGS = 4.5 V 4.0 V 3.1 V 2.5 V 20 VDS = 10.0 V Pulsed 10 ID - Drain Current - A ID - Drain Current - A 50 FORWARD TRANSFER CHARACTERISTICS TA = 125°C 75°C 25°C −25°C 1 0.1 0.01 10 0.001 0 0 0.2 0.4 0.6 0.8 1 0 1.2 0.5 GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE | yfs | - Forward Transfer Admittance - S VGS(off) - Gate Cut-off Voltage - V VDS = 10.0 V ID = 1.0 mA 1 0.8 0.6 0.4 0 50 100 150 VGS = 2.5 V 3.1 V 4.0 V 4.5 V 10 0 0.1 1 10 100 RDS(on) - Drain to Source On-state Resistance - mΩ RDS(on) - Drain to Source On-state Resistance - mΩ Pulsed 20 VDS = 10.0 V Pulsed 1 TA = −25°C 25°C 75°C 125°C 0.1 0.01 0.01 0.1 1 10 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 40 ID = 4.0 A Pulsed 30 20 10 ID - Drain Current - A 4 3 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 30 2.5 10 Tch - Channel Temperature - °C 40 2 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 1.4 -50 1.5 VGS - Gate to Source Voltage - V VDS - Drain to Source Voltage - V 1.2 1 0 0 2 4 6 8 10 VGS - Gate to Source Voltage - V Data Sheet G16635EJ1V0DS 12 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 10000 40 ID = 4.0 A Pulsed VGS = 2.5 V 3.1 V 4.0 V 4.5 V 30 Ciss, Coss, Crss - Capacitance - pF RDS(on) - Drain to Source On-state Resistance - mΩ µ PA2450B 20 10 VGS = 0 V f = 1.0 MHz 1000 Ciss Coss Crss 100 0 10 -50 0 50 100 150 0.1 Tch - Channel Temperature - °C 100 DYNAMIC INPUT CHARACTERISTICS 1000 4 VDD = 10.0 V VGS = 4.0 V RG = 6 Ω VGS - Gate to Drain Voltage - V td(on), tr, td(off), tf - Switching Time - ns 10 VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS td(off) tf 100 1 tr td(on) 10 ID = 8.6 A VDD = 4.0 V 10.0 V 16.0 V 3 2 1 0 0.1 1 10 ID - Drain Current - A 0 2 4 6 8 QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE IF - Diode Forward Current - A 100 VGS = 0 V Pulsed 10 1 0.1 0.01 0.4 0.6 0.8 1 1.2 VF(S-D) - Source to Drain Voltage - V Data Sheet G16635EJ1V0DS 5 µ PA2450B <Notes for using this device safely> When you use this device, in order to prevent a customer’s hazard and damage, use it with understanding the following contents. If used exceeding recommended conditions, there is a possibility of causing failure of the device and characteristic degradation. 1. When you mount the device on a substrate, carry out within our recommended soldering conditions of infrared reflow. If mounted exceeding the conditions, the characteristic of a device may be degraded and it may result in failure. 2. When you wash the device mounted the substrate, carry out within our recommended conditions. If washed exceeding the conditions, the characteristic of a device may be degraded and it may result in failure. 3. When you use ultrasonic wave to substrate after the device mounting, prevent from touching a resonance generator directly. If it touches, the characteristic of a device may be degraded and it may result in failure. 4. Please refer to Figure 1 as an example of the land pattern. Optimize the land pattern in consideration of density, appearance of solder fillets, common difference, etc in an actual design. Figure 1. Example of the land pattern Unit: mm 3.86 0.30 1.16 0.50 2.04 0.83 6 Data Sheet G16635EJ1V0DS µ PA2450B 5. This device is very thin device and should be handled with caution for mechanical stress. The rate of distortion applied to the device should become below 2000 µε.Note1 If the rate of distortion exceeds 2000 µε, the characteristic of a device may be degraded and it may result in failure. Figure 2. Direction of substrate and stress The substrate that mounted the device is on a stand with a support width of 24 mm. The device is turned downward. The stress is applied from a top. Substrate: 33 x 6 mm, t = 0.5 mm, FR-4 The direction of a device: Stress Bend Measurement position Support width 24 mm Device Figure 3. Example of the bend and the rate of distortion Note2 The rate of distortion - µ ε 6000 5000 4000 3000 2000 Recommended condition 1000 0 0 0.2 0.4 0.6 0.8 1 Bend - mm Note 1. Definition of rate of distortion(written as ε in this document) ε = (l − l0)/l0 l0: Distance for two arbitrary points before receiving stress. l: Distance above-mentioned when receiving stress. 2. The relation of the distortion and the bend changes with several conditions, such as a size of substrate and so on. Data Sheet G16635EJ1V0DS 7 µ PA2450B • The information in this document is current as of January, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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