PRELIMINARY DATA SHEET NPN SILICON EPITAXIAL TWIN TRANSISTOR FEATURES UPA836TC OUTLINE DIMENSIONS • SMALL PACKAGE OUTLINE: 1.5 mm x 1.1 mm, 33% smaller than conventional SOT-363 package • LOW HEIGHT PROFILE: Just 0.55 mm high (Units in mm) Package Outline TC (TOP VIEW) 1.50±0.1 1.10±0.1 0.20 +0.1 -0.05 • FLAT LEAD STYLE: Reduced lead inductance improves electrical performance • 1.50±0.1 TWO DIFFERENT DIE TYPES: Q1 - Ideal oscillator transistor Q2 - Ideal buffer amplifier transistor 1 6 2 5 3 4 PIN OUT 1. Collector (Q1) 2. Emitter (Q1) 3. Collector (Q2) 4. Base (Q2) 5. Emitter (Q2) 6. Base (Q1) 0.48 0.96 0.48 DESCRIPTION The UPA836TC contains one NE685 and one NE688 NPN high frequency silicon bipolar chip. NEC's new ultra small TC package is ideal for all portable wireless applications where reducing board space is a prime consideration. Each transistor chip is independently mounted and easily configured for oscillator/buffer amplifier and other applications. 0.11+0.1 -0.05 0.55±0.05 Note: Pin 1 is the lower left most pin as the package lettering is oriented and read left to right. ELECTRICAL CHARACTERISTICS (TA = 25°C) PART NUMBER PACKAGE OUTLINE Q1 SYMBOLS UNITS MIN TYP MAX ICBO Collector Cutoff Current at VCB = 5 V, IE = 0 µA 0.1 IEBO Emitter Cutoff Current at VEB = 1 V, IC = 0 µA 0.1 hFE fT Cre |S21E|2 Q2 PARAMETERS AND CONDITIONS UPA836TC TC DC Current Gain1 at VCE = 3 V, IC = 10 mA Gain Bandwidth at VCE = 3 V, IC = 10 mA, f = 2 GHz Feedback Capacitance2 at VCB = 3 V, IE = 0, f = 1 MHz 75 GHz 10 pF Insertion Power Gain at VCE = 3 V, IC =10 mA, f = 2 GHz dB NF Noise Figure at VCE = 3 V, IC = 3 mA, f = 2 GHz dB ICBO Collector Cutoff Current at VCB = 5 V, IE = 0 µA IEBO Emitter Cutoff Current at VEB = 1 V, IC = 0 µA hFE DC Current Gain1 at VCE = 1 V, IC = 3 mA 150 12 0.4 7 0.7 8.5 1.5 2.5 0.1 0.1 80 4.0 160 fT Gain Bandwidth (1) at VCE = 1 V, IC = 3 mA, f = 2 GHz GHz fT Gain Bandwidth (2) at VCE = 3 V, IC = 20 mA, f = 2 GHz GHz 9.0 Cre Feedback Capacitance2 at VCB = 1 V, IE = 0, f = 1 MHz pF 0.75 |S21E|2 Insertion Power Gain (1) at VCE = 1 V, IC =3 mA, f = 2 GHz dB |S21E|2 Insertion Power Gain (2) at VCE = 3 V, IC =20 mA, f = 2 GHz dB 6.5 NF Noise Figure (1) at VCE = 1 V, IC = 3 mA, f = 2 GHz dB 1.7 NF Noise Figure (2) at VCE = 3 V, IC = 7 mA, f = 2 GHz dB 1.5 2.5 4.5 0.85 3.5 2.5 Notes: 1. Pulsed measurement, pulse width ≤ 350 µs, duty cycle ≤ 2 %. 2. Collector to base capacitance when measured with capacitance meter (automatic balanced bridge method), with emitter connected to guard pin of capacitances meter. California Eastern Laboratories UPA836TC ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C) SYMBOLS PARAMETERS UNITS RATINGS Q1 Q2 VCBO Collector to Base Voltage V 9 9 VCEO Collector to Emitter Voltage V 6 6 VEBO Emitter to Base Voltage V 2 2 100 IC Collector Current mA 30 PT Total Power Dissipation mW TJ Junction Temperature °C TBD TBD TBD 150 150 TSTG Storage Temperature °C ORDERING INFORMATION PART NUMBER UPA836TC-T1 QUANTITY 3000 PACKAGING Tape & Reel -65 to +150 Note: 1. Operation in excess of any one of these parameters may result in permanent damage. EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM 1/99 DATA SUBJECT TO CHANGE WITHOUT NOTICE