DATA SHEET MOS INTEGRATED CIRCUIT µPD16879 MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT The µPD16879 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOSFET output circuit. Because it uses MOSFETs in its output stage, this driver IC consumes less power than conventional driver ICs that use bipolar transistors. Because the µPD16879 controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been reduced. This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. The µPD16879 is a housed in a 38-pin shrink SOP to contribute to the miniaturization of application set. This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders. FEATURES • Four H bridge circuits employing power MOS FETs • Current-controlled 64-step micro step driving • Motor control by serial data (8 bits × 13 bytes) PWM-frequency, output current and number of output pulse can be setting by serial data. • 3-V power supply. Minimum operating voltage: 2.7 V • Low consumption current. VDD pin current (operating mode) : 3 mA (MAX.) • Power save circuit bult in. VDD pin current (power save mode) : 100 µA (MAX.) fCLK: OFF state VDD pin current (power save mode) : 300 µA (MAX.) fCLK: 4.5 MHz input • 38-pin shrink SOP (7.62 mm (300)) ORDERING INFORMATION Part Number Package µPD16879GS-BGG 38-pin plastic shrink SOP (7.62 mm (300)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14188EJ1V0DS00 (1st edition) Date Published July 2000 N CP(K) Printed in Japan © 2000 µPD16879 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) When mounted on a glass epoxy board (100 mm × 100 mm × 1 mm, 15% copper foil) Parameter Supply voltage Input voltage Symbol Conditions Rating Unit VDD Control part –0.5 to +6.0 V VM Output part –0.5 to +11.2 V –0.5 to VDD + 0.5 V 0.5 V VIN Reference voltage VREF External input H bridge drive current IM(DC) DC ±0.15 A/ch IM(pulse) PW < 10 ms, Duty < 5 % ±0.3 A/ch PT 1.0 W TCH(MAX) 150 °C Tstg –55 ∼ +150 °C Power consumption Peak junction temperature Storage temperature RECOMMENDED OPERATING RANGE (TA = +25°C) When mounted on a glass epoxy board (100 mm × 100 mm × 1 mm, 15% copper foil) Parameter Supply voltage Input voltage Reference voltage Conditions MIN. TYP. MAX. Unit VDD Control part 2.7 5.5 V VM Output part 4.0 11 V 0 VDD V 275 mV VIN VREF External input 225 250 EXP pin input voltage VEXPIN VDD V EXP pin input current IEXPIN 100 µA H bridge drive current IM(DC) DC −0.1 +0.1 A/ch IM(pulse) PW < 10 ms, Duty < 5% −0.2 +0.2 A/ch COSC = 68 pF, VREF = 250 mV 3.9 6.0 MHz VDD V 5.0 MHz Clock frequency (OSCIN) fCLK Clock frequency amplitude VfCLK Serial clock frequency fSCLK 0.7 × VDD 4.5 Video sync signal width PW(VD) fCLK = 4.5 MHz 250 ns LATCH signal wait time t(VD-LATCH) Refer to Fig. 1 400 ns t(SCLK-LATCH) 400 ns SDATA setup time tsetup 80 ns SDATA hold time thold 80 ns Reset signal pulse width tRST 100 µs Operating temperautre TA −10 SCLK wait time Peak junction temperature 2 Symbol TCH(MAX) Data Sheet S14188EJ1V0DS00 85 °C 125 °C µPD16879 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, TA = 25°°C, VDD = 3 V, VM = 5.4 V, fCLK = 4.5 MHz, COSC = 68 pF, CFIL = 1000 pF, VREF = 250 mV, EVR = 100 mV (10000)) Parameter Off state VM pin current Operating state VDD pin current VDD pin current Power save state VDD pin current Symbol MAX. Unit No load, Reset period 1.0 µA IDD Output open 3.0 mA IDD(RESET) Reset period 100 µA IDD(PS)1 tCLK = off 100 µA IDD(PS)2 fCLK = 4.5 MHZ 300 µA IMO(RESET) High level input voltage VIH Low level input voltage VIL Input hysteresis vosltage VH Monitor output voltage 1 (EXTOUT α, β ) VOMα(H) VOMβ(H) Conditions LATCH, SCLK, SDATA, VD, VD RESET, OSCIN, VREFsel MIN. TYP. 0.7 × VDD V 0.3 × VDD 0.3 4th byte Monitor output voltage 2 (EXP 0,1 open drain) VOEXP(H) Pull up (VDD) VOEXP(L) IOEXP = 100 µA High level input current IIH VIN = VDD Low level input current IIL VIN = 0 Reset pin high level input current IIH(RST) VRST = VDD Reset pin low level input current IIL(RST) VRST = 0 V 0.9 × VDD V −0.3 VOMα(L) VOMβ(L) V 0.1 × VDD 0.9 × VDD V V 0.1 × VDD V 1.0 µA µA −1.0 1.0 µA µA −1.0 RON Note 1 fOSC Refer to table 1 (TYP.) kHz VREF 225 275 mV 250 ns Chopping frequency Internal reference voltage IM = 100 mA, upper + lower 6.0 Ω H bridge ON resistance 250 ∆tVD Note 2 VD delay time Sin wave peak output current Note 3 (reference value) Note 4 FIL pin voltage Note 4 FIL pin step voltage IM L = 15 mH/R = 70 Ω ( 1 kHz) RS = 6.8 Ω, fOSC = 72.58 kHz EVR = 220 mV (11100) VEVR EVR = 200 mV (11010) VREF = 250 mV external input VEVRSTEP Note 5 tONH Note 5 tOFFH H bridge turn on time H bridge turn off time 53 370 Minimum step 400 mA 430 20 IM = 100 mA mV mV 2.0 µs 2.0 µs Notes 1. When data are less than 7 (000111), PWM chopping doesn’t do it, and output pulse doesn’t occur. When data are beyong 49, PWM chopping frequency becomes a 225 kHz fixation. 2. By OSCIN and VD sync circuit 3. FB pin is monitored. 4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin. 5. 10% to 90% of the pulse peak value without filter capacitor (CFIL) Data Sheet S14188EJ1V0DS00 3 µPD16879 Fig 1. Delay Time of Serial Data VD VD t(VD-LATCH) LATCH 104 clocks (8 bits × 13 bytes) SCLK t(SCLK-LATCH) t(SCLK-LATCH) Ignored because LATCH is at low level Ignored because LATCH is at low level 50% LATCH D1 SDATA 50% SCLK t(SCLK-LATCH) D3 D2 50% tsetup thold Table 1. Chopping Frequency (3rd byte D5 to D0 bit data, fCLK = 4.5 MHz) Typical Value Input data D5 to D0 bit 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 Chopping frequency (kHz) 35.71 40.18 45.00 50.00 53.57 59.21 62.50 68.18 72.58 77.59 80.36 86.54 90.00 93.75 97.83 102.27 107.14 112.50 118.42 118.42 125.00 Input data D5 to D0 bit 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 Chopping frequency (kHz) 132.35 132.35 140.63 140.63 150.00 150.00 160.71 160.71 160.71 173.08 173.08 173.08 187.50 187.50 187.50 204.55 204.55 204.55 204.55 225.00 Note When data are less than 7 (000111), PWM chopping doesn’t do it, and output pulse doesn’t occur. When data are beyond 49, PWM chopping frequency becomes a 225 kHz fixation. 4 Data Sheet S14188EJ1V0DS00 µPD16879 Table 2. Relation Between Rotation Angle, Phase Current, and Vector Quantity (64-DIVISION MICRO STEP) (Value of µPD16879 for reference) STEP Rotation angle (θ) A phase current B phase current Vector quantity MIN. TYP. MAX. MIN. TYP. MAX. TYP. θ0 0 − 0 − − 100 − 100 θ1 5.6 2.5 9.8 17.0 − 100 − 100.48 θ2 11.3 12.4 19.5 26.5 93.2 98.1 103 100 θ3 16.9 22.1 29.1 36.1 90.7 95.7 100.7 100.02 θ4 22.5 31.3 38.3 45.3 87.4 92.4 97.4 100.02 θ5 28.1 40.1 47.1 54.1 83.2 88.2 93.2 99.99 θ6 33.8 48.6 55.6 62.6 78.1 83.1 88.1 99.98 θ7 39.4 58.4 63.4 68.4 72.3 77.3 82.3 99.97 θ8 45 65.7 70.7 75.7 65.7 70.7 75.7 99.98 θ9 50.6 72.3 77.3 82.3 58.4 63.4 68.4 99.97 θ 10 56.3 78.1 83.1 88.1 48.6 55.6 62.6 99.98 θ 11 61.9 83.2 88.2 93.2 40.1 47.1 54.1 99.99 θ 12 67.5 87.4 92.4 97.4 31.3 38.3 45.3 100.02 θ 13 73.1 90.7 95.7 100.7 22.1 29.1 36.1 100.02 θ 14 78.8 93.2 98.1 103 12.4 19.5 26.5 100 θ 15 84.4 − 100 − 2.5 9.8 17.0 100.48 θ 16 90 − 100 − − 0 − 100 Remark These data do not indicate guaranteed values. Data Sheet S14188EJ1V0DS00 5 µPD16879 PIN CONFIGURATION 1 LGND RESET 38 2 COSC OSCOUT 37 3 FILA OSCIN 36 4 FILB SCLK 35 5 FILC SDATA 34 6 FILD LATCH 33 7 VREF VD 32 8 VDD VD 31 9 VM3 B2 30 10 D2 FBB 29 11 FBD B1 28 27 12 6 D1 VM2 13 VM4 A2 26 14 C2 FBA 25 15 FBC A1 24 16 C1 VM1 23 17 EXP0 EXTβ 22 18 EXP1 EXTα 21 19 VREFsel PGND 20 Data Sheet S14188EJ1V0DS00 µPD16879 PIN FUNCTION Package: 38-pin plastic shrink SOP Pin Pin name Pin function 1 LGND 2 COSC Chopping capacitor connection pin 3 FILA α 1 ch filter capacitor connection pin 4 FILB α 2 ch filter capacitor connection pin 5 FILC β 1 ch filter capacitor connection pin 6 FILD β 2 ch filter capacitor connection pin 7 VREF Reference voltage input pin (250 mV typ) 8 VDD Control circuit supply voltage input pin 9 VM3 Output circuit supply voltage input pin 10 D2 β 2 ch output pin 11 FBD Control circuit GND pin Note 1 β 2 ch sense resistor connection pin 12 D1 β 2 ch output pin 13 VM4 Output circuit supply voltage input pin 14 C2 β 1 ch output pin 15 FBC 16 C1 17 EXP0 External extension pin (open drain) 18 EXP1 External extension pin (open drain) 19 VREFsel Reference voltage select pin 20 PGND Output circuit GND pin 21 EXT α α ch logic circuit monitor pin 22 EXT β β ch logic circuit monitor pin 23 VM1 Output circuit supply voltage input pin 24 A1 α 1 ch output pin 25 FBA β 1 ch sense resistor connection pin β 1 ch ouptut pin Note 1 α 1 ch sense resistor connection pin 26 A2 α 1 ch output pin 27 VM2 Output circuit supply voltage input pin 28 B1 α 2 ch output pin 29 FBB 30 B2 α 2 ch output pin 31 VD Video sync signal input pin 32 VD Video sync signal input pin 33 LATCH 34 SDATA 35 SCLK Serial clock input pin (4.5 MHz typ) 36 OSCIN Original oscillation input pin (4.5 MHz typ) 37 OSCOUT Original oscillation output pin 38 RESET Reset signal input pin α 2 ch sense resistor connection pin Note 2 Note 2 LATCH signal input pin Serial data input pin Remark Plural terminal (VM) is not only 1 terminal and connect all terminals. Notes 1. A standard voltage to use is chosen. VREFsel: High level using external input VREF VREFsel: Low level using internal reference voltage (VREF pin fixed GND level) 2. Input the video sync singnal to VD pin or VD pin. A free terminal is to do the following treatment. When input VD: VD pin connect to VDD pin. When input VD: VD pin connect to GND pin. Data Sheet S14188EJ1V0DS00 7 µPD16879 I/O PIN EQUIVALENT CIRCUIT Pin name VD VD LATCH SDATA SCLK OSCIN RESET VREFsel Equivalent circuit Pin name Equivalent circuit VREF VDD VDD Internal 250 mV PAD PAD VREFsel OSCOUT EXTα EXTβ EXP0 EXP1 VDD VDD PAD FILA FILB FILC FILD PAD VDD PAD Buffer A1, A2 B1, B2 C1, C2 D1, D2 VM Parasitic diodes PAD FB 8 Data Sheet S14188EJ1V0DS00 OSCOUT 36 37 VD VD 32 SCLK 31 SDATA LATCH 34 33 35 EXP0 EXP1 17 VREF VREFsel 19 18 BLOCK DIAGRAM Data Sheet S14188EJ1V0DS00 Remark Plural terminal (VM) is not only 1 terminal and connect all terminals. RESET OSCIN 7 38 VDD 8 VM1 23 ×2 SERIAL-PARARELLE DECODER VM2 27 VM3 9 Vref 250 mV select B.G.R EXTOUT SELECTOR PULSE GENERATER 1/N VM4 COSC 13 CURRENT SET α 2 21 CURRENT SET β OSC 22 + + + 1 PGND 20 α 1ch FBA 24 A1 26 A2 3 FILA 29 FBB + – FILTER + – FILTER VM VM H BRIDGE 25 + – FILTER VM LGND EXTβ + + – EXTα FILTER VM H BRIDGE H BRIDGE H BRIDGE α 2ch β 1ch β 2ch 28 B1 30 B2 4 FILB 15 FBC 16 C1 14 5 C2 FILC 11 FBD 12 D1 10 D2 6 FILD µPD16879 9 EXAMPLE OF STANDARD CONNECTION 10 CPU 100 kΩ × 2 4.5 MHz TYP. Using internal reference OSCIN 37 36 RESET REGULATOR 2.7 V to 5.5 V Data Sheet S14188EJ1V0DS00 BATTERY 4.0 V to 11 V VD 32 SCLK SDATA LATCH 31 35 34 EXP0 EXP1 17 33 VREFsel VREF 19 18 7 38 VDD 8 VM1 23 VM2 27 VM3 9 VM4 13 COSC VD OSCOUT CURRENT SET α 2 EXTOUT SELECTOR PULSE GENERATOR 1/N 250 mV B.G.R Vref select ×2 SERIAL-PARALLELE DECODER 21 CURRENT SET β OSC 22 68 pF + + – + PGND 20 – + FILTER VM 1 FBA 24 A1 – + FILTER VM H BRIDGE α 1ch 25 EXTβ + + LGND EXTα H BRIDGE α 1ch 26 3 29 A2 FILA FBB 28 B1 30 4 B2 FILB – + FILTER VM H BRIDGE β 1ch 15 FBC 16 C1 FILTER VM H BRIDGE β 1ch 14 5 11 C2 FILC FBD 12 D1 10 6 D2 FILD 6.8 Ω × 2 6.8 Ω 6.8 Ω 1000 pF 1000 pF 1000 pF × 2 MOTOR 2 µPD16879 MOTOR 1 RESET VD VD S1 S2 S3 S5 PS S4 pulse 0 S6 PS S9 Enable S7 release PS S8 S10 release PS S11 S12 data error S13 normal data LATCH S14 TIMING CHART (1) Initialization DATA SCLK OSCOUT S7 Start point wait (FF1) S1 Data Sheet S14188EJ1V0DS00 Start point wait+ Start point magnetize wait (FF2) S2 S2 S3 S3 S4 H level fixation It reverts from the VD start after a PS release. L level fixation S4 S4 ENABLE OUTNote 1 S8 S9 S9 S10 S10 S11 S12 S13 S12 S13 S14 S8 S11 L level fixation Stop from LATCH ↓ CHOPPING Start from LATCH ↓ Pulse count is done in enable period too EXP can be change in PS period too. EXP 0, 1 S2 S3 S4 S5 to S7 Pulse is nothing because pulse data is "0" PULSE OUT Pulse is nothing because PS data S8 S9 S10 S11 S13 Pulse is nothing because error data. PULSE GATE (FF3) PULSE CHECKNote 2 (FF7) Output L level because error data CHECK SUMNote 3 SCLK D0 D1 D2 (LSB) Data is held at rising edge SCLK D3 D4 D5 D6 D7 11 µPD16879 SDATA 1st byte → 13th byte Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low to high, and at the falling edge of FF2 when the level changes from high to low. 2. FF7 is an output signal that is used to check for the presence or absence of a pulse in the serial data, is updated at the falling edge of LATCH and reset once at the rising edge of LATCH. If CHECK SUM is other than "00h", FF7 goes low, inhibiting pulse output, even if a pulse is generated. 3. CHECK SUM output is updated at the falling edge of LATCH. µPD16879 TIMING CHART (2) CLK (PULSE OUT) MOB (CW mode) Current direction: A2 to A1 H bridge α , β 1ch output Current direction: A1 to A2 Current direction: B2 to B1 Current direction: B2 to B1 H bridge α , β 2ch output Current direction: B1 to B2 (Expanded view) CCW mode CW mode CW mode CLK PULSE OUT Position No. 1 2 3 4 5 6 5 4 3 2 3 CCW H bridge 1ch output 4 Note CW mode : Position No is incremented. CCW mode: Position No is decremented. CW CCW CW CW CW H bridge 2ch output CCW CW CW CCW Remarks 1. The current value of the actual wave is approximated to the value shown on the page 5. 2. The C1, C2, D1, and D2 pins of β channel correspond to the A1, A2, B1, and B2 pins of α channel. 3. The CW mode is set if the D6 bit of the fifth and ninth bytes of the data is “0”. 4. The CCW mode is set if the D6 bit of the fifth and ninth bytes of the data is “1”. 12 Data Sheet S14188EJ1V0DS00 µPD16879 STANDARD CHARACTERISTICS CURVES IDD vs. VDD characteristics PT vs. TA characteristics 7.0 0.8 125°C/W 0.6 0.4 0.2 0 –20 TA = 25°C operating 6.0 1.0 VDD pin current IDD (mA) Total power dissipation PT (W) 1.2 5.0 4.0 3.0 2.0 1.0 0 0 100 20 40 80 60 Ambient temperature TA (°C) 6 1 2 3 5 4 Control circuit supply voltage VDD (V) 120 IDD(PS) vs. VDD characteristics IDD(RESET) vs. VDD characteristics TA = 25°C RESET 300 250 200 150 100 50 VDD pin current (PS) IDD(PS1), IDD(PS2) ( µ A) VDD pin current (RESET) IDD(RESET) ( µ A) 350 TA = 25°C PS mode 600 500 IDD(PS)2 400 300 200 IDD(PS)1 100 0 0 6 1 2 3 5 4 Control circuit supply voltage VDD (V) 6 1 2 3 5 4 Control circuit supply voltage VDD (V) VREF vs. TA characteristics VIH, VIL vs. VDD characteristics 254 VDD = 3.0 V VFIL/2 TA = 25°C 253 Reference voltage VREF (mA) Input voltage VIH, VIL (V) 4.0 3.0 VIL 2.0 VIH 1.0 252 251 250 249 248 247 246 0 6 1 2 3 5 4 Control circuit supply voltage VDD (V) 245 –20 Data Sheet S14188EJ1V0DS00 0 100 20 40 80 60 Ambient temperature TA (°C) 120 13 µPD16879 IM vs. EVR characteristics IM vs. VM characteristics TA = 25°C, 70 Ω, 15 mV, VM = 5.4 V RS = 6.8 Ω, fOSC = 72.58 kHz 60 50 40 30 20 10 50 Sine wave peak output current IM (mA) Sine wave peak output current IM (mA) 70 0 TA = 25°C, 70 Ω, 15 mH, RS = 6.8 Ω fOSC = 72.58 kHz, EVR = 100 mV (10000) 40 30 20 10 0 50 100 150 250 200 EVR setting voltage EVR (mV) 2 4 6 12 10 8 Output circuit supply voltage VM (V) RON vs. VM characteristics IM vs. RS characteristics 8.0 TA = 25°C, 70 Ω, 15 mH, VM = 5.4 V fOSC = 72.58 kHz, EVR = 100 mV (10000) TA = 25°C H bridge ON resistance RON (Ω) Sine wave peak output current IM (mA) 60 50 40 30 20 10 6.0 4.0 2.0 0 0 2 4 6 8 10 12 Current sense resistor RS (Ω) 14 RON vs. TA characteristics H bridge ON resistance RON (Ω) 8.0 VM = 4.0 V 6.0 VM = 5.4 V 4.0 VM = 8.0 V VM = 11 V 2.0 0 –20 14 0 40 60 80 20 100 Ambient temperature TA (°C) 120 Data Sheet S14188EJ1V0DS00 4 6 8 10 2 12 Output circuit supply voltage VM (V) µPD16879 I/F CIRCUIT DATA CONFIGURATION (fCLK = 4.5 MHz EXTERNAL CLOCK INPUT) Input data consists of serial data (8 bits × 13 bytes). Input serial data with the LSB first, from the first byte to 13th byte. [1st byte] [2nd byte] Bit Data D7 8 bit data Note input D6 Function First point wait D5 D4 D3 Setting First point wait 227.6 µs to 58.03 ms Setting (1 to 255) ∆t = 227.6 µs Bit Data Function D7 8 bit data Note input First point magnetize wait D6 D4 D3 D2 D1 D1 D0 D0 Note Input other than “0” Note Input other than “0” [3rd byte] [4th byte] Bit Data Function Setting Bit Note 1 D7 1 or 0 Power save OFF/ON Note 1 Bit Data EXT α Output EXT β Output D7 1 or 0 EXP1 Z/L D6 1 or 0 EXP0 Z/L D5 6 bit data input D4 Chopping frequency D3 D2 D1 Chopping frequency 35.71 kHz to 225 kHz Setting Note 2 (8 to 48) D0 Notes 1. 2. First point magnetize wait 227.6 µs to 58.03 ms Setting (1 to 255) ∆t = 227.6 µs D5 D2 Z: High impedance/L: low level Data Setting Function Note 2 Setting Note 1 Note 2 Enable D6 Note 5 Enable D5 Note 5 Rotation Rotation D4 Note 5 Pulse out Pulse out D3 Note 5 FF7 FF7 D2 Note 5 FF3 FF3 D1 Note 5 Checksum D0 Note 5 Chopping Notes 1. Note 3 Note 4 Note 3 FF2 FF1 Data “1”: Normal/Data “0”: Power save 0 to 7 input: PWM and pulse out nothing 2. High: Conducts/Low: Stops 49 to 63 input: 225 kHz fixed 3. High: Reverse (CCW)/Low: Forward (CW) Refer to 4 page 4. High: Normal data/Low: Error data 5. Select one of D0 to D6 and input ”1”. If two or more of D0 to D6 are selected, they are positively ORed for output. Data Sheet S14188EJ1V0DS00 15 µPD16879 [5th byte] [6th byte] Bit Data Function Setting Bit Data 8 bit data input D7 1 or 0 Enable α α ch ON/OFF D7 D6 1 or 0 Rotation α α ch CCW/CW D6 D5 0 Not use Not use D5 D4 5 bit data input α channel Current set α channel Note Current set D4 D3 D1 D0 Note Fixed to 50 mV if 0 to 10 input. D2 D1 and 768. [8th byte] Bit Data 16 bti data low-order 8 bit data input D5 α channel Number of pulse in 1 VD 0 to 1020 pulses Setting (0 to 255) ∆n = 4 Note pulses Note Output pulse is nothing if data input 256, 512, [7th byte] D6 Setting D0 Refer to 4 page. D7 α channel Pulse Number D3 EVR: 50 to 250 mV Setting (11 to 31) D2 Function Function Setting Bit α channel Pulse Cycle α channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) ∆t = 222 ns D7 D4 D3 Data 16 bit data High-order 8 bit data input D6 D5 Function Setting α channel Pulse Cycle α channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) ∆t = 222 ns Setting D4 D3 D2 D2 D1 D1 D0 D0 Note D0 bit of 7th byte is LSB, and D7 bit of 8th byte is MSB. [9th byte] [10th byte] Bit Data Function Bit Data Function 8 bit data input β channel Pulse Number D7 1 or 0 Enable β β ch ON/OFF D7 D6 1 or 0 Rotation β β ch CCW/CW D6 D5 0 Not use Not use D5 D4 5 bit data input β channel Current set β channel Note Current set D4 D3 EVR: 50 to 250 mV Setting (11 to 31) D2 D1 D0 Note Fixed to 50 mV if 0 to 10 input. Refer to 4 page. 16 Setting D3 D2 D1 β channel Number of pulse in 1 VD 0 to 1020 pulses Setting (0 to 255) ∆n = 4 Note pulses D0 Note Output pulse is nothing if data input 256, 512, and 768. Data Sheet S14188EJ1V0DS00 µPD16879 [11th byte] Bit D7 D6 D5 [12th byte] Data 16 bit data low-order 8 bit data input Function Setting Bit β channel Pulse Cycle β channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) ∆t = 222 ns D7 D4 D3 D6 D5 Data 16 bit data high-order 8 bit data input D4 D3 D2 D2 D1 D1 D0 D0 Function Setting β channel Pulse Cycle β channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) ∆t = 222 ns Note D0 bit of 11th byte is LSB, and D7 bit of 12th byte is MSB. [13th byte] Bit Data Function Setting D7 8 bit data input Checksum Checksum D6 Note D5 D4 D3 D2 D1 D0 Note Data is input so that the sum of the first through the 13th bytes is 00h. Data Sheet S14188EJ1V0DS00 17 µPD16879 DATA CONFIGURATION Input data is composed of the serial data on 8 bits × 13 bytes. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the first byte. Therefore, the D7 bit of the 13th byte is the most significant bit (MSB). The establishment of the delay time to the output from the power supply injection, chopping frequency, output current, number of pulse, pulse cycle, and so on are possible with this product. The µPD16879 has an EXT pin for monitoring the internal operations, the parameter to be monitored can be selected by serial data. The µPD16879 built in power save function. If set power save mode, consumption current decreased to about 1/10. Input serial data during first point wait time (FF1: high level). This product uses separated external reference clock (fCLK). If they don’t input fCLK, this product can’t operate normally. The establishment value which shows it in this document is at the time of fCLK = 4.5 MHz. Please be careful because establishment value is different in the case of one except for fCLK = 4.5 MHz. Detail of Data Configuration Ho to input serial data is below. [1st byte] The 1st byte specifies the delay between data being read and data being output. This delay is called the first point wait time, and the motor can be driven from that point at which the first point wait time is “0”. This time is counted at the rising edge of VD (or falling edge of VD). The first point wait time can be set to 58.03 ms (when a 4.5 MHz clock input) and can be fine-tuned by means of 8-bit division (227.6 µs step: with 4.5 MHz clock). Always input data other than “0” to this byte because the first point wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. Transfer serial data during the first point wait time. Table 3. 1st Byte Data Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Data Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 Prohibition LSB 00001001 About 2.05 ms 11111111 About 58.03 ms MSB n 18 Data Sheet S14188EJ1V0DS00 First point wait N × 1024/4.5 MHz µPD16879 [2nd byte] The 2nd byte specifies the delay between the first point wait time being cleared and the output pulse being generated. This time called the first point magnetize wait time, and the output pulse is generated from the point at which the start up wait time. The first point magnetize wait time is counted at the falling edge of the first point wait time. The first point magnetize wait time can be set to 58.03 ms (when a 4.5 MHz clock input) and can be fine-tuned by means of 8-bit division (227.6 µs step: with 4.5 MHz clock). Always input data other than “0” to this byte because the first point magnetize wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. Table 4. 2nd Byte Data Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Data Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 Prohibition LSB 00101001 About 9.33 ms 11111111 About 58.03 ms MSB n First point wait N × 1024/4.5 MHz [3rd byte] The 3rd byte sets the chopping frequency and external extension pins (EXP0, EXP1). The chopping frequency sets by bits D0 to D5. The EXP pins goes low (current sink) when the input data is “0”, and high (high-impedance state) when the input data is “1”. Pull this pin up to VDD for use. Table 5. 3rd Byte Data Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 EXP1 sets MSB LSB EXP0 sets Chopping frequency sets D7: EXP1 sets “1”: High impedance “0”: Low level (Current sink) D6: EXP0 sets “1”: High impedance “0”: Low level (Current sink) The chopping frequency is set to 0 kHz and to a value in the range of 35.71 kHz to 225 kHz (4.5 MHz clock input). Refer to table 1 (4 page). [4th byte] The 4th byte selects a parameter to be output EXT α and EXT β pins (logic operation monitor pin). And, power save mode sets too. Table 6. 4th Byte Data Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Power save sets Test parameter select Data Sheet S14188EJ1V0DS00 19 µPD16879 The test parameter is selected by bits D0 to D6. There are two EXT pins. EXT α indicates the operating status of α channel, and EXT β indicates that of β channel. The relationship between each bit and each EXT pin is as shown in Table 7. Table 7. Output Data of Test Parameter EXT α EXT β Bit Data D6 0 or 1 Enable α Enable β D5 0 or 1 Rotation α Rotation β D4 0 or 1 Pulseout α Pulseout β D3 0 or 1 FF7 α FF7 β D2 0 or 1 FF3 α FF3 β D1 0 or 1 Checksum FF2 D0 0 or 1 Chopping FF1 If two or more signals that output signals to EXT α and EXT β are selected, they are positively ORed for output. The meanings of the symbols listed in Table 7 are as follows: Enable : Output setting (High level: Conducts/Low level: Stops) Rotation : Rotation setting (High level: Reverse (CCW)/Low level: Forward (CW)) Pulse out : Output pulse signal FF7 : Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in serial data.) FF3 : Pulse gate (output while pulse exists) FF2 : Outputs high level during first point wait time + first point magnetize wait time FF1 : Outputs high level during first point wait time Checksum : Checksum output (High level: when normal data is transmitted/Low level: when abnormal data is transmitted) Chopping : Chopping wave output Power save mode sets by D7 bit. D7 bit data is “1”: Normal mode D7 bit data in “0”: Power save mode When power save mode is selected, circuit consumption current can be reduced. Detail of power save function is refer to “About Power Save Mode (25 page)”. [5th byte] The 5th byte sets the enable, rotation, and output current of α channel. The enable sets by bit D7, the rotation sets by bit D6, and the output current sets by bits D0 to D4. Bit D5 is fixed “0”. Bit D5 isn’t use. Table 8. 5th Byte Data Configuration (α channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Enable sets Rotation sets 20 MSB LSB Output current sets Data Sheet S14188EJ1V0DS00 µPD16879 Enable sets by D7 bit. D7 bit data is “0”: Output high impedance (but, internal counter increase) D7 bit data is “1”: Output conducts Rotation sets by D6 bit. D6 bit data is “0”: Forward turn (CW mode) D6 bit data is “1”: Reverse turn (CCW mode) Output current sets by D0 to D4 bits. The 250 mV (typical) voltage input from external source or internal reference voltage is internally doubled and input to a 5-bit D/A converter. By dividing this voltage by 5-bit data, a current setting reference voltage can be set inside the IC within the range of 100 to 500 mV, in units of 20 mV. If external source is used, the VREFsel pin connects VDD pin. If internal reference voltage is used, the VREFsel pin and VREF pin connect GND pin. The 64 steps micro-step (setting reference voltage is maximum) control is possible. Table 9. Output Current Setting Reference Voltage Data (α channel data) EVR setting D4 D3 D2 D1 D0 FIL pin voltage 50 mV 0 1 0 1 1 100 mV 60 mV 0 1 1 0 0 70 mV 0 1 1 0 80 mV 0 1 1 90 mV 0 1 100 mV 1 110 mV EVR setting D4 D3 D2 D1 D0 FIL pin voltage 160 mV 1 0 1 1 0 320 mV 120 mV 170 mV 1 0 1 1 1 340 mV 1 140 mV 180 mV 1 1 0 0 0 360 mV 1 0 160 mV 190 mV 1 1 0 0 1 380 mV 1 1 1 180 mV 200 mV 1 1 0 1 0 400 mV 0 0 0 0 200 mV 210 mV 1 1 0 1 1 420 mV 1 0 0 0 1 220 mV 220 mV 1 1 1 0 0 440 mV 120 mV 1 0 0 1 0 240 mV 230 mV 1 1 1 0 1 460 mV 130 mV 1 0 0 1 1 260 mV 240 mV 1 1 1 1 0 480 mV 140 mV 1 0 1 0 0 280 mV 250 mV 1 1 1 1 1 500 mV 150 mV 1 0 1 0 1 300 mV Remark If D0 to D4 bits input “00000” to “01010”, EVR value fixed 50 mV (FIL pin voltage fixed 100 mV). FIL pin (peak voltage) is output about double of EVR setting value. [6th byte] The 6th byte sets pulse number during 1VD period of α channel. The pulse number setting 1020 pulses maximum. It is set by eight bits in terms of software. However, the actual circuit uses 10-bit counter with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually generated during fall edge of the first point wait time + first point magnetize wait time (FF2) cycle is the number of pulses input x 4. The number of pulses can be set in a range of 0 to 1020 and in units of four pulses. Table 10. 6th Byte Data Configuration (α channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data Pulse number/VD Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 0 LSB 00000001 4 11111111 1020 n n×4 MSB Data Sheet S14188EJ1V0DS00 21 µPD16879 [7th, 8th byte] The 7th byte and 8th byte set the pulse cycle of the α channel. The pulse cycle is specified using 16 bits: bits D0 (least significant bit) to D7 of the 7th byte, and bits D0 to D7 (most significant bit) of the 8th byte. The pulse cycle can be set to a value in the range of 222 ns to 14.563 ms in units of 222 ns (with a 4.5 MHz clock). Table 11 (A). 7th Byte Data Configuration (α channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 LSB Table 11 (B). 8th Byte Data Configuration (α channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 MSB [9th byte] The 9th byte sets the enable, rotation, and output current of β channel. The enable sets by bit D7, the rotation sets by bit D6, and the output current sets by bits D0 to D4. Bit D5 is fixed “0”. Bit D5 isn’t use. Table 12. 9th Byte Data Configuration (β channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Enable sets MSB Rotation sets LSB Output current sets Enable sets by D7 bit. D7 bit data is “0”: Output high impedance (but, internal counter increase) D7 bit data is “1”: Output conducts Rotation sets by D6 bit. D6 bit data is “0”: Forward turn (CW mode) D6 bit data is “1”: Reverse turn (CCw mode) Output current sets by D0 to D4 bits. The 250 mV (typical) voltage input from external source or internal reference voltage is internally doubled and input to a 5-bit D/A converter. By dividing this voltage by 5-bit data, a current setting reference voltage can be set inside the IC within the range of 100 to 500 mV, in units of 20 mV. If external source is used, the VREFsel pin connects VDD pin. If internal reference voltage is used, the VREFsel pin and VREF pin connect GND pin. The 64 steps micro-step (setting reference voltage is maximum) control is possible. 22 Data Sheet S14188EJ1V0DS00 µPD16879 Table 13. Output Current Setting Reference Voltage Data (β channel data) EVR setting D4 D3 D2 D1 D0 FIL pin voltage 50 mV 0 1 0 1 1 100 mV 60 mV 0 1 1 0 0 70 mV 0 1 1 0 80 mV 0 1 1 90 mV 0 1 100 mV 1 110 mV EVR setting D4 D3 D2 D1 D0 FIL pin voltage 160 mV 1 0 1 1 0 320 mV 120 mV 170 mV 1 0 1 1 1 340 mV 1 140 mV 180 mV 1 1 0 0 0 360 mV 1 0 160 mV 190 mV 1 1 0 0 1 380 mV 1 1 1 180 mV 200 mV 1 1 0 1 0 400 mV 0 0 0 0 200 mV 210 mV 1 1 0 1 1 420 mV 1 0 0 0 1 220 mV 220 mV 1 1 1 0 0 440 mV 120 mV 1 0 0 1 0 240 mV 230 mV 1 1 1 0 1 460 mV 130 mV 1 0 0 1 1 260 mV 240 mV 1 1 1 1 0 480 mV 140 mV 1 0 1 0 0 280 mV 250 mV 1 1 1 1 1 500 mV 150 mV 1 0 1 0 1 300 mV Remark If D0 to D4 bits input “00000” to “01010”, EVR value fixed 50 mV (FIL pin voltage fixed 100 mV). FIL pin (peak voltage) is output about double of EVR setting value. [10th byte] The 10th byte sets pulse number during 1VD period of β channel. The pulse number setting 1020 pulses maximum. It is set by eight bits in terms of software. However, the actual circuit uses 10-bit counter with the loworder two bits fixed to “0”. Therefore, the number of pulses that is actually generated during fall edge of the first point wait time + first point magnetize wait time (FF2) cycle is the number of pulses input × 4. The number of pulses can be set in a range of 0 to 1020 and in units of four pulses. Table 14. 10th Byte Data Configuration (β channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data Pulse number/VD Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 0 LSB 00101001 164 11111111 1020 n n×4 MSB Data Sheet S14188EJ1V0DS00 23 µPD16879 [11th, 12th byte] The 11th byte and 12th byte set the pulse cycle of the β channel. The pulse cycle is specified using 16 bits: bits D0 (least significant bit) to D7 of the 7th byte, and bits D0 to D7 (most significant bit) of the 8th byte. The pulse cycle can be set to a value in the range of 222 ns to 14.563 ms in units of 222 ns (with a 4.5 MHz clock). Table 15 (A). 11th Byte Data Configuration (β channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 LSB Table 15 (B). 12th Byte Data Configuration (β channel data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 MSB [13th byte] The 13th byte is checksum data. Please input the data that sum of the 1st byte to 13th byte is “0”. When the sum is “0”, the stepping operation continued. If the sum is not “0” because data transmission is abnormal, the stepping operation is inhibited and EXT pin (at the Checksum selecting) is held at low level. 24 Data Sheet S14188EJ1V0DS00 µPD16879 About Power Save Mode It is possible that circuit electric current is made small in the power saving (the following PS) mode. Data maintenance just before the PS mode and the maintenance of the phase position are done in the PS mode. Circuit consumption current in the PS mode becomes 300 µA (MAX.) at the time of the outside clock (OSCIN) = 4.5 MHz, and becomes 100 µA (MAX.) at the time of the outside clock (OSCIN) stopped. It can be reduced in less than 1/10 in normal mode. (How to be within PS mode) The establishment of the PS mode is done by a D7 bits of the 4th byte. Please follow the following process when it is within PS mode. (1) Normal operation (Pulse number > 1, enable: conducts) ↓ (2-1) Normal operation (Pulse number = 0, enable: conducts) (2-2) Normal operation (Pulse number = 0, enable: stops) ↓ (3) Please input PS data. (Effective timing of PS mode) • Chopping movement stops at the LATCH falling timing which PS data are contained to. • First point wait count and first point magnetize wait count stop at the next VD rising timing which PS data are contained to. FF1 is fixed on the high level, and FF2 is fixed on low level. • Enable becomes low level at the LATCH falling timing which PS data are contained to. • And, the outside expansion circuit (EXP terminal) works at the time of PS mode too. (PS mode release movement) • Chopping movement resumes at the LATCH falling timing which PS release data are contained to. • First point wait count and first point magnetize wait count resume at the next VD rising timing which PS release data are contained to. • Enalbe becomes high level at the first FF1 falling timing which PS release data are contained to. (When enable data is high level) Data Sheet S14188EJ1V0DS00 25 µPD16879 Data Update Timing The serial data of this product is set and update at the following timing. Table 16. Update Timing of The Data (1) Data Data set Update timing First point wait time LATCH falling edge Next VD rising edge or, next VD falling edge First point magnetize wait time LATCH falling edge FF1 falling edge EXP LATCH falling edge LATCH falling edge Chopping LATCH falling edge LATCH falling edge Power save LATCH falling edge Refer to 25 page The timing at which data is to be update differ, as shown in Table 17, depending on the enable status. Table 17. Update Timing of The Data (2) 1→1 Change of enable 0→1 1→0 0→0 Pulse cycle FF2 ↓ FF2 ↓ FF2 ↓ − Pulse number FF2 ↓ FF2 ↓ FF2 ↓ − Rotation FF2 ↓ FF2 ↓ FF2 ↓ − Enable FF2 ↓ FF1 ↓ FF2 ↓ − EVR LATCH ↓ LATCH ↓ LATCH ↓ VD LATCH FF1 FF2 Pulse out Pulse cycle, Pulse number, Rotation are update Enable is update (at the change of enable: 0 to 1) Output current (EVR) is updated 26 Data Sheet S14188EJ1V0DS00 − µPD16879 Initialization The IC operation can be initialized as follows: (1) Turns ON VDD. (2) Make RESET input low level signal. In initial mode, the operating status of the IC is as shown in Table 18. Table 18. Operations in Initial Mode Item Specification Current consumption 100 µA OSC Input of external clock is inhibited. VD, VD Input inhibited. FF1 to FF7 Low level Pulse out Low level EXP0, EXP1 Low level in the case of (1) above. Previous value is retained in the case of (2) above. Serial operation Can be accessed after initialization in the case of (1) above. Can be accessed after RESET has gone high level in the case of (2) above. Step pulse output is inhibited and FF7 is made low level if the following conditions are satisfied. (1) If the set number of pulses (6th/10th byte) is “0”. (2) If the checksum value is other than “0”. (3) If the first point wait time (FF1) is set to 1VD or longer. (4) If the first point wait time + first point magnetize wait time (FF2) is set to 1VD or longer. (5) If the first point wait time (FF1) is completed earlier than falling timing of LATCH. (6) If VD is not input. Data Sheet S14188EJ1V0DS00 27 µPD16879 Hints on correct use (1) With this product, input the data for first point wait time and first point magnetize wait time. Because the serial data are set or updated by these wait times, if the first point wait time and first point magnetize wait time are not input, the data are not updated. (2) The first point wait time must be longer than LATCH. (3) If the falling of the FF2 is the same as the falling of the last output pulse, a count error occurs, and the IC may malfunction. (4) Transmit the serial data during the first point wait time (FF1). If it is input at any other time, the data may not be transmitted correctly. (5) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to prevent the leakage of noise from the output circuit. 28 Data Sheet S14188EJ1V0DS00 µPD16879 PACKAGE DRAWINGS 38-PIN PLASTIC SSOP (7.62 mm (300)) 38 20 detail of lead end F G 1 P 19 A L E H I J S C N S B K D M M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 12.7±0.3 B 0.65 MAX. C 0.65 (T.P.) D 0.37 +0.05 −0.1 E 0.125±0.075 F 1.675±0.125 G 1.55 H 7.7±0.2 I 5.6±0.2 J 1.05±0.2 K 0.2 +0.1 −0.05 L 0.6±0.2 M 0.10 N 0.10 P +7° 3° −3° P38GS-65-BGG-1 Data Sheet S14188EJ1V0DS00 29 µPD16879 RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For soldering methods and conditions other than those recommended, consult NEC. For details of the recommended soldering conditions, refer to information document “Semiconductor Device Mounting Technology Manual”. Soldering Method Soldering Conditions Recommended Condition Infrared reflow Package peak temperature: 235°C, Time: 30 secs max. (210°C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt%, ax.) is recommended IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 secs max. (200°C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt%, ax.) is recommended. VP15-00-3 Wave soldering Package peak temperature: 260°C; Time: 10 secs max.; Preheating temperature: 120°C max; Number of times: once; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt%, ax.) is recommended. WS60-00-1 Caution Do not use two or more soldering methods in combination. 30 Data Sheet S14188EJ1V0DS00 µPD16879 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14188EJ1V0DS00 31 µPD16879 • The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4