NEC UPD16520

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16520,16520A
VERTICAL DRIVER FOR CCD SENSORS
DESCRIPTION
The µ PD16520 and µ PD16520A are vertical drivers for CCD image sensors that have a level conversion circuit and
a 3-level output function.
Since it incorporates a CCD vertical register driver equivalent to the µ PD16510 (10
channels, consisting of six 3-level channels and four 2-level channels) and a VOD shutter driver (1 channel), it is ideal
as a vertical driver for multiple-electrode high-pixel CCD transfer type area image sensors employed in digital still
cameras.
The µ PD16520 and µ PD16520A use a CMOS process to achieve optimum transmission delay characteristics for
vertical driving of CCD image sensors, as well as output on-state resistance characteristics. The µ PD16520 and
µ PD16520A also support low-voltage logic (logic power supply voltage: 2.0 to 5.5 V).
FEATURES
• CCD vertical register driver: 10 channels (3-level: 6 channels, 2-level: 4 channels)
• VOD shutter driver: 1 channel
• High withstanding voltage: 33 V MAX.
• Low-output on-state resistance: 30 Ω TYP.
• Low-voltage input supported (Logic power supply voltage: 2.0 to 5.5 V)
• Latch-up free
• Same drive capacity as µ PD16510
• Small package: 38-pin plastic SSOP (7.62 mm (300) )
• Super small package: 42-pin wafer level CSP
APPLICATIONS
Digital still cameras, digital video cameras, etc.
ORDERING INFORMATION
Part Number
Package
µ PD16520GS-BGG
38-pin plastic SSOP (7.62 mm (300) )
µ PD16520AFH-2Q1
42-pin wafer level CSP
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S14201EJ3V0DS00 (3rd edition)
Date Published February 2005 NS CP(K)
Printed in Japan
The mark
shows major revised points.
1999, 2003
µ PD16520,16520A
1. PIN CONFIGURATION
(1) 38-pin plastic SSOP (7.62 mm (300) )
µ PD16520GS-BGG (Top view)
2
GND
1
38
VSS
VCC
2
37
VDD1
TI1
3
36
TO1
TI2
4
35
VDD2a
TI3
5
34
TO2
TI4
6
33
TO3
TI5
7
32
VDD2a
TI6
8
31
TO4
PG1
9
30
TO5
PG2
10
29
VDD2A
PG3
11
28
TO6
PG4
12
27
BO1
PG5
13
26
BO2
PG6
14
25
VDD2b
BI1
15
24
BO3
BI2
16
23
BO4
BI3
17
22
SUBO
BI4
18
21
Vsb
SUBI
19
20
VSS
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
(2) 42-pin wafer level CSP
µ PD16520AFH-2Q1 (Bottom view)
13
14
15
16
17
12
33
34
35
18
11
32
42
36
19
10
31
37
20
9
30
38
21
8
29
39
22
7
28
41
40
23
6
27
26
25
24
5
4
3
2
1
Index Mark
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
BO4
15
VSS
29
PG5
2
Vsb
16
VDD1
30
PG2
3
VSS
17
VDD2a
31
TI6
4
BI4
18
TO2
32
TI4
5
BI2
19
TO3
33
TI2
6
BI1
20
TO4
34
GND
7
PG6
21
TO5
35
TO1
8
PG4
22
TO6
36
VDD2a
9
PG3
23
BO2
37
VDD2a
10
PG1
24
BO3
38
VDD2a
11
TI5
25
BO4
39
BO1
12
TI3
26
SUBO
40
VDD2b
13
TI2
27
BI3
41
SUBI
14
TI1
28
BI2
42
VCC
Data Sheet S14201EJ3V0DS
3
µ PD16520,16520A
2. BLOCK DIAGRAM
(1) µ PD16520GS-BGG
GND
38 VSS
1
37 VDD1
VCC
2
TI1
3
+
−
TI2
4
+
−
TI3
5
+
−
TI4
6
+
−
TI5
7
+
−
TI6
8
+
−
PG1
9
+
−
PG2 10
+
−
PG3 11
+
−
PG4 12
+
−
PG5 13
+
−
PG6 14
+
−
BI1 15
+
−
BI2 16
+
−
3-level
36 TO1
35 VDD2a
3-level
34 TO2
3-level
33 TO3
32 VDD2a
3-level
31 TO4
3-level
30 TO5
29 VDD2a
3-level
28 TO6
2-level
27 BO1
2-level
26 BO2
25 VDD2b
BI3 17
+
−
2-level
24 BO3
BI4 18
+
−
2-level
23 BO4
SUBI 19
+
−
2-level
22 SUBO
21 Vsb
20 VSS
4
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
(2) µ PD16520AFH-2Q1
15 VSS
GND 34
16 VDD1
VCC 42
TI1 14
TI2 13
TI2 33
TI3 12
+
−
+
−
TI4 32
+
−
TI5 11
+
−
TI6 31
+
−
PG1 10
+
−
PG2 30
+
−
PG3
9
+
−
PG4
8
+
−
PG5 29
+
−
PG6
7
+
−
BI1
6
+
−
BI2
5
3-level
+
−
+
−
35 TO1
17 VDD2a
36 VDD2a
3-level
18 TO2
3-level
19 TO3
37 VDD2a
3-level
20 TO4
3-level
21 TO5
38 VDD2a
3-level
22 TO6
2-level
39 BO1
2-level
23 BO2
BI2 28
40 VDD2b
BI3 27
+
−
2-level
BI4
+
−
2-level
4
24 BO3
1
BO4
25 BO4
SUBI 41
+
−
2-level
Data Sheet S14201EJ3V0DS
26 SUBO
2
Vsb
3
VSS
5
µ PD16520,16520A
3. PIN FUNCTIONS
(1) µ PD16520GS-BGG
Pin No.
6
Pin Name
I/O
Function
1
GND
−
Ground
2
VCC
−
Logic power supply
3
TI1
Input
3-level driver input (for charge transfer)
4
TI2
Input
(Refer to 4. FUNCTION TABLES.)
5
TI3
Input
6
TI4
Input
7
TI5
Input
8
TI6
Input
9
PG1
Input
3-level driver input (for charge read)
10
PG2
Input
(Refer to 4. FUNCTION TABLES.)
11
PG3
Input
12
PG4
Input
13
PG5
Input
14
PG6
Input
15
BI1
Input
2-level driver input (for charge transfer)
16
BI2
Input
(Refer to 4. FUNCTION TABLES.)
17
BI3
Input
18
BI4
Input
19
SUBI
Input
20
VSS
−
VL power supply
21
Vsb
−
VHH power supply (for SUB drive)
22
SUBO
Output
VOD shutter drive pulse output
23
BO4
Output
2-level pulse output
24
BO3
Output
25
VDD2b
26
BO2
Output
27
BO1
Output
28
TO6
Output
29
VDD2a
30
TO5
Output
31
TO4
Output
32
VDD2a
33
TO3
Output
34
TO2
Output
35
VDD2a
36
TO1
37
VDD1
−
VH power supply
38
VSS
−
VL power supply
−
−
−
−
Output
VOD shutter drive pulse input
VMb power supply (for 2-level driver)
2-level pulse output
3-level pulse output
VMa power supply (for 3-level driver)
3-level pulse output
VMa power supply (for 3-level driver)
3-level pulse output
VMa power supply (for 3-level driver)
3-level pulse output
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
(2) µ PD16520AFH-2Q1
Pin No.
Pin Name
I/O
Function
1
BO4
Output
2-level pulse output
2
Vsb
−
VHH power supply (for SUB drive)
3
VSS
−
VL power supply
4
BI4
Input
2-level driver input (for charge transfer)
5
BI2
Input
(Refer to 4. FUNCTION TABLES.)
6
BI1
Input
7
PG6
Input
3-level driver input (for charge read)
8
PG4
Input
(Refer to 4. FUNCTION TABLES.)
9
PG3
Input
10
PG1
Input
11
TI5
Input
3-level driver input (for charge transfer)
12
TI3
Input
(Refer to 4. FUNCTION TABLES.)
13
TI2
Input
14
TI1
Input
15
VSS
−
VL power supply
16
VDD1
−
VH power supply
17
VDD2a
−
VMa power supply (for 3-level driver)
18
TO2
Output
19
TO3
Output
20
TO4
Output
21
TO5
Output
22
TO6
Output
23
BO2
Output
24
BO3
Output
25
BO4
Output
26
SUBO
Output
27
BI3
Input
2-level driver input (for charge transfer)
28
BI2
Input
(Refer to 4. FUNCTION TABLES.)
29
PG5
Input
3-level driver input (for charge read)
30
PG2
Input
(Refer to 4. FUNCTION TABLES.)
31
TI6
Input
3-level driver input (for charge transfer)
32
TI4
Input
(Refer to 4. FUNCTION TABLES.)
33
TI2
Input
34
GND
−
35
TO1
Output
36
VDD2a
−
37
VDD2a
−
38
VDD2a
39
BO1
40
VDD2b
41
SUBI
42
VCC
3-level pulse output
2-level pulse output
VOD shutter drive pulse output
Ground
3-level pulse output
VMa power supply (for 3-level driver)
−
Output
−
Input
−
2-level pulse output
VMb power supply (for 2-level driver)
VOD shutter drive pulse input
Logic power supply
Data Sheet S14201EJ3V0DS
7
µ PD16520,16520A
4. FUNCTION TABLE (VL = VSS, VMa = VDD2a, VMb = VDD2b, VH = VDD1, VHH = Vsb)
Pins TO1 to TO6
Input
Pin
Output
TI1
TI2
TI3
TI4
TI5
TI6
PG1
PG2
PG3
PG4
PG5
PG6
TO1
TO2
TO3
TO4
TO5
TO6
Pin
3
4
5
6
7
8
9
10
11
12
13
14
36
34
33
31
30
28
No.
14
13,
12
32
11
31
10
30
9
8
29
7
35
18
19
20
21
22
Name
33
L
L
VH
L
H
VMa
H
L
VL
H
H
Remark Pin No. upper row: µ PD16520GS-BGG, lower row: µ PD16520AFH-2Q1
Pins BO1 to BO4
Input
Pin
Output
BI1
BI2
BI3
BI4
BO1
BO2
BO3
BO4
Pin
15
16
17
28
27
26
24
23
No.
6
5,
27
4
39
23
24
Name
28
1,
25
L
VMa
H
VL
Remark Pin No. upper row: µ PD16520GS-BGG, lower row: µ PD16520AFH-2Q1
Pin SUBO
Input
Output
SUBI
SUBO
Pin
19
22
No.
41
26
L
VHH
H
VL
Pin
Name
Remark Pin No. upper row: µ PD16520GS-BGG, lower row: µ PD16520AFH-2Q1
8
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, GND = 0 V)
Parameter
Rating
Unit
VSS
0 to −10
V
VCC
VSS − 0.3 to VSS + 20.0
V
VDD1
VSS − 0.3 to VSS + 33.0
V
VDD2
VSS − 0.3 to VSS + 33.0
V
Vsb
VSS − 0.3 to VSS + 33.0
V
Input pin voltage
VI
VSS − 0.3 to VCC + 0.3
V
Operating ambient temperature
TA
−25 to +85
°C
Storage temperature
Tstg
−40 to +125
°C
Allowable dissipation
Pd
500
mW
Power supply voltage
Symbol
Condition
µ PD16520GS-BGG
µ PD16520AFH-2Q1
600
Note
mW
Note Mounted on 8-layer glass epoxy board of 30 mm x 30 mm x 1.6 mm
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = 25°C, GND = 0 V)
Parameter
Power supply voltage
Symbol
Condition
VCC
MIN.
TYP.
MAX.
Unit
5.5
V
15.0
21.0
V
2.0
VDD1
Note
10.5
VDD1-VSS
Note
16.5
31.0
V
VDD2a
−1.0
+4.0
V
VDD2b
−1.0
+4.0
V
VSS
−10.0
−6.0
V
31.0
V
Vsb-VSS
Note
High level input voltage
VIH
0.8 VCC
VCC
V
Low level input voltage
VIL
0
0.3 VCC
V
Operating ambient temperature
TA
−20
+70
°C
Note Set VDD1 and VSS to values that satisfy VDD1-VSS rating.
Data Sheet S14201EJ3V0DS
9
µ PD16520,16520A
Electrical Characteristics (Unless otherwise specified, TA = 25°C, VDD1 = +15 V, VDD2a = 0 V, VDD2b = +1.0 V,
Vsb = 21.5 V, VCC = +2.5 V, VSS = −7.0 V, GND = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
High level output voltage
VH
IO = −20 µA
VDD1 − 0.1
VDD1
V
Middle level output voltage
VMa
IO = −20 µA
VDD2a − 0.1
VDD2a
V
VMb
IO = 20 µA
VDD2b
VDD2b + 0.1
V
Low level output voltage
VL
IO = 20 µA
VSS
VSS + 0.1
V
SUB high level output voltage
VsubH
IO = −20 µA
Vsb − 0.1
Vsb
V
SUB low level output voltage
VsubL
IO = 20 µA
VSS
VSS + 0.1
V
Output on-state resistance
RL
IO = 10 mA
20
30
Ω
RM
IO = ±10 mA
30
45
Ω
RH
IO = −10 mA
30
40
Ω
30
40
Ω
Rsub
Transmission delay time 1
TD1
No load,
200
ns
Transmission delay time 2
TD2
Refer to Figure 5−2. Timing Chart.
200
ns
Transmission delay time 3
TD3
200
ns
Rise/fall time 1
TP1
Refer to Figure 5−1. Output Load
500
ns
Rise/fall time 2
TP2
Equivalence Circuit and
500
ns
Rise/fall time 3
TP3
Figure 5−2. Timing Chart.
200
ns
10
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
Figure 5−1. Output Load Equivalence Circuit
(a) Between output pins
BO4
(b) Between output pin and GND
TO1
R1
R10
BO3
TO2
BO4'
TO1'
R2
R3
BO2'
TO2'
C1
C10
R9
BO3'
C2
C3 TO3' R3
BO2
C4
BO1'
R7
BO1
TO6'
TO5'
BO1'
R4
R6
TO6
TO4
R5
RGND
TO6
TO5
R4
TO5'
TO6'
BO1
R5
R6
C6
TO4'
C5
R7
TO4
TO3
R8 BO2' C8
C7
TO4'
R2
C9
TO3
TO3'
R8
TO2
TO1'
BO4'
TO2'
BO2
R1
R10
BO3
BO3'
R9
TO1
BO4
TO5
SUBO
C11
Output Load Capacitance Symbol
TO1'
TO2'
TO3'
TO4'
TO5'
TO6'
BO1'
BO2'
BO3'
BO4'
GND
TO1'
−
C_33
C_33
C_33
C_33
C_33
C_32
C_23
C_32
C_23
C1
TO2'
C_33
−
C_33
C_33
C_33
C_33
C_23
C_32
C_23
C_32
C2
TO3'
C_33
C_33
−
C_33
C_33
C_33
C_32
C_23
C_32
C_23
C3
TO4'
C_33
C_33
C_33
−
C_33
C_33
C_23
C_32
C_23
C_32
C4
TO5'
C_33
C_33
C_33
C_33
−
C_33
C_32
C_23
C_32
C_23
C5
TO6'
C_33
C_33
C_33
C_33
C_33
−
C_23
C_32
C_23
C_32
C6
BO1'
C_32
C_23
C_32
C_23
C_32
C_23
−
C_22
C_22
C_22
C7
BO2'
C_23
C_32
C_23
C_32
C_23
C_32
C_22
−
C_22
C_22
C8
BO3'
C_32
C_23
C_32
C_23
C_32
C_23
C_22
C_22
−
C_22
C9
BO4'
C_23
C_32
C_23
C_32
C_23
C_32
C_22
C_22
C_22
−
C10
SUBO
−
−
−
−
−
−
−
−
−
−
C11
Data Sheet S14201EJ3V0DS
11
µ PD16520,16520A
Output Load Equivalence Circuit Constants
Parameter
Symbol
Constant
Vertical register serial resistor
R1 to R10
0Ω
Vertical register ground resistor
PGND
0Ω
Capacitance 1 between vertical register clocks (3-level - 3-level)
C_33
0 pF
Capacitance 2 between vertical register clocks (2-level - 2-level)
C_22
0 pF
Capacitance 3 between vertical register clocks (3-level - 2-level)
C_32
1000 pF
Capacitance 4 between vertical register clocks (2-level - 3-level)
C_23
500 pF
Vertical register ground capacitance 1 (3-level)
C1 to C6
3000 pF
Vertical register ground capacitance 2 (2-level)
C7 to C10
1500 pF
Substrate ground capacitance
C11
1600 pF
Figure 5−2. Timing Chart
BI1 to BI4
TI1 to TI6
TD1
TD1
VMb
VMa
BO1 to BO4
TO1 to TO6
VL
TP1
TP1
PG1 to PG6
TD2
TD2
VH
TO1 to TO6
VMa
TP2
TP2
SUBI
TD3
TD3
VHH
SUBO
VL
TP3
12
Data Sheet S14201EJ3V0DS
TP3
µ PD16520,16520A
6. NOTE ON USE
6.1 Power ON/OFF Sequence
In the µ PD16520 and µ PD16520A, a PN junction (diode) exists between VDD2 → VDD1, input pin (TI1 to TI6, PG1
to PG6, BI1 to BI4, and SUBI) → VCC, so that in the case of voltage conditions: VDD2 > VDD1, input pin voltage (TI1
to TI6, PG1 to PG6, BI1 to BI4, and SUBI) > VCC, an abnormal current flows. Therefore, when turning the power
ON/OFF, make sure that the following voltage conditions are satisfied: VDD2 ≤ VDD1, input pin voltage (TI1 to TI6,
PG1 to PG6, BI1 to BI4, and SUBI) ≤ VCC. Also, to minimize the negative potential applied to the SUB pin of the CCD
image sensor, following the power ON/OFF sequence described below.
(1) Power ON
<1> Powering ON VCC
Make sure that input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, and SUBI) ≤ VCC. Also, when Vsb = 2 V,
make sure that VCC reaches the rated voltage.
<2> Powering ON Vsb, VDD1, VDD2a, VDD2b and VSS
At this time, make SUBI high level (0.8VCC or higher) .
Vsb
VDD1
VCC
VDD2a, VDD2b
2V
0V
<1>
<2>
VSS
Time
Data Sheet S14201EJ3V0DS
13
µ PD16520,16520A
(2) Power OFF
<1> Powering OFF Vsb, VDD1, VDD2a, VDD2b and VSS
Until VCC power OFF, keep SUBI high level (0.8VCC or higher) .
<2> Powering OFF VCC
Power OFF VCC when Vsb becomes 2 V or lower. At this time, make sure that the input pin voltage (TI1 to TI6,
PG1 to PG6, BI1 to BI4, and SUBI) ≤ VCC.
<1>
Vsb
VDD1
<2>
VCC
VDD2a, VDD2b
2V
0V
VSS
Time
6.2 Recommended Connection of Unused Pins
Handle input pins and output pins that are not used as follows.
Input pin: High level (connect to VCC)
Output pin: Leave open
14
Data Sheet S14201EJ3V0DS
VSS
1
2
TG/SSG
Data Sheet S14201EJ3V0DS
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Vsb
VDD2b
VSUB (Substrate voltage)
CCD
µ PD16520GS-BGG
GND
VCC
TI1
TI2
TI3
TI4
TI5
TI6
PG1
PG2
PG3
PG4
PG5
PG6
BI1
BI2
BI3
BI4
SUBI
VDD1
VSS
VDD1
TO1
38
37
36
35
34
TO2
33
TO3
32
VDD2a
31
TO4
30
TO5
29
VDD2a
28
TO6
27
BO1
26
BO2
25
VDD2b
24
BO3
23
BO4
22
SUBO
21
Vsb
20
VSS
VDD2a
+
1 µF
0.1 µF 0.1 µF 0.1 µF 0.1 µF
0.1 µF
15
µ PD16520,16520A
1 MΩ
0.1 µF
7. APPLICATION CIRCUIT EXAMPLE
VCC
µ PD16520,16520A
8. PACKAGE DRAWINGS
38-PIN PLASTIC SSOP (7.62 mm (300))
38
20
detail of lead end
F
G
1
P
19
A
L
E
H
I
J
S
C
N
S
B
K
D
M
M
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
12.7±0.3
B
0.65 MAX.
C
0.65 (T.P.)
D
0.37 +0.05
−0.1
E
0.125±0.075
F
1.675±0.125
G
1.55
H
7.7±0.2
I
5.6±0.2
J
1.05±0.2
K
0.2 +0.1
−0.05
L
0.6±0.2
M
0.10
N
0.10
P
3° +7°
−3°
P38GS-65-BGG-1
16
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
42-PIN WAFER LEVEL CSP (Unit: mm)
w S B
w S A
D
ZD
Pitch 0.5 x (5 − 1) = 2.0
9
E
Pitch 0.5 x (9 − 1) = 4.0
8
7
6
5
4
INDEX φ 0.25
3 Solder ball is not
loaded yet.
2
1
ZE
INDEX MARK
t S A B
C Block
// y1 S
y S
A1
A
A2
C Block Details
E
D
42 − φ b
Parameter MIN.
D
2.98
E
4.99
ZD
−
ZE
−
e
t
A
0.66
A1
0.18
A2
0.48
b
0.25
y
−
x
−
w
−
y1
−
Data Sheet S14201EJ3V0DS
C
B
A
φxM S A B
Standard
TYP. MAX.
3.03
3.08
5.04
5.09
0.515
−
0.520
−
0.5
0.15
0.73
0.8
0.23
0.28
0.50
0.52
0.30
0.35
−
0.08
−
0.05
−
0.20
−
0.20
17
µ PD16520,16520A
9. RECOMMENDED SOLDERING CONDITIONS
The µ PD16520 and µ PD16520A should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
µ PD16520GS-BGG: 38-pin plastic SSOP (7.62 mm (300) )
Process
Infrared reflow
Conditions
Peak temperature: 235°C or below (package surface temperature) ,
Symbol
IR35-00-3
Reflow time: 30 seconds or less (at 210°C or higher) ,
Maximum number of reflow processes: 3 times or less.
Vapor phase soldering
Peak temperature: 215°C or below (package surface temperature) ,
VP15-00-3
Reflow time: 40 seconds or less (at 200°C or higher) ,
Maximum number of reflow processes: 3 times or less.
Wave soldering
Solder temperature: 260°C or below, Flow time: 10 seconds or less,
WS60-00-1
Maximum number of flow processes: 1 time,
Pre-heating temperature: 120° or below (package surface temperature) .
Partial heating method
−
Pin temperature: 300°C or below,
Heat time: 3 seconds or less (per each side of the device) .
µ PD16520AFH-2Q1: 42-pin wafer level CSP
Process
Infrared reflow
Conditions
Peak temperature: 260°C or below (package surface temperature) ,
Reflow time: 60 seconds or less (at 220°C or higher) ,
Maximum number of reflow processes: 3 times or less.
Caution Do not use different soldering methods together (except for partial heating) .
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades on NEC Semiconductor Devices (C11531E)
18
Data Sheet S14201EJ3V0DS
Symbol
IR60-00-3
µ PD16520,16520A
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet S14201EJ3V0DS
19