DATA SHEET MOS INTEGRATED CIRCUIT µPD16520 VERTICAL DRIVER FOR CCD SENSORS The µPD16520 is a vertical driver for CCD image sensors that has a level conversion circuit and a 3-level output function. Since it incorporates a CCD vertical register driver equivalent to the µPD16510 (10 channels, consisting of six 3-level channels and four 2-level channels) and a VOD shutter driver (1 channel), it is ideal as a vertical driver for multiple-electrode high-pixel CCD transfer type area image sensors employed in digital still cameras. The µPD16520 uses a CMOS process to achieve optimum transmission delay characteristics for vertical driving of CCD image sensors, as well as output on-state resistance characteristics. The µPD16520 also supports low-voltage logic (logic supply voltage: 2.0 to 5.5 V). FEATURES • CCD vertical register driver: 10 channels (3-level: 6 channels, 2-level: 4 channels) • VOD shutter driver: 1 channel • High withstand voltage: 33 V Max. • Low-output on-state resistance: 30 Ω TYP. • Low-voltage input supported (Logic supply voltage: 2.0 to 5.5 V) • Latch-up free • Same drive capacity as µPD16510 • Small package: 38-pin plastic shrink SOP (300 mil) APPLICATIONS Digital still cameras, digital video cameras, etc. ORDERING INFORMATION Part Number Package µPD16520GS-BGG 38-pin plastic shrink SOP (300 mil) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14201EJ1V0DS00 (1st edition) Date Published May 1999 N CP(K) Printed in Japan © 1999 µPD16520 PIN CONFIGURATION (TOP VIEW) • 38-pin plastic shrink SOP (300 mil) µPD16520GS-BGG GND 1 38 VSS Vcc 2 37 VDD1 TI1 3 36 TO1 TI2 4 35 VDD2a TI3 5 34 TO2 TI4 6 33 TO3 TI5 7 32 VDD2a TI6 8 31 TO4 PG1 9 30 TO5 PG2 10 29 VDD2a PG3 11 28 TO6 PG4 12 27 BO1 PG5 13 26 BO2 PG6 14 25 VDD2b BI1 15 24 BO3 BI2 16 23 BO4 BI3 17 22 SUBO BI4 18 21 Vsb SUBI 19 20 Vss PIN NAMES BI1 to BI4: 2 Level Driver Input TO1 to TO6: 3 Level Pulse Output BO1 to BO4: 2 Level Pulse Output VDD1: Power Supply (VH) GND: Ground VDD2a: Power Supply (VMa) PG1 to PG6: 3 Level Driver Input VDD2b: Power Supply (VMb) SUBI: VOD Shutter Drive Pulse Input VCC: Power Supply (Logic) SUBO: VOD Shutter Drive Pulse Output Vsb: Power Supply (VHH) TI1 to TI6: 3 Level Driver Input VSS: Power Supply (VL) 2 Data Sheet S14201EJ1V0DS00 µPD16520 BLOCK DIAGRAM GND 1 Vcc 2 TI1 3 + − TI2 4 + − TI3 5 + − TI4 6 + − TI5 7 + − TI6 8 3 level + − PG2 10 + − PG3 11 + − PG4 12 + − PG5 13 + − Vss 37 VDD1 36 TO1 35 VDD2a 3 level 34 3 level 33 TO3 + − PG1 9 38 TO2 32 VDD2a 3 level 31 TO4 3 level 30 TO5 29 VDD2a 3 level 28 TO6 PG6 14 + − BI1 15 + − 2 level 27 BO1 BI2 16 + − 2 level 26 BO2 25 BI3 VDD2b 17 + − 2 level 24 BO3 BI4 18 + − 2 level 23 BO4 22 SUBO SUBI 19 + − 2 level 21 Vsb 20 Vss Data Sheet S14201EJ1V0DS00 3 µPD16520 1. PIN FUNCTIONS Pin No. 4 Pin Name I/O Function 1 GND − Ground 2 VCC − Logic power supply 3 TI1 I 4 TI2 I 3-level driver input (for charge transfer) (See Function Tables.) 5 TI3 I 6 TI4 I 7 TI5 I 8 TI6 I 3-level driver input (for charge read) (See Function Tables.) 9 PG1 I 10 PG2 I 11 PG3 I 12 PG4 I 13 PG5 I 14 PG6 I 15 BI1 I 16 BI2 I 17 BI3 I 18 BI4 I 19 SUBI I VOD shutter drive pulse input 20 VSS − VL power supply 21 Vsb − VHH power supply (for SUB drive) 22 SUBO O VOD shutter drive pulse output 23 BO4 O 2-level pulse output 24 BO3 O 25 VDD2b − VMb power supply (for 2-level driver) 26 BO2 O 2-level pulse output 27 BO1 O 28 TO6 O 3-level pulse output 29 VDD2a − VMa power supply (for 3-level driver) 30 TO5 O 3-level pulse output 31 TO4 O 32 VDD2a − VMa power supply (for 3-level driver) 33 TO3 O 3-level pulse output 34 TO2 O 35 VDD2a − VMa power supply (for 3-level driver) 36 TO1 O 3-level pulse output 37 VDD1 − VH power supply 38 VSS − VL power supply 2-level driver input (for charge transfer) (See Function Tables.) Data Sheet S14201EJ1V0DS00 µPD16520 Function Tables VL = VSS, VMa = VDD2a, VMb = VDD2b, VH = VDD1, VHH = Vsb Pins TO1 to TO6 Input Pin Name Pin No. TI1 TI2 TI3 3 4 5 Output TI4 TI5 TI6 PG1 PG2 PG3 6 7 8 9 10 11 PG4 PG5 PG6 12 13 14 TO1 TO2 TO3 TO4 TO5 TO6 36 34 33 31 L L VH L H VMa H L VL H H VL 30 28 Pins BO1 to BO4 Input Output Pin Name BI1 BI2 BI3 BI4 BO1 BO2 BO3 BO4 Pin No. 15 16 17 18 27 26 24 23 L VMb H VL Pin SUBO Pin Name Pin No. Input Output SUBI SUBO 19 22 L VHH H VL Data Sheet S14201EJ1V0DS00 5 µPD16520 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, GND = 0 V) Parameter Supply voltage Ratings Unit VSS Symbol Conditions 0.0 to −10 V VCC VSS − 0.3 to VSS + 20.0 V VDD1 VSS − 0.3 to VSS + 33.0 V VDD2 VSS − 0.3 to VSS + 33.0 V Vsb VSS − + 33.0 V Input pin voltage VI VSS − 0.3 to VCC + 0.3 V Operating ambient temperature TA −25 to +85 °C Storage temperature Tstg −40 to +125 °C Allowable dissipation Pd 500 mW Caution 0.3 to VSS Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = 25°°C, GND = 0 V) Parameter Supply voltage Symbol VCC MIN. TYP. MAX. 5.5 V 15.0 21.0 V 2.0 VDD1 Note VDD1-VSS Note 10.5 Unit 16.5 31.0 V VDD2a −1.0 +4.0 V VDD2b −1.0 +4.0 V VSS −10.0 −6.0 V Vsb-VSS Input voltage, high Conditions 31.0 V 0.8VCC VCC V Note VIH Input voltage, low VIL 0 0.3VCC V Operating ambient temperature TA −20 +70 °C Note Set VDD1 and VSS to values that satisfy VDD1-VSS rating. 6 Data Sheet S14201EJ1V0DS00 µPD16520 Electrical Specifications (Unless otherwise specified, VDD1 = +15 V, VDD2a = 0 V, VDD2b = +1.0 V, Vsb = +21.5 V, VCC = +2.5 V, VSS = −7.0 V, TA = 25°°C, GND = 0 V) MAX. Unit Output voltage, high Parameter VH Symbol IO = −20 µA Conditions VDD1 − 0.1 MIN. VDD1 V Output voltage, middle VMa IO = −20 µA VDD2a − 0.1 VDD2a V VMb IO = 20 µA VDD2b VDD2b + 0.1 V Output voltage, low VL IO = 20 µA VSS VSS + 0.1 V Output voltage, sub-high VsubH IO = −20 µA Vsb − 0.1 Vsb V Output voltage, sub-low VsubL IO = 20 µA VSS VSS + 0.1 V Output on-state resistance RL IO = 10 mA 20 30 Ω RM IO = ±10 mA 30 45 Ω RH IO = −10 mA 30 40 Ω 30 40 Ω 200 ns 200 ns 200 ns 500 ns 500 ns 200 ns Rsub Transmission delay time 1 TD1 Transmission delay time 2 TD2 Transmission delay time 3 TD3 Rise/fall time 1 TP1 Rise/fall time 2 TP2 Rise/fall time 3 TP3 No load See Figure 2-2 Timing Charts. See Figure 2-1 Output Load Equivalence Circuit. See Figure 2-2 Timing Charts. Data Sheet S14201EJ1V0DS00 TYP. 7 µPD16520 Figure 2-1. Output Load Equivalence Circuit (a) Between output pins BO4 TO1 BO4 BO3 R1 R10 BO3 (b) Between output pin and GND BO4' TO2 TO1' BO4' TO1' R9 BO3' C2 C9 BO2 R8 BO2' C8 TO3' R8 R4 TO4' C5 TO6' BO1 R6 TO5' R5 RGND TO6 TO6 TO4 TO4 R5 R6 TO5' TO6' BO1 R4 C6 R7 TO4' R7 TO3 C4 C7 BO1' BO1' TO3' R3 C3 TO3 R3 BO2' R2 TO2' C1 C10 BO3' TO2' BO2 R1 R10 TO2 R2 R9 TO1 TO5 TO5 SUB0 C11 Output Load Capacitance Symbol TO1' TO2' TO3' TO4' TO5' TO6' BO1' BO2' BO3' BO4' GND TO1' − C_33 C_33 C_33 C_33 C_33 C_32 C_23 C_32 C_23 C1 TO2' C_33 − C_33 C_33 C_33 C_33 C_23 C_32 C_23 C_32 C2 TO3' C_33 C_33 − C_33 C_33 C_33 C_32 C_23 C_32 C_23 C3 TO4' C_33 C_33 C_33 − C_33 C_33 C_23 C_32 C_23 C_32 C4 TO5' C_33 C_33 C_33 C_33 − C_33 C_32 C_23 C_32 C_23 C5 TO6' C_33 C_33 C_33 C_33 C_33 − C_23 C_32 C_23 C_32 C6 BO1' C_32 C_23 C_32 C_23 C_32 C_23 − C_22 C_22 C_22 C7 BO2' C_23 C_32 C_23 C_32 C_23 C_32 C_22 − C_22 C_22 C8 BO3' C_32 C_23 C_32 C_23 C_32 C_23 C_22 C_22 − C_22 C9 BO4' C_23 C_32 C_23 C_32 C_23 C_32 C_22 C_22 C_22 − C10 − − − − − − − − − − C11 SUBO 8 Data Sheet S14201EJ1V0DS00 µPD16520 Output Load Equivalence Circuit Constants Parameter Symbol Vertical register serial resistor Constant 0Ω R1 to R10 Vertical register ground resistor RGND 0Ω Capacitance 1 between vertical register clocks (3 level-3 level) C_33 0 pF Capacitance 2 between vertical register clocks (2 level-2 level) C_22 0 pF Capacitance 3 between vertical register clocks (3 level-2 level) C_32 1000 pF Capacitance 4 between vertical register clocks (2 level-3 level) C_23 500 pF Vertical register ground capacitance 1 (3 level) C1 to C6 3000 pF Vertical register ground capacitance 2 (2 level) C7 to C10 1500 pF Substrate ground capacitance C11 1600 pF Figure 2-2. Timing Charts BI1 to BI4 TI1 to TI6 TD1 TD1 VMb VMa BO1 to BO4 TO1 to TO6 VL TP1 TP1 PG1 to PG6 TD2 TD2 VH TO1 to TO6 VMa TP2 TP2 SUBI TD3 TD3 VHH SUBO VL TP3 Data Sheet S14201EJ1V0DS00 TP3 9 µPD16520 3. CAUTIONS 3.1 Power ON/OFF Sequence In the µPD16520, a PN junction (diode) exists between VDD2 → VDD1, input pin (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) → VCC, so that in the case of voltage conditions: VDD2 > VDD1, input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) > VCC, an abnormal current flows. Therefore, when turning the power ON/OFF, make sure that the following voltage conditions are satisfied: VDD2 ≤ VDD1, input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) ≤ VCC. Also, to minimize the negative potential applied to the SUB pin of the CCD image sensor, following the power ON/OFF sequence described below. (1) Power ON <1> Powering ON VCC Make sure that input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) ≤ VCC. Also, when Vsb = 2 V, make sure that VCC reaches the rated voltage. <2> Powering ON Vsb, VDD1, VDD2a, VDD2b, VSS At this time, make SUBI high level (0.8VCC or higher). Vsb VDD1 Vcc VDD2a, VDD2b 0V 2V <1> <2> Vss Time 10 Data Sheet S14201EJ1V0DS00 µPD16520 (2) Power OFF <1> Powering OFF Vsb, VDD1, VDD2a, VDD2b, V SS Until VCC power OFF, keep SUBI high level (0.8V CC or higher). <2> Powering OFF VCC Power OFF VCC when Vsb becomes 2 V or lower. At this time, make sure that the input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) ≤ VCC. <1> Vsb VDD1 <2> Vcc VDD2a, VDD2b 2V 0V Vss Time 3.2. Recommended Connection of Unused Pins Handle input pins and output pins that are not used as follows. Input pin: High level (connect to VCC) Output pin: Leave open Data Sheet S14201EJ1V0DS00 11 TG/SSG 12 0.1µF VCC TI6 TI3 TI4 TI5 TI2 TI1 GND VCC PG1 10 PG2 11 PG3 12 PG4 13 PG5 14 PG6 15 BI1 16 BI2 17 BI3 18 BI4 19 SUBI 7 8 9 1 2 3 4 5 6 38 VSS 37 VDD1 36 TO1 35 VDD2a 34 TO2 33 TO3 32 VDD2a 31 TO4 30 TO5 29 VDD2a 28 TO6 27 BO1 26 BO2 25 VDD2b 24 BO3 23 BO4 22 SUBO 21 Vsb 20 VSS µ PD16520GS-BGG 0.1µF 0.1µF VDD1 0.1µF VSS 0.1µF Vsb 0.1µF VDD2b Data Sheet S14201EJ1V0DS00 1µF + 1MΩ VSUB (Substrate voltage) CCD µPD16520 4. APPLICATION CIRCUIT EXAMPLE µPD16520 5. PACKAGE DRAWING 38-PIN PLASTIC SSOP (300 mil) 38 20 detail of lead end F G 1 P 19 A L E H I J S C N S B K D M M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 12.7±0.3 B 0.65 MAX. C 0.65 (T.P.) D 0.37+0.05 −0.1 E 0.125±0.075 F 1.675±0.125 G H 1.55 7.7±0.2 I J 5.6±0.2 1.05±0.2 K 0.2 +0.1 −0.05 L 0.6±0.2 M 0.10 N 0.10 P 3°+7° −3° P38GS-65-BGG Data Sheet S14201EJ1V0DS00 13 µPD16520 6. RECOMMENDED SOLDERING CONDITIONS The µPD16520 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 6-1. Surface Mounting Type Soldering Conditions • µPD16520GS-BGG: 38-pin plastic shrink SOP (300 mil) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260°C, Time: 10 sec. Max., Count: Once, Preheating temperature: 120°C Max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row) Caution 14 Do not use different soldering methods together (except for partial heating). Data Sheet S14201EJ1V0DS00 − µPD16520 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14201EJ1V0DS00 15 µPD16520 • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8