TB62718AFG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62718AFG Controller and Driver for Full-color LED Modules and Panels The TB62718AFG is an LED driver which is suitable for driving full-color LED modules. This device has built-in 8 bit PWM grayscale and an output current adjustment functions. It can turn on to 16 LEDs. This device has a heat sink fitting side on the surface of the package. Then, a heat sink will dissipate heat generated in the device. In addition, this device incorporates built-in TSD (thermal Shutdown) and output-open detection functions to protect the device. Features • Output current capability and number of outputs: 90 mA × 16 outputs • Constant current range: 5 mA~75 mA • Application output voltage: 0.7 V (output current 5 mA~90 mA) • Adjustment function Weight: 0.26 g (typ.) 1. Standard current adjustment (8-bit serial data input) This function supports standard current adjustment using an external resistance connected to the REXT pin. 2 high-order bits … Output current can be adjusted to any one of 4 levels in the range 25%~100%. 6 low-order bits … Output current can be adjusted to any one of 64 levels in the range 40%~100%. 2. Each dot adjustment (128-bit serial data input) This function allows adjustment of the current value for each output (dot). … Output current can be adjusted to any one of 64 levels in the range 20%~100%. 3. All dot adjustment 1 (8-bit parallel data input) This function allows adjustment of brightness for each LED module. 5 low-order bits … Output current can be adjusted to any one of 32 levels in the range 50%~100%. 4. All dot adjustment 2 (8-bit parallel data input) This function allows changes to the frequency of the PWM clock and allows major brightness adjustment for the display. 3 high-order bits … PWM clock frequency can be adjusted to any one of 8 levels in the range 1/1~1/8. 5. 256-grayscale PWM function (8-bit parallel input) This function controls the pulse width for each output, yielding 256 grayscales. Maximum PWM clock frequency 10 MHz (for all temperature range), Minimum pulse width 2 ms • Accuracy of bits in constant-current output levels prior to adjustment ±6.0% max (for output current of 40 mA~80 mA) ±7.0% max (for output current of 20 mA~40 mA) ±12.0% max (for output current of 5 mA~20 mA) • Protection functions 1. Thermal shutdown function (TSD) This function monitors the rise in junction temperature. Connect a pull-up resistor to the ALARM1 pin in order to monitor the temperature. 2. Output Pin Open Detection function This function detect when an output pin is open. Connect a pull-up resistor to the ALARM2 pin in order to monitor this. Company Headquarters 3 Northway Lane North Latham, New York 12110 Toll Free: 800.984.5337 Fax: 518.785.4725 Web: www.marktechopto.com | Email: [email protected] California Sales Office: 950 South Coast Drive, Suite 265 Costa Mesa, California 92626 Toll Free: 800.984.5337 Fax: 714.850.9314 TB62718AFG • For anode-common LEDs • Input signal voltage level: CMOS level (Schmitt trigger input) • Power supply voltage range VDD = 4.5 V~5.5 V • Maximum output pin voltage: 26 V • Serial and parallel data transfer rate: 20 MHz (max, cascade connection) • Operating temperature range Topr = −40°C~85°C • Package: HQFP64-P-1010-0.50. A Heat sink can be fitted. Warnings Short-circuiting an output pin to GND or to the power supply pin may destroy the device. Take care when wiring the output pins, the power supply pin and the GND pins (VSS, VSS2). Do not apply either positive or negative voltages to the heat sink on the surface of the IC. In addition, do not solder anything to the heat sink. 2 2005-04-20 TB62718AFG Pin Assignment (top view) and Markings 48 DOE 33 49 32 TB62718AFG SI DATA OUT 01 OUT 02 SI CLK OUT 03 SI LATCH OUT 04 SI SEL OUT 05 PWMCLK OUT 06 BCEN OUT 07 DCEN VSS2 RESET VSS2 LED TEST OUT 08 BLANK OUT 09 REXT OUT 10 VSS OUT 11 SO DATA OUT 12 TSENA OUT 13 5WWKA** 64 17 VSS2 NC VDD PO DATA 07 PO DATA 06 PO DATA 05 PO DATA 04 PO DATA 03 PO DATA 02 PO DATA 01 PO DATA 00 VSS ALARM2 TEST1 16 ALARM1 1 OUT 14 OUT 15 TEST0 Note: OUT 00 VSS2 NC VDD PI DATA 08 PI DATA 07 PI DATA 06 PI DATA 05 PI DATA 04 PI DATA 03 PI DATA 02 PI DATA 01 VSS PI CLK PI LATCH PI SEL Package type: HQFP64-P-1010-0.50 Indicates device name on the upper surface of the package. Indicates weekly code on the lower surface of the package. Details of weekly code on lower surface: From left, 1st character = rightmost digit of year 0 for 2000, 1 for 2001 2nd and 3rd characters = week of manufacture during year: maximum value = 52. 4th characters = manufacturing factory (‘K’ means the Kita Kyushu factory.) 5th to 7th characters = lot number within week 1st lot is A11, 2nd lot is A1 and 3rd lot is A. 4th lot is B11, 5th lot is B1 and 6th lot is B. 64th lot is Z11, 65th lot is Z1 and 66th lot is Z. The four characters of ‘I’, ‘M’, ‘O’ and ‘W’ are not used. 3 2005-04-20 TSENA ALARM1 ALARM2 BLANK LED TEST DOE PO DATA 00 ~PO DATA 07 OUT 00~OUT 15 DCEN PI LATCH BCEN PI CLK 8 8 16 5 TSD1 circuit PWMCLK 4 V/I conversion circuit generator circuit (8 bits) PWM pulse 8 8-bit clock counter 3-bit Clock counter DAC4 8 3 Output-open detection circuit 16 × 6 bit DACs and 16 constant-current outputs TSD2 circuit 8 & latch (16 × 8 bits) 8 data register latch (1 × 8 bits) PI REG2 data register & 8 PWM PI REG1 8 8 PI DATA 00 ~PI DATA 07 All dot adjustment PI SEL Block Diagram (entire device) For PI REG1, PI REG2, SI REG1 and SI REG2 1 × 5-bit DAC DAC3 & latch (1 × 128 bits) 1 × 6-bit DAC DAC2 1 × 2-bit DAC DAC1 register & latch (1 × 8 bits) register 128 current adjustment data adjustment data Standard SI REG1 Each dot SI REG2 SI DATA SI SEL 2005-04-20 RESET REXT SO DATA SI LATCH SI CLK TB62718AFG TB62718AFG Constant Current Adjustment Range (graph) This graph shows how current may be adjusted to a fraction of its full-scale value. Note 1: In each case, the value input to each DAC is the value output from the previous DAC. Reference: Current adjustment functions DAC1 to DAC3 are the current adjustment functions for all outputs. The adjustment width of DAC1 is large and approximate (1 LSB ∼ − 25%). The adjustment width of DAC2 is the smallest and has a large error (1 LSB ∼ − 0.9%). The adjustment width of DAC3 is small. DAC3 is a high-performance DAC with a small error (1 LSB ∼ − 1.61%). Therefore, It is recommended that DAC1 and DAC2 be used for adjusting the REXT resistance. It is recommended that DAC3 be used for adjusting brightness between module. (after it was set and it had DAC4 adjusted to the dot.) The beginning is set in about 75% of the middle value, after that, it is effective to use ±25% of set width. DAC4 is the current adjustment function for all outputs. The adjustment width of DAC4 is small. But it is a high-performance DAC with a small error (1 LSB ∼ − 1.27%). And also, DAC4 has a very wide setting range. Therefore, DAC4 can be used to adjust the brightness of LEDs without a rank classification. This method allows brightness to be adjusted with a degree of accuracy of 1.27% of full scale. Note 2: Assuming precise linear correlation between output current and LED brightness 5 2005-04-20 TB62718AFG Equivalent Input and Output Circuits (resistance values are typical values.) Input pins with pull-up resistor Input pins with pull-down resistor. TSENA, BLANK, BC/DCEN VDD IN SI/PI LATCH, PI DATA 00~PI DATA 07, LED TEST R (UP) = 300 kΩ VDD IN 1 kΩ GND GND R (DOWN) = 300 kΩ Output terminals Input terminals PO DATA 00~PO DATA 07, SO DATA (A) SI DATA, SI CLK, PI CLK, PWMCLK (B) RESET , DOE , PI SEL, SI SEL VDD VDD IN 1 kΩ 100 Ω Rin OUT GND GND (A) Rin = 250 Ω (B) Rin = 1 kΩ Protection circuit monitor terminals Constant-current output terminals OUT 00~OUT 15 ALARM1 & ALARM2 Parasitic diode Parasitic diode VSS2 VSS 6 2005-04-20 TB62718AFG Explanation of Pin Functions Table No. Name I/O Function Explanation 4, 45 VSS P ⎯ 35, 14 NC ⎯ ⎯ Logic ground pins. Be sure to use all. Unused This pin is used to reset the IC’s built-in temperature monitoring circuit (TSD). Rising edge of input signal re-enables outputs which had been forced to OFF. The latched data as the setting is not reset. Either in case of H- or L-level of this terminals can be operated TSD circuit. 63 TSENA I Pullup 15, 24, 25, 34 VSS2 P ⎯ Ground pin for output. Be sure to use all. 13, 36 VDD P ⎯ Logic power supply input pins. Be sure to use all. 16~23, 26~33 OUT 00~ OUT 15 O ⎯ LED drive output pins. Connect to cathode of LED. 50 SI DATA I ⎯ Serial data input pin. Used for input of standard current adjustment data and dot adjustment data 51 SI CLK I ⎯ Serial data transfer clock input pin. Data is transferred positive edge. 52 SI LATCH I 53 SI SEL I 62 SO DATA O 37~44 PI DATA 00~ PI DATA 07 I 46 PI CLK I PullSerial data latch signal input pin. Data is held on positive edge. down ⎯ Serial data selection pin. Either standard current adjustment data or dot adjustment data may be selected. ⎯ Serial data output pin. The output data type is selected using SI SEL. PullInput pins for parallel data. Inputs for all output adjustment data and PWM data down ⎯ Input pin for parallel data transfer clock. Data is transferred on positive edge. PullInput pin for parallel data latch signal. Data is held on rising positive edge. down 47 PI LATCH I 48 PI SEL I ⎯ Parallel data selection pin. Either all output adjustment data or PWM data may be selected. 5~12 PO DATA 00~ PO DATA 07 O ⎯ Output pin for parallel data. The output data type is selected using PISEL. 49 DOE I ⎯ Control pin for parallel data output PODATA. PIDATA is out on input of an H-level signal. PIDATA is set to High-impedance by input of an L-level signal. 59 BLANK I Pullup 54 PWMCLK I ⎯ 55 BCEN I Pullup Selection signal input pin for all output adjustment functions. All output adjustment is fixed to 100% when this signal is Low. All bit adjustments become effective when it is High. It isn’t influent anything to all output adjustment by PWMCLK. 56 DCEN I Pullup Selection signal input pin for dot adjustment function. Dot adjustment value is fixed to 100% when this signal is Low. Dot adjustment becomes effective when it is High. 57 RESET I ⎯ 58 LED TEST I 60 REXT P ⎯ Connection pin of resistor for setting for the current. 2 ALARM1 O ⎯ Open-drain monitor pin for TSD circuit. When the TSD circuit detects an abnormal temperature, this signal is turned ON. IO monitor the TSD circuit connect this pin to a pull-up resistor. ALARM1 is independent of the RESET signal. 3 ALARM2 O ⎯ Open-drain monitor pin for output-open detection circuit. When an open output is detected, this signal is turned ON. 1, 64 TEST 0, TEST 1 I ⎯ Pins for the device testing. Connect all these pins to ground. Pin attributes PWM circuit control signal input pin. Output is turn OFF by input of an H-level signal. PWM output is initiated by input of an L-level signal accordingly to the input data. Standard clock input pin for PWM circuit. One clock cycle is equivalent to the minimum pulse width of the PWM output. Reset signal input pin. Setting and registered data are reset when it is Low. A reset also releases TSD. Connection confirmation signal input pin for an LED. When this signal is High, all outputs Pullare ON. down This signal should normally be kept Low. P: power supply/ground/other, I: input pin, O: output pin Note 3: It is recommended that pins with pull-up or pull-down resistors not be left open. Ambient noise may cause malfunction of the device. 7 2005-04-20 TB62718AFG Absolute Maximum Ratings (Topr = 25°C unless otherwise specified) Characteristics Supply voltage Symbol Rating Unit VDD −0.3~7 V VO −0.3~26 V Output current IOUT 90 mA/bit Logic output voltage VOUT −0.3~ VDD + 0.3 V VIN −0.3~VDD + 0.3 V A Constant-current output voltage Logic input voltage Total VSS2 current Power dissipation Saturation heat resistance of package (Note 5) IVSS2 1.44 (Note 6) Pd 1.19 (Note 4) 5.0 (Note 6) θ (j-a) 102 When device mounted on PCB of any size θ (j-c) 25 When device mounted on PCB When device mounted on PCB of any size When device mounted on PCB W °C/W Operating temperature Topr −40~85 °C Storage temperature Tstg −55~150 °C Note 4: If the operating temperature exceeds 25°C, derate the power dissipation rating by 0.95 mW/°C. Note 5: All four VSS2 pins must be connected. If not, device characteristics cannot be guaranteed. Note 6: When device mounted on PCB with dimensions 100 mm × 100 mm × 1.6 mm Recommended Operating Conditions (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C unless otherwise specified) Characteristics Symbol Conditions & Pins Min Typ. Max Unit Supply voltage VDD ⎯ 4.5 5.0 5.5 V High-level input voltage VIH PI DATA, PI CLK, PI SEL, PI LATCH, SI DATA, SI CLK, SI SEL, SI LATCH, PWM CLK 0.7 VDD ⎯ VDD V Low-level input voltage VIL BLANK, LED TEST, TSENA, DOE, DCEN, BCEN VSS ⎯ 0.3 VDD V High-level output current IOH PO DATA 00~PO DATA 07, SO DATA ⎯ ⎯ −1 mA Low-level output current IOL VDD = 4.5 V, ALARM1, ALARM2 ⎯ ⎯ 1 mA Constant-current output IOUT OUT 00~OUT 15 5 ⎯ 80 mA/bit VOUT OUT 00~OUT 15 OFF ⎯ ⎯ 26 V VOH ALARM1, ALARM2 OFF ⎯ ⎯ 5 V −40 ⎯ 85 °C Output voltage Operating temperature ⎯ Topr 8 2005-04-20 TB62718AFG Recommended Operating Conditions (continue) (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C unless otherwise specified) Characteristics Symbol Min Typ. Max Ratio of High-level: Low level = 50%, PWM CLK ⎯ ⎯ 10 fPI1 PI CLK, ⎯ ⎯ 15 fPI2 PI CLK, connected in cascade ⎯ ⎯ 10 fSI1 SI CLK ⎯ ⎯ 15 fPWM Clock frequency SI CLK, connected in cascade ⎯ ⎯ 10 PWM CLK 30 ⎯ ⎯ PI CLK, SI CLK 30 ⎯ ⎯ PI LATCH, SI LATCH 50 ⎯ ⎯ twrstH/twrstL RESET 50 ⎯ ⎯ twblkH/twblkL BLANK 400 ⎯ ⎯ twledH/twledL LED TEST 400 ⎯ ⎯ PI DATA → PI CLK 10 ⎯ ⎯ PI LATCH → PI CLK 10 ⎯ ⎯ SI DATA → SI CLK 10 ⎯ ⎯ SI LATCH → SI CLK 10 ⎯ ⎯ fSI2 twH/twL Minimum pulse width Set-up time Hold time Condition & Terminals twltH/twltL tsetup thold SI LATCH → SI CEL 50 ⎯ ⎯ PI DATA → PI CLK 5 ⎯ ⎯ PI LATCH → PI CLK 5 ⎯ ⎯ SI DATA → SI CLK 5 ⎯ ⎯ SI LATCH → SI CLK 5 ⎯ ⎯ SI LATCH → SI CEL 50 ⎯ ⎯ 9 Unit MHz ns ns ns 2005-04-20 TB62718AFG Electrical Characteristics 1 (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, typ: VDD = 5.0 V, Topr = 25°C) Parameter Symbol Test conditions & Terminals Min Typ. Max Unit High-level output voltage VOH IOH = −1.0 mA, PO DATA 00~PO DATA 07, SO DATA VDD −0.4 ⎯ ⎯ V Low-level output voltage VOL IOL = 1.0 mA, PO DATA 00~PO DATA 07, SO DATA ⎯ ⎯ 0.4 IOL = 1.0 mA, ALARM1, ALARM2 ⎯ ⎯ 0.3 VOUT = VDD or VSS, PO DATA 00~PO DATA 07 ⎯ ±0.5 ±5 µA All pins without pull-up/pull-down resistors ⎯ ⎯ ±1 µA IDD1 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = 20 MHz PWMCLK = L, BLANK = H Settings: *1 ⎯ 20 30 IDD2 PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *5a ⎯ 75 105 IDD3 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Settings: *5a ⎯ 80 115 IDD4 PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *6a ⎯ 90 140 IDD5 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Settings: *6a ⎯ 95 150 Tri-state output leakage current Input current Supply current IOZ II V mA Electrical Characteristic Settings (OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 kΩ unless otherwise specified) No. Surface Brightness Adjustment (DAC3) DAC Settings Constant Output Current (typ.) ∗1 Outputs all OFF, VOUT = 26 V, DAC1, 2, 4 = MSB, BLANK = H IOUT = 0 mA ∗2 DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L IOUT = 7.10 mA ∗3a DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 10.0 mA ∗4a DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5a DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L ∗6a DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L IOUT = 60.2 mA ∗7 DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L IOUT = 71.0 mA ∗3b DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 5.0 mA ∗4b DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5b DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L ∗6b DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L DAC3 = 31 IOUT = 19.9 mA IOUT = 40.1 mA DAC3 = 00 IOUT = 10.0 mA IOUT = 20.0 mA IOUT = 30.1 mA 10 2005-04-20 TB62718AFG Electrical Characteristics 2 (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, typ: VDD = 5.0 V, Topr = 25°C) Parameter Symbol Constant-current output Constant-current output Depends on temperature Leakage current for constant-current output Constant current accuracy between bits Dot adjustment deviation between bits (when DAC3 data were changed from MSB to LSB.) Test Conditions Min Typ. Max IOUT1 Settings *7 60.4 71.0 81.6 IOUT2 Settings *6a 51.2 60.2 69.2 IOUT3 Settings *5a 34.1 40.1 46.1 IOUT4 Settings *4a 16.5 19.9 23.2 IOUT5 Settings *3a 7.8 10.0 12.2 IOUT6 Settings *2 4.54 7.1 9.65 %TOPR1 Settings *6a, VOUT = 1.0 V, Topr is varied in the range −40°C~85°C. ⎯ ±50 ±80 %TOPR2 Settings *4a, VOUT = 1.0 V, Topr is varied in the range −40°C~85°C. ⎯ ±25 ±50 Settings *1, VOUT = 26 V ⎯ 0.05 0.1 ∆IOUT1 Settings *6a, VOUT = 0.7 V ⎯ ±2.5 ±6 ∆IOUT2 Settings *5a, VOUT = 0.7 V ⎯ ±3.5 ±6 ∆IOUT3 Settings *4a, VOUT = 0.7 V ⎯ ±5.5 ±7 IOLK Unit V µA/°C ∆IOUT4 Settings *3a, VOUT = 0.7 V ⎯ ±7 ±12 %IOUT1 Settings is changed from *6a to *6b. ⎯ ±1 ±3 %IOUT2 Settings is changed from *5a to *5b. ⎯ ±1.5 ±3 %IOUT3 Settings is changed from *4a to *4b. ⎯ ±3.5 ±5 %IOUT4 Settings is changed from *3a to *3b. ⎯ ±6 ±12 Settings *6a, VOUT is varied in the range 0.7 V~3 V. ⎯ ±5 ±8 Settings *4a, VOUT is varied in the range 0.7 V~3 V. ⎯ ±3 ±6 µA % % Constant-current output depends on output voltage %VOUT Constant-current output depends on supply voltage %VDD Settings *6a, VDD is varied in the range 4.5 V~5.5 V. ⎯ ±1 ±2 Tsd1 ⎯ 120 140 160 Tsd2 ⎯ 140 160 180 ⎯ 0.04 VDD ⎯ V 150 300 600 kΩ TSD detection temperature Output-open detection voltage Pull-up/down resistor VARL ALARM2 ⎯ Rup/Rdw % % °C Electrical Characteristic Settings (OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 kΩ unless otherwise specified) No. All Dot Adjustment (DAC3) DAC Settings Constant Output Current (typ.) ∗1 OUT00~15 OFF, VOUT = 26 V, DAC1~4 = MSB, BLANK = H IOUT = 0 mA IOUT = 7.10 mA ∗2 DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L ∗3a DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L ∗4a DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5a DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L IOUT = 40.1 mA ∗6a DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L IOUT = 60.2 mA IOUT = 10.0 mA DAC3 = 31 IOUT = 19.9 mA ∗7 DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L IOUT = 71.0 mA ∗3b DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 5.0 mA ∗4b DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5b DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L ∗6b DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L DAC3 = 00 IOUT = 10.0 mA IOUT = 20.0 mA IOUT = 30.1 mA 11 2005-04-20 TB62718AFG Switching Characteristics (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, CL = 50 pF unless otherwise specified, typ: VDD = 5.0 V, Topr = 25°C, CL = 50 pF) Parameter Symbol Test Conditions Min Typ. Max Unit Tri-state output enable propagation delay tpZH/ZL DOE → PO DATA0~ PO DATA 7 8 16 30 ns Tri-state output disable propagation delay tpHZ/LZ DOE → PO DATA0~ PO DATA 7 8 16 30 ns OUT00~ OUT 15 10 17 30 µs ALARM1, ALARM2 0.2 0.4 0.8 ns Rise time tr Fall time tf OUT00~ OUT 15 20 40 70 ALARM1, ALARM2 2 4 8 tpHL BLANK → OUT00~ OUT 15 30 60 120 tpLH PWM CLK → OUT00~ OUT 15 70 120 200 tpHL PWM CLK → OUT00~ OUT 15 40 70 140 60 110 190 30 60 130 RESET → OUT00~ OUT 15 30 60 130 PI CLK → PO DATA0~ PO DATA 7 20 30 70 PI SEL → PO DATA0~ PO DATA 7 20 30 70 SI SEL → SO DATA 10 18 40 SI SEL → SO DATA 10 20 40 tpLH Propagation delay tpHL tpHL tpd LED TEST → OUT00~ OUT 15 12 ns ns 2005-04-20 TB62718AFG Explanation of Operation and Truth Tables Serial data transfer: standard current adjustment using DAC1 and DAC2 (data register SI REG [7:0]) Process SI DATA SI CLK SI LATCH SI SEL L 1 H or L 2 SO DATA H H or L Selects standard current adjustment (8 bits, 2 bits and 6 bits) for input data when SI SEL is high. Data is transferred to SI REG [1] on 8th positive edge of SI CLK input. H No change Holds the data transferred to SI REG [1] on positive edge of SI LATCH. Set is reflected on standard current adjustment from the moment when it is held. (×8) L Operation and Function (×1) Serial data transfer timing (standard current adjustment, SI SEL = H, single device) RESET SI SEL SI DATA Data held on positive edge of SI LATCH after the data transfer by single device (after 8 clock cycles) SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L SODATA is synchronized with 8th clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. Serial data transfer timing (standard current adjustment, SI SEL = H, two devices connected in cascade) RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L Indicates undefined logic state after reset and before input. Data held on positive edge of SI LATCH after the data transfer by two devices (after 16 clock cycles) SODATA is synchronized with 8th clock cycle after reset, and the first data is output. 13 2005-04-20 TB62718AFG Serial data transfer: dot adjustment DAC4. (data register SI REG2 [127:0]) Process SI DATA SI CLK 1 H or L 2 SI LATCH SI SEL SO DATA Operation and Function L L H or L Selects dot adjustment (128 bits) for input data. Data is transferred to SI REG2 on 128th positive edge of SI CLK. L No change Holds the data transferred to SI REG2 on positive edge of SILATCH. Set is reflected on dot adjustment from the moment when it is held. (×128) L (×1) Serial data transfer timing (dot adjustment, SI SEL = L, single device) RESET SI SEL There pairs of bits are Don’t care. SI DATA SI CLK Dot adjustment data for OUT 15 (1st device). Dot adjustment data for OUT 00 (1st device). Data held on positive edge of SI LATCH after data transfer by single device (after 128 clock cycles) SI LATCH SO DATA (1st device) Data reset by RESET = L SODATA is synchronized with 128th clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. Serial data transfer timing (dot adjustment, SI SEL = L, two devices connected in cascade) RESET SI SEL There pairs of bits are Don’t care. SI DATA SI CLK Dot adjustment data for OUT 15 (1st device). Dot adjustment data for OUT 00 (1st device). Dot adjustment data for OUT 15 (2nd device). Dot adjustment data for OUT 00 (2nd device). SI LATCH SO DATA (1st device) Data reset by RESET = L Indicates undefined logic state after reset and before input. SODATA is synchronized with 128th clock cycle after reset, and the first data is output. Data held on positive edge of SI LATCH after data transfer by two devices (after 256 clock cycles) 14 2005-04-20 TB62718AFG DAC1: Standard current adjustment settings for DAC1 (SI REG1 [7:6]) RESET SI SEL SI REG (7:6) SI REG (5:0) Current Rate H H HH XXXXXX 100% (1.0) H H HL XXXXXX 75% (0.75) H H LH XXXXXX 50% (0.5) H H LL XXXXXX 25% (0.25) X LL LLLLLL 25% (0.25) Operation and Function Notes 100% of base current setting as determined by REXT (Ω) When SI SEL = H, 2 bits on 75% of base current setting as determined by REXT MSB sides are (Ω) corresponding to set of standard 50% of base current setting as determined by REXT current (Ω) adjustment 25% of base current setting as determined by REXT DAC1. The output (Ω) current can be set to one of 4 Initial state after input of reset signal: 25% of base levels. current setting as determined by REXT (Ω) (as described above) DAC2: Standard current adjustment settings for DAC2 (SI REG1 [5:0]) RESET SI SEL SI REG (7:6) SI REG (5:0) Current Rate H H XX XXXXXX 100% (1.0) HHHHHL ↑ (0.9905) ↑ H H XX ↓ LLLLLH H Operation and Function Notes 100% of base current value as set using DAC1 base current adjustment Any one or 64 levels in the range 40%~100% of the current can be set. (1 LSB = 0.95%) 1LSB = 6-bit DAC performance ±0.95% 1LSB variation: ±0.95% (±0.0095) Non linearity error: ±1/2LSB Differential non linearity error: ±3/4LSB ↓ (0.4095) H XX LLLLLL 40% (0.4) 40% of base current value as set using DAC1 base current adjustment X LL LLLLLL 40% (0.4) Initial state after input of reset signal: 40% of base current value set as described above When SI SEL = H, 6 bits on MSB sides are corresponding to set of standard current adjustment DAC2. The output current can be set to one of 64 levels. DAC4: Set details of dot adjustment DAC4 (SI REG2 [127:0]) RESET SI SEL DCEN About 8 bits Unit of SI REG2 [127:0] Current Rate Operation and Function Notes H L H XXHHHHHH 100% (1.0) Output current is 100% of base current value as set using DAC1 and DAC2 base current adjustment and DAC3 surface brightness adjustment When SI SEL = L 8 bits out of 128 bits are corresponding to set of each output, and the 6 bits on MSB sides of 8 bits are data on dot adjustment. XXHHHHHL ↑ H L H ↓ XXLLLLLH H H (0.9874) ↑ 1LSB = ±1.269% (±0.0126) ↓ (20.0126) L H XXLLLLLL 20% (0.2) X H XXLLLLLL 20% (0.2) X L XXHHHHHH 100% (1.0) Any one of 64 levels in the range 20%~100% of the current can be set. (1LSB ∼ − 1.27%) 6-bit DAC performance 1LSB variation: ±1.269% Non linearity error: ±1/2LSB Differential non linearity error: ±1/2LSB The output current can be set to one of 64 levels. SI REG2 [7:0] → adjustment data for OUT 00. SI REG2 [15:8] 20% of base current value as set using → adjustment data for DAC3 surface brightness adjustment OUT 01. Initial state after input of reset signal: 20% SI REG2 [127:120] → adjustment data for of base current value set as described OUT 15. above Output current is 100% of base current value set as described above. 15 Data input is still enabled if DCEN = L. If DCEN = H, adjustment is performed at the same time. 2005-04-20 TB62718AFG Polarity of serial input data for standard current adjustment (SI REG1 [7:0]) and dot adjustment (SI REG2 [127:0]) Serial data transfer timing (SI SEL = H, input of standard current adjustment data for DAC1 and DAC2) Standard current adjustment data (6 bits) Standard current adjustment data (2 bits) SO DATA SI DATA D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F SI REG1 (7) SI REG1 (0) MSB LSB SI LATCH D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT Serial data transfer timing (SI SEL = L, input of dot adjustment data for DAC4) Dot adjustment data (6 bits) SI DATA SI REG2 (0) LSB Not used × × SI REG2 (7) Dot adjustment data (6 bits) Not used SO DATA × × SI REG2 (120) SI REG2 (127) MSB SI LATCH DAC4 (6-bit DAC) DAC4 (6-bit DAC) OUT 00 OUT 15 16 2005-04-20 TB62718AFG Parallel data transfer: All dot adjustment DAC3. (data register PI REG1 [7:0]) Process PI DATA [7:0] PI CLK PI LATCH PI SEL PO DATA [7:0] Operation and Function L H H or L Selects total dot adjustment (8-bit, 3-bit and 5-bit) for input data. Data is transferred to PI REG1 on 128th positive edge of PI CLK. H No change Holds the data transferred to PI REG1. Set is reflected on all dot adjustment from the moment when it is held. 1 H or L 2 (×1) L (×1) Parallel data transfer timing (all dot adjustment, PI SEL = H, single device) RESET PI SEL PI DATA [7:0] 111_11111 PI CLK Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) PI LATCH PO DATA [7:0] 000_00000 111_11111 Indicates undefined logic state after reset and before input. PO DATA is synchronized with 1st clock cycle after reset, and the first data is output. Parallel data transfer timing (all dot adjustment, PI SEL = H, two devices connected in cascade) RESET PI SEL PI DATA [7:0] 111_11111 110_11110 PI CLK PI LATCH PO DATA [7:0] (1st device) 000_00000 111_11111 Indicates undefined logic state after reset and before input. 101_11101 Data held on positive edge of PI LATCH after the data 110_11110 transfer by two devices (2 clock cycles) PO DATA is synchronized with 2nd clock cycle after reset, and the second data is output. PO DATA is synchronized with 1st clock cycle after reset, and the first data is output. 17 2005-04-20 TB62718AFG Parallel data transfer PMW display data (data register PI REG2 [127:0]) Process PI DATA PI CLK PI LATCH PI SEL PO DATA Operation and Function L L H or L Selects for input data of PWM display data (8 bit × 16). Data is transferred to PI REG2 on 16th positive edge of PI CLK. L No change Holds the data transferred to PI REG2. Set is reflected on PWM 256 grayscales from the next BLANK = L when it is held. 1 (×16) H or L 2 L (×1) Parallel data transfer timing (PWM data PI SEL = L, single device) RESET PWM data for OUT 15 PWM data for OUT 00 PI SEL PI DATA [7:0] 01H 02H 0EH 0FH PI CLK Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) PI LATCH PO DATA [7:0] 00H 00H Indicates undefined logic state after reset and before input. 01H PO DATA is synchronized with 16th clock cycle after reset, and is output. Parallel data transfer timing (PWM data PI SEL = L, two devices connected in cascade) RESET PI SEL PI DATA [7:0] 00H 01H 02H 0EH 0FH 10H 01H 02H 0EH 0FH 10H PI CLK PI LATCH PO DATA [7:0] (1st device) PWM data for OUT 15 (1st device) 00H PWM data for OUT 00 (1st device) 00H Indicates undefined logic state after reset and before input. 01H 02H 0FH 10H 01H PO DATA is synchronized with 16th clock cycle after reset, and the first data is output. Data held on positive edge of PI LATCH after data transfer by two devices (32 clock cycles) 18 2005-04-20 TB62718AFG Details all dot adjustment setting using PWMCLK division (PI REG1 [7:5]) RESET PI SEL BCEN PI REG1 [7:5] PWMCLK Divisor Operation and Function H H H LLL PWM CLK = 8/8 PWMCLK (Hz) The period of PWMCLK is set to equal the change in the PWM pulse width data. 1LSB. 7/8 PWMCLK to 2/8 PWMCLK Variable does the frequency of PWMCLK to 1/8 of the minimal. It is set in 8 levels. 6-bit DAC performance Maximum input: PWMCLK = 20 MHz LLH ↑ H H H ↓ HHL H H H H HHH PWMCLK = 1/8 PWMCLK (Hz) The period of PWMCLK is set to one-eighth the change in the PWM pulse width data. 1 LSB. X H LLL PWMCLK = 8/8 PWMCLK (Hz) The period of PWMCLK is set to equal the change in the PWM pulse width data. 1 LSB. H L XXX Unchanged BCEN signal does not affect PWMCLK frequency dividing. Notes When PI SEL = H is selected, 3 bits on MSB sides are corresponding to set of standard current adjustment by PWM frequency dividing. PI REG [7:5] varies the pulse width of PWM data corresponding to 1 LSB for eight levels and adjusts brightness. This setting values affects pulse widths on all outputs. Data input is still enabled if BCEN = L. Output current level reflects input settings. DAC3: Details of all dot adjustment setting for DAC3 (PI REG2 [4:0]) RESET PI SEL PI REG1 [4:0] BCEN Current Rate Operation and Function H H HHHHH H 100% (1.0) 100% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment H H HHHHL ↑ (0.9839) ↑ H ↓ LLLLH H H Any one of 32 levels in the range 50%~100% of the current can be set. (1 LSB = 1.61%) 1LSB = 5-bit DAC performance ±1.61% 1LSB variation: ±1.61% (±0.0161) Non linearity error: ±1/2LSB Differential non linearity error: ↓ ±1/2LSB (0.5161) (No guarantee for monotonicity) Notes H LLLLL H 50% (0.5) 50% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment X HHHHH H 100% (1.0) Initial state after input of reset signal: 100% of base current value set as described above X HHHHH L 100% (1.0) Initial state after input of DCEN signal: 100% of base current value set as described above 19 When PI SEL = H is selected, 5 bits on LSB side are corresponding to set of surface brightness adjustment. The output current can be set to one of 32 levels. Data input is still enabled if BCEN = L. If BCEN = H, adjustment is performed at the same time. 2005-04-20 TB62718AFG Detailed PWM 256 grayscales setting (PI REG2 [127:0], 16 × 8 bits) RESET PI SEL 1 word (8 bits) of PI REG2 Output Pulse Rate H L HHHHHHHH 255/255 100% HHHHHHHL ↑ H ⎯ L ↓ LLLLLLLH H L LLLLLLLL 0/255 0% X LLLLLLLL 0/255 0% Operation and Function Output pulse width is at its maximum value when input data is FF. Notes When PI SEL = L, The PWM grayscale controls the output pulse width. 16 × 8-bit words are transferred in parallel. The input data can be used to 1 word is the PWM data of each output control the PWM pulse width pulse width is set in 256 step. and hence generate 256 PI REG2 [7:0] grayscales. → PWM data for OUT 00. PI REG2 [15:8] → PWM data for OUT 01. Outputs are OFF when the PI REG2 [127:120] input data is 00. → PWM data for OUT 15. Early condition after the reset signal input is set in 0/256 (output off). Minimum output pulse width is 1/PWMCLK. Polarity of serial input data for all dot adjustment (PI REG [7:0]) and PWM 256 grayscales (PI REG2 [127:0]) Parallel data transfer timing (PI SEL = H, selects data input for all dot adjustment for DAC3.) PI REG1 [7] MSB PI DATA [7] All dot adjustment by division by PWMCLK PO DATA [7] All dot adjustment by DAC3 PI DATA [0] PO DATA [0] LSB PI REG1 [0] PI LATCH (PI SEL = L, selects data input for PWM 256 grayscales.) PI REG2 [7] MSB PO REG2 [127] MSB PO DATA [7] PI DATA [7] PWM pulse data PWM pulse data PO DATA [0] PI DATA [0] LSB PI REG2 [120] LSB PI REG2 [0] PI LATCH PWM pulse generator circuit PWM pulse generator circuit OUT 00 OUT 15 20 2005-04-20 TB62718AFG Reference table: output current setting vales (1) DAC1 (2-bit) DAC2 (6-bit) DAC3 (5-bit) DAC4 (6-bit) No. Input Data Current Rate1 No. Input Data Current Rate2 No. Input Data Current Rate3 No. Input Data Current Rate4 3 11 1.00 63 111111 1.000 31 **11111 **1.000 63 111111 63 2 10 0.75 62 111110 0.990 30 11110 0.984 62 111110 62 1 01 0.50 61 111101 0.981 29 11101 0.968 61 111101 61 0 **00 **0.25 60 111100 0.971 28 11100 0.952 60 111100 60 ⎯ ⎯ ⎯ 59 111011 0.962 27 11011 0.936 59 111011 59 ⎯ ⎯ ⎯ 58 111010 0.952 26 11010 0.919 58 111010 58 ⎯ ⎯ ⎯ 57 111001 0.943 25 11001 0.903 57 111001 57 ⎯ ⎯ ⎯ 56 111000 0.933 24 11000 0.887 56 111000 56 ⎯ ⎯ ⎯ 55 110111 0.924 23 10111 0.871 55 110111 55 ⎯ ⎯ ⎯ 54 110110 0.914 22 10110 0.855 54 110110 54 ⎯ ⎯ ⎯ 53 110101 0.905 21 10101 0.839 53 110101 53 ⎯ ⎯ ⎯ 52 110100 0.895 20 10100 0.823 52 110100 52 ⎯ ⎯ ⎯ 51 110011 0.886 19 10011 0.807 51 110011 51 ⎯ ⎯ ⎯ 50 110010 0.876 18 10010 0.790 50 110010 50 ⎯ ⎯ ⎯ 49 110001 0.867 17 10001 0.774 49 110001 49 ⎯ ⎯ ⎯ 48 110000 0.857 16 10000 0.758 48 110000 48 ⎯ ⎯ ⎯ 47 101111 0.848 15 01111 0.742 47 101111 47 ⎯ ⎯ ⎯ 46 101110 0.838 14 01110 0.726 46 101110 46 ⎯ ⎯ ⎯ 45 101101 0.829 13 01101 0.710 45 101101 45 ⎯ ⎯ ⎯ 44 101100 0.819 12 01100 0.694 44 101100 44 ⎯ ⎯ ⎯ 43 101011 0.820 11 01011 0.677 43 101011 43 ⎯ ⎯ ⎯ 42 101010 0.800 10 01010 0.661 42 101010 42 ⎯ ⎯ ⎯ 41 101001 0.791 9 01001 0.645 41 101001 41 ⎯ ⎯ ⎯ 40 101000 0.781 8 01000 0.629 40 101000 40 ⎯ ⎯ ⎯ 39 100111 0.771 7 00111 0.613 39 100111 39 ⎯ ⎯ ⎯ 38 100110 0.762 6 00110 0.597 38 100110 38 ⎯ ⎯ ⎯ 37 100101 0.752 5 00101 0.581 37 100101 37 ⎯ ⎯ ⎯ 36 100100 0.743 4 00100 0.565 36 100100 36 ⎯ ⎯ ⎯ 35 100011 0.733 3 00011 0.549 35 100011 35 ⎯ ⎯ ⎯ 34 100010 0.724 2 00010 0.532 34 100010 34 ⎯ ⎯ ⎯ 33 100001 0.714 1 00001 0.516 33 100001 33 ⎯ ⎯ ⎯ 32 100000 0.705 0 00000 0.500 32 100000 32 ⎯ ⎯ ⎯ 31 011111 0.695 ⎯ ⎯ ⎯ 31 011111 31 ⎯ ⎯ ⎯ 30 011110 0.686 ⎯ ⎯ ⎯ 30 011110 30 ⎯ ⎯ ⎯ 29 011101 0.676 ⎯ ⎯ ⎯ 29 011101 29 ⎯ ⎯ ⎯ 28 011100 0.667 ⎯ ⎯ ⎯ 28 011100 28 ⎯ ⎯ ⎯ 27 011011 0.657 ⎯ ⎯ ⎯ 27 011011 27 ⎯ ⎯ ⎯ 26 011010 0.648 ⎯ ⎯ ⎯ 26 011010 26 ⎯ ⎯ ⎯ 25 011001 0.638 ⎯ ⎯ ⎯ 25 011001 25 ⎯ ⎯ ⎯ 24 011000 0.629 ⎯ ⎯ ⎯ 24 011000 24 ⎯ ⎯ ⎯ 23 010111 0.619 ⎯ ⎯ ⎯ 23 010111 23 ⎯ ⎯ ⎯ 22 010110 0.610 ⎯ ⎯ ⎯ 22 010110 22 ⎯ ⎯ ⎯ 21 010101 0.600 ⎯ ⎯ ⎯ 21 010101 21 ⎯ ⎯ ⎯ 20 010100 0.591 ⎯ ⎯ ⎯ 20 010100 20 ⎯ ⎯ ⎯ 19 010011 0.581 ⎯ ⎯ ⎯ 19 010011 19 ⎯ ⎯ ⎯ 18 010010 0.571 ⎯ ⎯ ⎯ 18 010010 18 ⎯ ⎯ ⎯ 17 010001 0.562 ⎯ ⎯ ⎯ 17 010001 17 ⎯ ⎯ ⎯ 16 010000 0.552 ⎯ ⎯ ⎯ 16 010000 16 ⎯ ⎯ ⎯ 15 001111 0.543 ⎯ ⎯ ⎯ 15 001111 15 ⎯ ⎯ ⎯ 14 001110 0.533 ⎯ ⎯ ⎯ 14 001110 14 ⎯ ⎯ ⎯ 13 001101 0.524 ⎯ ⎯ ⎯ 13 001101 13 ⎯ ⎯ ⎯ 12 001100 0.514 ⎯ ⎯ ⎯ 12 001100 12 ⎯ ⎯ ⎯ 11 001011 0.505 ⎯ ⎯ ⎯ 11 001011 11 ⎯ ⎯ ⎯ 10 001010 0.495 ⎯ ⎯ ⎯ 10 001010 10 ⎯ ⎯ ⎯ 9 001001 0.486 ⎯ ⎯ ⎯ 9 001001 9 ⎯ ⎯ ⎯ 8 001000 0.476 ⎯ ⎯ ⎯ 8 001000 8 ⎯ ⎯ ⎯ 7 000111 0.467 ⎯ ⎯ ⎯ 7 000111 7 ⎯ ⎯ ⎯ 6 000110 0.457 ⎯ ⎯ ⎯ 6 000110 6 ⎯ ⎯ ⎯ 5 000101 0.448 ⎯ ⎯ ⎯ 5 000101 5 ⎯ ⎯ ⎯ 4 000100 0.438 ⎯ ⎯ ⎯ 4 000100 4 ⎯ ⎯ ⎯ 3 000011 0.429 ⎯ ⎯ ⎯ 3 000011 3 ⎯ ⎯ ⎯ 2 000010 0.419 ⎯ ⎯ ⎯ 2 000010 2 ⎯ ⎯ ⎯ 1 000001 0.410 ⎯ ⎯ ⎯ 1 000001 1 ⎯ ⎯ ⎯ 0 **000000 **0.4 ⎯ ⎯ ⎯ 0 **000000 0 Note 7: **: Indicates post-reset initialization value ( RESET = L). Note 8: The formula for calculating resistance settings is as follows: This value is theory value. Actual current value contains error and so on in this value. REXT [kΩ] = (1.9 × current rate 1 × current rate 2 × current rate 3 / output current [mA]) × (1 + (7 × current rate 4 / 105)) × 19.4 21 2005-04-20 TB62718AFG Reference table: output current setting value (2) Reference value for standard current adjustment under conditions: REXT = 2.7 kΩ (fixed), all dot adjustment = MSB and dot adjustment = MSB Unit: mA DAC1 DAC2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 7.1 7.3 7.4 7.6 7.8 7.9 8.1 8.3 8.5 8.6 8.8 9.0 9.1 9.3 9.5 9.6 1 14.2 14.5 14.9 15.2 15.6 15.9 16.2 16.6 16.9 17.2 17.6 17.9 18.3 18.6 18.9 19.3 2 21.3 21.8 22.3 22.8 23.3 23.8 24.3 24.9 25.4 25.9 26.4 26.9 27.4 27.9 28.4 28.9 3 28.4 29.1 29.6 30.4 31.1 31.8 32.5 33.1 33.8 34.5 35.2 35.8 36.5 37.2 37.9 38.6 DAC1 DAC2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 9.8 10.0 10.1 10.3 10.5 10.7 10.8 11.0 11.2 11.3 11.5 11.7 11.8 12.0 12.2 12.3 1 19.6 19.9 20.3 20.6 21.0 21.3 21.6 22.0 22.3 22.7 23.0 23.3 23.7 24.0 24.3 24.7 2 29.4 29.9 30.4 30.9 31.4 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 3 39.2 39.9 40.6 41.2 41.9 42.6 43.3 44.0 44.6 45.3 46.0 46.7 47.3 48.0 48.7 49.4 DAC1 DAC2 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0 12.5 12.7 12.9 13.0 13.2 13.4 13.5 13.7 13.9 14.0 14.2 14.4 14.5 14.7 14.9 15.0 1 25.0 25.4 25.7 26.0 26.4 26.7 27.0 27.4 27.7 28.1 28.4 28.7 29.1 29.4 29.8 30.1 2 37.5 38.0 38.6 39.0 39.6 40.1 40.6 41.1 41.6 42.1 42.6 43.1 43.6 44.1 44.6 45.1 3 50.0 50.7 51.4 52.1 52.7 53.4 54.1 54.8 55.4 56.1 56.8 57.5 58.1 58.8 59.5 60.2 DAC1 DAC2 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 15.2 15.4 15.6 15.7 15.9 16.1 16.2 16.4 16.6 16.7 16.9 17.1 17.2 17.4 17.6 17.8 1 30.4 30.8 31.1 31.4 31.8 32.1 32.5 32.8 33.1 33.5 33.8 34.1 34.5 34.8 35.2 35.5 2 45.6 46.1 46.7 47.2 47.7 48.2 48.7 49.2 49.7 50.2 50.7 51.2 51.7 52.2 52.7 53.2 3 60.9 61.5 62.2 62.9 63.6 64.2 64.9 65.6 66.3 66.9 67.6 68.3 69.0 69.6 70.3 71.0 22 2005-04-20 TB62718AFG Temperature detection function (can be monitored via the ALARM1 pin.) Perform two-stage temperature detection as described in the table below (TSD1/TSD2). Junction Temperature [°C] ALARM1 OUT 00~OUT 15 Function −40~120 OFF Normal operation ⎯ 120~ ON Normal operation When the chip temperature reaches the specified range the ALARM1 signal goes Low (TSD1), Other functions are not affected. When the chip temperature reaches the specified range the ALARM1 signal goes Low and all output pins are turned OFF (TSD2). 140~ ON OFF Outputs are re-enabled on the positive edge of TSENA or when the RESET signal goes Low. Neither of these causes the internal data to be reset. If RESET pin = L, all internal data is reset. Output-open detection function (can be monitored via the ALARM2 pin.) Reform output-open detection as described in the table below. Output Voltage [V] ALARM2 > = VDD × 0.04 OFF < = VDD × 0.04 ON Function ⎯ The output-open condition is detected when the ARARM2 pin signal is ON and the specified voltage level is detected. (it is also detected when the output voltage falls to near GND for some reason) Pulse cancellation circuit (when monitored using output-open detection pin ARARM2.) PWMCLK ALARM2 Input signal Operating No input Always OFF Function The built-in pulse cancellation circuit is designed to prevent malfunction. However, if there is no input on PWMCLK, ALARM2 output will not be turned ON. 23 2005-04-20 TB62718AFG Block Diagram of Protection Circuit RESET Output-OFF condition is released and internal data is reset. Output ON LED TEST Release of output OFF on positive edge TSENA Constantcurrent output Output OFF TSD2 ALARM1 TSD1 ALARM2 Pulse cancel Output-open detection 16 Continue one, open condition is detected. OUT00~OUT15 Protection circuit function Operating chart (terminal for TESNA, ALARM1 and outputs OUT 00~OUT 15) Junction Temperature (unit: °C) TSD1 TSD2 Tj < 120 < 140 < = 120°C = Tj = Tj < < = 160°C = 180°C ALARM1 OUT 00 ~ OUT 15 ON Function TSENA RESET X L ○ ⎯ ⎯ OFF X H ○ ⎯ ⎯ OFF ON Outputs operate normally. X L ⎯ ○ ⎯ ON ON Device reset X H ⎯ ○ ⎯ ON Normal operation ALARM1 goes Low, indicating a rise in temperature. Outputs operate normally. X L ⎯ ⎯ ○ ON OFF Even after a reset, if the junction temperature is high, outputs are turned OFF. X H ⎯ ⎯ ○ ON OFF ALARM1 goes Low, indicating a rise in temperature. Outputs operate normally. Device reset Note 9: The internal operation of the TSD circuit is independent of the TSENA and RESET pin voltage levels. 24 2005-04-20 TB62718AFG Serial Data Input Timing Chart BLANK Output ON Output OFF RESET SI DATA SI CLK Data of DAC3 for OUT 15 Data of DAC3 for OUT 00 ×8 ×8 Data of DAC1 to 2 ×8 SI LATCH SI SEL Selects input of each dot adjustment data. Selects input of standard current adjustment data. The data read with 1st time SO DATA The data read with 1st time SO DATA outputs standard current SO DATA outputs each dot adjustment data. Note 10: Serial data input has no effect on the ON/OFF state of the outputs. When the SI LATCH signal holds the serial data, the output current values and output pulse width are affected. Parallel Data Input Timing Chart Output OFF & data hold BLANK Output ON & data transfer Output ON & data transfer RESET DOE PWM data for OUT 15 PWM data for OUT 00 PI DATA 00~ PI DATA 07 for total dot adjustment PI CLK 1 Time 16 Times PI LATCH Holds PWM data, output-ON data and total dot adjustment data. Selects input of total dot adjustment PI SEL PO DATA 00~ PO DATA 07 Selects input of PWM data and output-ON data. High-Impedance Selects input of PWM data and output-ON data. High-Impedance The data read with 1st time The data read with 1st time PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output all bit adjustment data. OUT 00~ OUT 15 Output ON (output-OFF if PWM data = 0) OFF Starts output of PWM data after synchronizing with rising edge of BLANK. Note 11: The BLANK signal has not effect on parallel data input. The PWM pulse can be controlled using the BLANK signal. It is recommended that, on completion of data transfer, BLANK be set to High and outputs be turned OFF. 25 2005-04-20 TB62718AFG PWM Operating Timing Chart and All Bit Adjustment Using Division by PWMCLK Output OFF, data hold Output OFF, data change & hold Output can be turned ON. BLANK Output can be turned ON. RESET OUT 00~ OUT 15 ON OFF ON tBLANK (8) tBLANK (7) tBLANK (6) PWMCLK division tBLANK (5) tBLANK (4) tBLANK (6) = (1/ (6/8PWMCLK) ) × 256 tBLANK (5) = (1/ (5/8PWMCLK) ) × 256 tBLANK (4) = (1/ (4/8PWMCLK) ) × 256 tBLANK (3) = (1/ (3/8PWMCLK) ) × 256 tBLANK (2) tBLANK (2) = (1/ (2/8PWMCLK) ) × 256 tBLANK (1) OUT 00~OUT 15 PWM data = 01 H PWMCLK8 OUT 00~OUT 15 PWM data = 80 H PWMCLK8 OUT 00~OUT 15 PWM data = FE H PWMCLK8 Minimum PWM control time tBLANK (8) = (1/ (8/8PWMCLK) ) × 256 tBLANK (7) = (1/ (7/8PWMCLK) ) × 256 tBLANK (3) OUT 00~OUT 15 PWM data = 00 H OFF Maximum PWM control time tBLANK (1) = (1/ (1/8PWMCLK) ) × 256 Output OFF because data is 00H though it can on. Because data is 01 H output is ON with 1/255 of tBLANK. Because data is 80 H output is ON with 128/255 of tBLANK. Because data is 80 H output is ON with 254/255 of tBLANK. Note 12: PWM operation timing: PWM pulse output on the output pins is initiated when BLANK goes Low. (there is simultaneous output on all 16 pins) Output pulse only once toward BLANK signal’s changing once in L from H. Hence, if PWM data is to be re-used, BLANK must be pulled Low again. PWMCLK division: As shown in the central part of the upper figure, the brightness of the LED module can be set to any one of eight levels without adjusting the current value, simply by dividing by PWMCLK. For large-scale brightness adjustment, division by PWMCLK is recommended. 26 2005-04-20 TB62718AFG Logic Input and Output Timing Waveforms 1. PI CLK (SI CLK) vs. PI DATA [7:0] (SI DATA) PI CLK (SI CLK) vs. PO DATA [7:0] (SO DATA) twH PI CLK (SI CLK) PI DATA [7:0] (SI DATA) 50% twL 50% 50% 50% 50% thold tsetup PO DATA [7:0] (SO DATA) 50% 50% tpd tpd 2. PI SEL (SI SEL) vs. PI CLK (SI CLK) twH PI CLK (SI CLK) twL 50% 50% 50% PI DATA [7:0] (SI DATA) PI SEL (SI SEL) 50% tsetup 50% thold tsetup 27 50% thold 2005-04-20 TB62718AFG 3. PI LATCH (SI LATCH) vs. PI CLK (SI CLK) twH PI CLK (SI CLK) twL 50% 50% 50% PI DATA [7:0] (SI DATA) (Internal flip-flop data) tsetup PI LATCH (SI LATCH) thold 50% 50% twltH 50% twltL 4. PI SEL (SI SEL) vs. PO DATA 00~PO DATA 07 (SO DATA) PI SEL (SI SEL) 50% 50% PO DATA [7:0] (SO DATA) 50% 50% tpd tpd 5. DOE vs. PO DATA 00~PO DATA 07 DOE 50% 50% PO DATA [7:0] tpzH/zL 28 tpzH/zL 2005-04-20 TB62718AFG Logic Input and Constant-current Output Timing Waveforms 1. BLANK vs. OUT 00~OUT 15 with PWMCLK twblkL BLANK 50% twblkH 50% 50% 50% PWMCLK Maximum delay time is 1 PWMCLK cycle. OUT 00~OUT 15 (current waveform) Maximum delay time is 1 PMCLK cycle. 50% 50% tpLH tpHL 2. RESET vs. OUT 00~OUT 15 BLANK twrstL RESET 50% 50% OUT [15:0] (current waveform) 50% tpHL 3. LED TEST vs. OUT 00~OUT 15 twledH LED TEST 50% 50% tpLH OUT 00~OUT 15 (current waveform) 50% 50% tpHL 29 2005-04-20 TB62718AFG Package Dimensions Weight: 0.26 g (typ.) 30 2005-04-20 TB62718AFG About solderability, following conditions were confirmed • Solderability Use of Sn-63Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 31 2005-04-20