DATA SHEET MOS INTEGRATED CIRCUIT µPD16835 MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT The µPD16835 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional driver ICs that use bipolar transistors. Because the µPD16835 controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been reduced. This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. The µPD16835 is housed in a 38-pin shrink SOP to contribute to the miniaturization of the application set. This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders. FEATURES • Four H bridge circuits employing power MOS FETs • Current-controlled 64-step micro step driving • Motor control by serial data (8 bytes × 8 bits) (original oscillation: 4-MHz input) Data is input with the LSB first. EVR reference setting voltage: 100 to 250 mV (@VREF = 250 mV) ... 4-bit data input (10-mV step) Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step) Original oscillation division or internal oscillation selectable Number of pulses in 1 VD: 0 to 252 pulses ... 6 bits + 2-bit data input (4 pulses/step) Step cycle: 0.25 to 8,191.75 µs ... 15-bit data input (0.25-µs step) • 3-V power supply. Minimum operating voltage: 2.7 V (MIN.) • Low current consumption IDD: 3 mA (MAX.), IDD (reset): 100 µA (MAX.), IMO: 1 µA (MAX.) • 38-pin shrink SOP (300 mil) ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter Symbol Supply voltage Input voltage Reference voltage H bridge drive currentNote 1 Instantaneous H bridge drive Power Rating Unit VDD -0.5 to +6.0 V VM -0.5 to +11.2 V VIN -0.5 to VDD + 0.5 V VREF 500 mV DC ±150 mA/phase PW ≤ 10 ms, Duty ≤ 5% ±300 mA/phase PT 1.0 W TCH (MAX) 150 °C Tstg -55 to +150 °C IM (DC) currentNote 1 consumptionNote 2 Peak junction temperature Storage temperature IM (pulse) Condition Notes 1. Permissible current per phase with the IC mounted on a PCB. 2. When the IC is mounted on a glass epoxy PCB (10 cm × 10 cm × 1 mm). The information in this document is subject to change without notice. Document No. G11594EJ1V0DS00 (1st edition) Date Published August 1998 J CP(K) Printed in Japan © 1998 µPD16835 RECOMMENDED OPERATING RANGE Parameter Symbol Supply voltage Input voltage MIN. TYP. MAX. Unit VDD 2.7 5.5 V VM 4.8 11 V VIN 0 VDD V Reference voltage VREF 275 mV EXP pin input voltage VEXPIN 225 VDD V EXP pin input current IEXPIN 100 µA H bridge drive current IM (DC) -100 +100 mA H bridge drive current IM (pulse)Note 1 -200 +200 mA Clock frequency (OSCIN) fCLKNote 2 3.9 4.2 MHz Clock frequency amplitude VfCLKNote 2 0.7VDD VDD V Serial clock frequency (SCLK) fSCLK 5.0 MHz Video sync signal width PW LATCH signal wait time t (VD-LATCH) Note SCLK wait time t (SCLK-LATCH) Note SDATA setup time (VD)Note 3 250 4 250 ns 400 ns 400 ns tsetupNote 4 80 ns SDATA hold time tholdNote 4 80 ns Chopping frequency foscNote 3 32 Reset signal pulse width fRST 100 Operating temperature TA -10 Peak junction temperature TCH (MAX) 4 4 124 µs +70 °C 125 °C Notes 1. PW ≤ 10 ms, duty ≤ 5% 2. COSC = 33 pF, VREF = 250 mV 3. fCLK = 4 MHz 4. Serial data delay (see the figure below.) VD t (VD-LATCH) LATCH 64 clocks (8 bits × 8 bytes) SCLK t (SCLK-LATCH) t (SCLK-LATCH) Ignored because LATCH is at L level. LATCH SDATA SCLK 2 Ignored because LATCH is at L level. 50% D1 50% t (SCLK-LATCH) D2 50% tsetup thold D3 kHz µPD16835 ELECTRICAL CHARACTERISTICS DC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, VREF = 250 mV, TA = 25°C, fCLK = 4 MHz, COSC = 33 pF, CFIL = 1,000 pF, EVR = 100 mV (0000)) Parameter Symbol Condition MIN. TYP. MAX. Unit Off VM pin current IMO (RESET) No load, reset period 1.0 µA VDD pin current IDD Output open 3.0 mA VDD pin current IDD (RESET) Reset period 100 µA High-level input voltage VIH Low-level input voltage VIL LATCH, SCLK, SDATA, VD, RESET, OSCIN Input hysteresis voltage VH Monitor output voltage 1 (EXTOUT α, β) VOMα (H), VOMβ (H) 5th byte VOMα (L), VOMβ (L) 5th byte Pull up (VDD) VOEXP (L) IOEXP = 100 µA High-level input current IIH VIN = VDD Low-level input current IIL VIN = 0 Reset pin high-level input current IIH (RST) VRST = VDD Reset pin low-level input current IIL (RST) VRST = 0 Input pull-down resistor RIND LATCH, SCLK, SDATA, VD H bridge ON resistanceNote 1 RON IM = 100 mA Chopping frequency (internal oscillation: COSC = 100 pF) fOSC (1) DATA: 00000 (4th byte) fOSC (2) DATA: 11111 (4th byte) Step frequency fSTEP Minimum step VD delayNote 2 ∆tVD Sine wave peak output IM L = 25 mH/R = 100 Ω (1 kHz) EVR = 200 mV (1010) RS = 6.8 Ω, fOSC = 64 kHz VEVR EVR = 200 mV (1010) VEVRSTEP Minimum step V 0.1*VDD V VDD V 0.1*VDD V 0.06 mA µA -1.0 1.0 50 3.5 200 kΩ 5.0 Ω 0 124 kHz 150 4 kHz 52 370 µA µA -1.0 100 V mV 250 currentNote 3 FIL pin step 0.3*VDD 0.9*VDD VOEXP (H) voltageNote 4 V 300 Monitor output voltage 2 (EXP 0 to 4: open drain) FIL pin voltageNote 4 0.7*VDD 400 ns mA 430 20 mV mV AC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, TA = 25°C, fCLK = 4 MHz) Parameter H bridge output circuit turn on time H bridge output circuit turn off time Symbol tONH tOFFH Condition TYP. MAX. Unit IM = 100 mANote 5 1.0 2.0 µs mANote 5 1.0 2.0 µs IM = 100 MIN. Notes 1. Total of ON resistance at top and bottom of output H bridge 2. By OSCIN and VD sync circuit 3. FB pin is monitored. 4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin. 5. 10% to 90% of the pulse peak value without filter capacitor (CFIL) 3 µPD16835 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4 LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 EXP2 RESET OSCOUT OSCIN SCLK SDATA LATCH VD EXTβ B2 FBB B1 VM2 A2 FBA A1 VM1 EXTα EXP3 PGND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 µPD16835 PIN FUNCTION No. Name Function 1 LGND Control circuit GND pin 2 COSC Chopping capacitor connection pin 3 FILA α 1-ch filter capacitor connection pin (1,000 pF TYP.) 4 FILB α 2-ch filter capacitor connection pin (1,000 pF TYP.) 5 FILC β 1-ch filter capacitor connection pin (1,000 pF TYP.) 6 FILD β 2-ch filter capacitor connection pin (1,000 pF TYP.) 7 VREF Reference voltage input pin (250 mV TYP.) 8 VDD Control circuit supply voltage input pin 9 VM3 Output circuit supply voltage input pin 10 D2 β 2-ch output pin 11 FBD β 2-ch sense resistor connection pin 12 D1 β 2-ch output pin 13 VM4 Output circuit supply voltage connection pin 14 C2 β 1-ch output pin 15 FBC β 1-ch sense resistor connection pin 16 C1 β 1-ch output pin 17 EXP0 Output monitor pin (open-drain) 18 EXP1 Output monitor pin (open-drain) 19 EXP2 Output monitor pin (open-drain) 20 PGND Power circuit GND pin 21 EXP3 Output monitor pin (open-drain) 22 EXTα Logic circuit monitor pin 23 VM1 Output circuit supply voltage input pin 24 A1 α 1-ch output pin 25 FBA α 1-ch sense resistor connection pin 26 A2 α 1-ch output pin 27 VM2 Output circuit supply voltage input pin 28 B1 α 2-ch output pin 29 FBB α 2-ch sense resistor connection pin 30 B2 α 2-ch output pin 31 EXTβ Logic circuit monitor pin 32 VD Video sync signal input pin 33 LATCH Latch signal input pin 34 SDATA Serial data input pin 35 SCLK Serial clock input pin 36 OSCIN Original oscillation input pin (4 MHz TYP.) 37 OSCOUT Original oscillation output pin 38 RESET Reset signal output pin 5 µPD16835 I/O PIN EQUIVALENT CIRCUIT Pin name Equivalent circuit Pin name Equivalent circuit VDD VDD LATCH SDATA SCLK VDD Pad OSCIN RESET Pad Pull-down resistor (125 Ω) VDD OSCOUT EXTα EXTβ VDD EXP0 EXP1 EXP2 EXP3 Pad Pad VDD VREF Pad VDD FILA FILB FILC FILD Pad Buffer VM A1, A2 B1, B2 C1, C2 D1, D2 Parasitic diodes Pad FB 6 OSCOUT 37 RESET VD 36 SCLK VREF 32 7 SDATA 35 LATCH 34 BLOCK DIAGRAM OSCIN EXP0 EXP1 EXP2 EXP3 33 17 18 19 21 38 VDD 8 VM1 23 ×2 SERIAL-PARARELLE DECODER VM2 27 VM3 9 PULSE GENERATER EXTOUT SELECTOR 1/N VM4 13 EVR1 COSC 2 SELECTOR OSC EVR2 CURRENT SET α EVR1 EVR2 22 CURRENT SET β 31 + + + - FILTER VM DGND 1 PGND 20 H BRIDGE α 1 ch - FILTER 24 A1 H BRIDGE α 2 ch 26 A2 3 FILA 29 FBB + - FILTER VM 28 B1 H BRIDGE β 1 ch 30 B2 4 FILB 15 FBC + FILTER VM 16 C1 H BRIDGE β 2 ch 14 C2 5 FILC 11 FBD 12 D1 10 D2 6 FILD 7 µPD16835 FBA + VM 25 EXTβ + + - EXTα 100 kΩ × 4 4 MHz OSCIN OSCOUT VD VREF EXP0 EXP1 EXP2 EXP3 SCLK SDATA LATCH RESET REGULATOR 3.3 V ×2 VDD VM1 SERIAL-PARARELLE DECODER VM2 VM3 EXTOUT SELECTOR PULSE GENERATER 1/N VM4 COSC BATTERY 4.8 V-11 V SELECTOR OSC EVR1 EVR2 EVR1 EVR2 CURRENT SETα CURRENT SETβ EXTα EXAMPLE OF STANDARD CONNECTION 8 250 mV EVR : 1010 fOSC : 64 kHz CPU EXTβ 33 pF + + + + - + - FILTER VM + - FILTER VM + - FILTER VM + FILTER VM DGND PGND H BRIDGE α 1 ch FBA A1 H BRIDGE α 2 ch A2 FILA FBB B1 B2 FILB H BRIDGE β 1 ch FBC C1 H BRIDGE β 2 ch C2 FILC FBD D1 D2 FILD 6.8 Ω × 2 6.8 Ω 1000 pF 6.8 Ω 1000 pF 1,000 pF × 2 MOTOR 2 µPD16835 MOTOR 1 Initialization TIMING CHART (1) RESET VD LATCH Initial DATA I1 Standard S1 Dummy data EXP: 1 S2 EXP : 0 ENABLE: 0 Standard EXP : 1 ENABLE: 1 S3 Standard EXP : 1 error DATA Standard S4 Standard EXP : 0 ENABLE: 1 S5 EXP : 1 ENABLE: 0 OSCOUT (original oscillation) Input at rising edge of RESET Start point wait (FF1) Output by I1 data Start point wait + start point drive wait (FF2) Output by I1 data Output by S2 data setting ENABLE OUTNote 1 Output by S5 data setting Output by chopping setting of I1 data Chopping pulse Output by EXP setting of S1 data Output by EXP setting of I1 data EXP_0-3 Output by EXP setting of S2DATA S4DATA output Pulse error S2DATA output PULSE OUT Outputs high level while pulse is being generated PULSE GATE (FF3) Outputs high level for standard data while a pulse output signal exists (LATCH cycle) PULSE CHECKNote 2 (FF7) CHECK SUMNote 3 High level because data is normal. No pulse output because data is erroneous Low level because data is abnormal. Restore to high level because data is normal. Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low SCLK to high, and at the falling edge of FF2 when the level changes from high to low. D0 D1 D2 (LSB) Data is held at rising edge of SCLK. D3 D4 D5 D6 D7 2. FF7 is an output signal that is used to check for the presence or absence of a pulse in the standard data, is updated at the falling edge of LATCH and reset once at the rising edge of LATCH. If CHECK SUM is other than “00h”, FF7 goes low, inhibiting pulse output, even if a pulse is generated. 9 3. CHECK SUM output is updated at the falling edge of LATCH. µPD16835 SDATA 1st byte → 8th byte Enable µPD16835 TIMING CHART (2) CLK (PULSE OUT) MOB (CW mode) Current direction: A2 → A1 H bridge α , β 1-ch output status Current direction: A1 → A2 H bridge α , β 2-ch output status Current direction: B2 → B1 Current direction: B2 → B1 Current direction: B1 → B2 (Expanded view) CW mode CCW mode CW mode CLK PULSE OUT Position No. Note In CW mode : Position No. is incremented. In CCW mode : Position No. is decremented. 1 2 3 4 5 6 5 4 3 2 3 4 CCW H bridge 1-ch output status CW CW CCW CW CW H bridge 2-ch output status CCW CW CW CCW Remarks 1. The current value of the actual wave is approximated to the value shown on the next page. 2. The C1, C2, D1, and D2 pins of β channel correspond to the A1, A2, B1, and B2 pins of α channel. 3. The CW mode is set if the D7 bit of the second and fifth bytes of the standard data is “0”. 4. The CCW mode is set if the D7 bit of the second and fifth bytes of the standard data is “1”. 10 µPD16835 RELATION BETWEEN ROTATION ANGLE, PHASE CURRENT, AND VECTOR QUANTITY (64-DIVISION MICRO STEP) (Values of µPD16835 for reference) Step θ0 Rotation angle (θ ) 0 A phase current B phase current Vector quantity MIN. TYP. MAX. MIN. TYP. MAX. TYP. - 0 - - 100 - 100 θ1 5.6 2.5 9.8 17.0 - 100 - 100.48 θ2 11.3 12.4 19.5 26.5 93.2 98.1 103 100 θ3 16.9 22.1 29.1 36.1 90.7 95.7 100.7 100.02 θ4 22.5 31.3 38.3 45.3 87.4 92.4 97.4 100.02 θ5 28.1 40.1 47.1 54.1 83.2 88.2 93.2 99.99 θ6 33.8 48.6 55.6 62.6 78.1 83.1 88.1 99.98 θ7 39.4 58.4 63.4 68.4 72.3 77.3 82.3 99.97 θ8 45 65.7 70.7 75.7 65.7 70.7 75.7 99.98 θ9 50.6 72.3 77.3 82.3 58.4 63.4 68.4 99.97 θ 10 56.3 78.1 83.1 88.1 48.6 55.6 62.6 99.98 θ 11 61.9 83.2 88.2 93.2 40.1 47.1 54.1 99.99 θ 12 67.5 87.4 92.4 97.4 31.3 38.3 45.3 100.02 θ 13 73.1 90.7 95.7 100.7 22.1 29.1 36.1 100.02 θ 14 78.8 93.2 98.1 103 12.4 19.5 26.5 100 θ 15 84.4 - 100 - 2.5 9.8 17.0 100.48 θ 16 90 - 100 - - 0 - 100 Remark These data do not indicate guaranteed values. 11 µPD16835 STANDARD CHARACTERISTIC CURVES PT vs. TA characteristics IMO (RESET) vs. VM characteristics 1.4 1 OFF VM pin current IMO (RESET) (µ A) Total power dissipation PT (W) 1.2 1.0 125°C/W 0.8 0.6 0.4 0.2 0 -10 0 20 40 60 80 100 Ambient temperature TA (°C) 0.8 0.6 0.4 0.2 0 120 TA = 25°C, no load, after reset 4 IDD vs. VDD characteristics 200 VDD pin current IDD (mA) VDD pin current at reset state IDD (RESET) (µA) TA = 25°C, operating, output open 4 3 2 1 2 3 4 5 Control circuit supply volage VDD (V) TA = 25°C, after reset 150 100 50 0 6 2 VIH/VDD, VIL/VDD vs. VDD characteristics High-level/low-level input current IIH/IIL (µ A) Input voltage VIH/VDD, VIL/VDD 6 60 TA = 25°C 12 3 4 5 Control circuit supply volage VDD (V) IIH/IIL vs. VIN characteristics 1 0.8 0.6 VIH VIL 0.4 0.2 0 12 IDD (RESET) vs. VDD characteristics 5 0 6 8 10 Output circuit supply voltage VM (V) 2 3 4 5 Control circuit supply volage VDD (V) 6 TA = 25°C, IIH: VIN = VDD, IIL: VIN = 0 40 IIH 20 IIL 0 2 3 5 4 Input voltage VIN (V) 6 µPD16835 fOSC vs. VDD characteristics fSTEP vs. VDD characteristics 6 TA = 25°C, COSC = 100 pF, DATA: all high 140 TA = 25°C, COSC = 100 pF Step frequency fSTEP (kHz) Chopping frequency fOSC (kHz) 150 130 120 110 5 4 3 100 90 2 3 4 5 Control circuit supply voltage VDD (V) 2 6 2 VREFVER vs. VDD characteristics IM (MAX) vs. EVR characteristics Sine wave peak output current IM (MAX) (mA) TA = 25°C, VREF = 250 mV EVR variable voltage VREFVER (mV) 6 80 40 30 20 10 0 3 4 5 Control circuit supply voltage VDD (V) 2 5 3 4 Control circuit supply voltage VDD (V) 6 70 TA = 25°C, VM = 6 V Rs = 6.8 Ω, fOSC = 64 kHz, L = 25 mH/R = 100 Ω at 1 kHz 60 50 40 30 20 50 100 150 200 250 Reference setting voltage EVR (mV) 300 tON, tOFF vs. VM characteristics Turn-on time, turn-off time tON/tOFF (ns) 500 TA = 25°C, IM = 100 mA, CFIL: none 400 300 tON tOFF 200 100 0 4 10 6 8 Output circuit supply voltage VM (V) 12 13 µPD16835 I/F CIRCUIT DATA CONFIGURATION (fCLK = 4-MHz EXTERNAL CLOCK INPUT) Input data consists of serial data (8 bytes × 8 bits). Input serial data with the LSB first, from the first byte to eighth byte. (1) Initial data (2) Standard data <1st byte> Bit Data <1st byte> Function Setting Bit DATA selection D7 Data Function Setting 0 HEADER DATA2 DATA selection D7 1 HEADER DATA2 D6 1 HEADER DATA1 D6 0 HEADER DATA1 D5 1 HEADER DATA0 D5 0 HEADER DATA0 D4 0 - D4 0 - D3 1 or 0 EXP_3 Z or L D3 1 or 0 EXP_3 Z or L D2 1 or 0 EXP_2 Z or L D2 1 or 0 EXP_2 Z or L D1 1 or 0 EXP_1 Z or L D1 1 or 0 EXP_1 Z or L D0 1 or 0 EXP_0 Z or L D0 1 or 0 EXP_0 Z or L - Z: High impedance, L: Low level (current sink) <2nd byte> Bit D7 D6 Data - Z: High impedance, L: Low level (current sink) <2nd byte> Function 8-bit data First Point Wait inputNote Setting Bit Start point wait 256 µs to 65.28 ms D7 1 or 0 α ROTATION α ch CCW/CW D6 1 or 0 α ENABLE α ch ON/OFF D5 6-bit data input α Pulse Number α ch Number of pulses in 1 V D5 D4 Setting (1 to 255) ∆t = 256 µs D3 D2 D4 Data Function Setting D3 D2 Setting (0 to 63) ∆n = 4 pulsesNote D1 D1 D0 D0 Note Input other than “0”. Note The number of pulses can be varied in 4-pulse steps. <3rd byte> Bit D7 D6 Data <3rd byte> Function 8-bit data First Point inputNote Magnetize Wait Setting Bit Start point drive wait 256 µs to 65.28 ms D7 D5 D4 D3 D2 D5 Setting (1 to 255) ∆t = 256 µs D4 D3 D2 D1 D1 D0 D0 Note Input other than “0”. 14 D6 Data 15-bit data Low-order 8-bit data input Function α Pulse Width Setting α ch pulse cycle 0.25 to 8,191.75 µs Setting (1 to 32,767) ∆t = 0.25 µs µPD16835 <4th byte> Bit Data <4th byte> Function Bit Internal/external D7 1 or 0 Current Set α set2/set1 15-bit data α Pulse Width α ch pulse cycle: 0.25 to 8,191.75 µs D7 1 or 0 D6 0 - - D6 D5 0 - - D5 D4 5-bit data Chopping input Frequency Chopping frequency: 32 to 124 kHz D4 D3 OSCSEL Setting D2 Setting (8 to 31)Note ∆f = 4 kHz D1 D0 Note Data D3 High-order 8-bit data D2 input Function Setting Setting (1 to 32,767) ∆t = 0.25 µs D1 D0 The frequency is 0 kHz if 0 to 7 is input. <5th byte> Bit Data <5th byte> EXT_α EXT_β Bit - - D7 1 or 0 β ROTATION β ch CCW/CW Data Function Setting D7 0 D6 Note 5 ENABLE α Note 1 ENABLE β Note 1 D6 1 or 0 β ENABLE β ch ON/OFF D5 Note 5 ROTATION α Note 2 ROTATION β Note 2 D5 β Pulse Number D4 Note 5 Pulse Out α Pulse Out β D4 6-bit data input D3 Note 5 FF7 α FF7 β β ch Number of pulses in 1 V D3 D2 Note 5 FF3 α FF3 β D2 D1 Note 5 ChecksumNote 3 FF2 β D1 D0 Note 5 ChoppingNote 4 FF1 β D0 Notes 1. H level: Conducts, L level: Stops Setting (1 to 63) ∆n = 4 pulsesNote Note The number of pulses can be varied in 4-pulse 2. H level: Reverse (CCW), steps. L level: Forward (CW) 3. H level: Normal data input, L level: Abnormal data input 4. Not output in internal oscillation mode. 5. Select one of D0 to D6 and input “1”. If two or more of D0 to D6 are selected, they are positively ORed for output. <6th byte> Bit D7 D6 Data <6th byte> Function 4-bit data α ch input Current Set2 D5 Setting α ch Output current setting 2 EVR: 100 to 250 mV Setting (0 to 15)Note D4 D3 D2 Bit D7 D6 D5 D4 4-bit data α ch input Current Set1 D1 α ch Output current setting 1 EVR: 100 to 250 mV Setting (0 to 15)Note D0 D3 D2 Data 15-bit data Low-order 8-bit data input Function β Pulse Width Setting β ch pulse cycle: 0.25 to 8,191.75 µs Setting (1 to 32,767) ∆t = 0.25 µs D1 D0 Note A voltage of about double EVR is output to the FIL pin. 15 µPD16835 <7th byte> Bit D7 D6 Data <7th byte> Function 4-bit data β ch input Current Set2 D5 Setting β ch Output current setting 2 EVR: 100 to 250 mV Setting (0 to 15)Note D4 D3 D2 Bit D1 β ch Output current setting 1 EVR: 100 to 250 mV Setting (0 to 15)Note D0 Function Setting D7 1 or 0 Current Set β set2/set1 D6 15-bit data β Pulse Width β ch pulse cycle: 0.25 to 8,191.75 µs D5 D4 4-bit data β ch input Current Set1 Data D3 D2 High-order 7-bit data input Setting (1 to 32,767) ∆t = 0.25 µs D1 D0 Note A voltage of about double EVR is output to the FIL pin. <8th byte> Bit Data <8th byte> Function Checksum Setting Bit ChecksumNote D7 1 or 0 D7 1 or 0 D6 1 or 0 D6 1 or 0 D5 1 or 0 D5 1 or 0 D4 1 or 0 D4 1 or 0 D3 1 or 0 D3 1 or 0 D2 1 or 0 D2 1 or 0 D1 1 or 0 D1 1 or 0 D0 1 or 0 D0 1 or 0 Note Data is input so that the sum of the first through the eighth bytes is 00h. 16 Data Function Checksum Setting ChecksumNote Note Data is input so that the sum of the first through the eighth bytes is 00h. µPD16835 DATA CONFIGURATION Data can be input in either of two ways. Initial data can be input when the power is first applied, or standard data can be input during normal operation. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the first byte. Therefore, the D7 bit of the eighth byte is the most significant bit (MSB). When inputting initial data, set a start-point wait time that specifies the delay from power application to pulse output, and the start-point drive wait time. At the same time, also set a chopping frequency and a reference voltage (EVR) that determines the output current of each channel. Because the µPD16835 has an EXT pin for monitoring the internal operations, the parameter to be monitored can be selected by initial data. When inputting standard data, input the rotation direction of each channel, the number of pulses, and the data for the pulse cycle. Initial data or standard data is selected by using bits D5 to D7 of the first byte (see Table 1). Table 1. Data Selection Mode (1st byte) If the high-order three bits are high, the initial data is selected; D7 D6 D5 Data type 1 1 1 Initial data if they are low, the standard data is selected. Data other than 0 0 0 Standard data (0, 0, 0) and (1, 1, 1) must not be input. Input the serial data during start-point wait time. Details of Data Configuration How to input initial data and standard data is described below. (1) Initial data input <First byte> The first byte specifies the type of data (initial data or standard data) and determines the presence or absence of the EXP pin output. Bits D5 to D7 of this byte specify the type of data as shown in Table 1, while bits D0 to D3 select the EXP output (open drain). Table 2. First Byte Data Configuration Bit Data D7 D6 D5 D4 1 1 1 0 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 The EXP pin goes low (current sink) when the input data is “0”, and high (high-impedance state) when the input data is “1”. Pull this pin up to VDD for use. Input “0” to bit D4. <Second byte> The second byte specifies the delay between data being read and data being output. This delay is called the start-up wait time, and the motor can be driven from that point at which the start-up wait time is “0”. This time is counted at the rising edge of VD. The start-up wait time can be set to 65.28 ms (when a 4-MHz clock is input), and can be fine-tuned by means of 8-bit division (256-µs step: with 4-MHz clock). The start-up wait time is set to 65.28 ms when all the bits of the second byte are set to “1”. Always input data other than “0” to this byte because the start-up wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. Transfer standard data during the start-up wait time. 17 µPD16835 <Third byte> The third byte specifies the delay between the start-point wait time being cleared and the output pulse being generated. This time is called the start-up drive wait time, and the output pulse is generated from the point at which the start-up drive wait time reaches “0”. The start-up drive wait time is counted at the falling edge of the start-up wait time. The start-up drive wait time can be set to 65.28 ms (with 4-MHz clock) and can be fine-tuned by means of 8-bit division (256-µs step: with 4-MHz clock). The start-up drive wait time is set to 65.28 ms when all the bits of the third byte are “1”. Always input data other than “0” to this byte because the start-up drive wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. <Fourth byte> The fourth byte selects a chopping frequency by using 5-bit data. It also selects whether the chopping frequency is created by dividing the original oscillation (external clock) or whether the internal oscillator is used. The chopping frequency is selected by bits D0 to D4. Bit D7 specifies the method used to create the chopping frequency. When this bit is “0”, the original oscillation (external clock input to OSCIN) is used; when it is “1”, the internal oscillator is used. Bits D5 and D6 are fixed to “0”. The chopping signal is output after the initial data has been input and the first standard data has been latched (see Timing Chart). Table 3. Fourth Byte Data Configuration (Initial data) Bit Data D7 D6 D5 0 or 1 0 0 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 The chopping frequency is set to 0 kHz and to a value in the range of 32 to 124 kHz (in 4-kHz steps), as follows. Although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the loworder 2 bits fixed to 0). Bit D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 0 0 0 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 0 0 1 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 0 0 1 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 0 1 1 1 1 1 fOSC = 0 kHz Data Bit fOSC = 0 kHz Data Bit fOSC = 32 kHz Data Bit fOSC = 36 kHz Data Bit fOSC = 124 kHz Data 18 µPD16835 <Fifth byte> The fifth byte selects a parameter to be output to the EXTOUT pin (logic operation monitor pin). Input data to bits D0 to D6 of this byte. Bit D7 is fixed to “0”. There are two EXTOUT pins. EXTOUT α indicates the operating status of α ch, and EXTOUT β indicates that of β ch. The relationship between each bit and each EXTOUT pin is as shown in Table 4. Table 4. Fifth Byte Data Configuration (Initial data) Bit Data EXTOUT α EXTOUT β D7 0 Not used Not used D6 0 or 1 ENABLE α ENABLE β D5 0 or 1 ROTATION α ROTATION β D4 0 or 1 PULSEOUT α PULSEOUT β D3 0 or 1 FF7 α FF7 β D2 0 or 1 FF3 α FF3 β D1 0 or 1 CHECKSUM FF2 β D0 0 or 1 CHOPPING FF1 β The checksum bit is cleared to “0” in the event of an error. Normally, it is “1”. If two or more signals that output signals to EXTOUT α and EXTOUT β are selected, they are positively ORed for output. The CHOPPING signal is not output in internal oscillation mode. The meanings of the symbols listed in Table 4 are as follows: ENABLE: Output setting (H: Conducts, L: Stops) ROTATION: Rotation direction (H: Reverse (CCW), L: Forward (CW)) PULSEOUT: Output pulse signal FF7: Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in standard data.) FF3: Pulse gate (output while pulse exists) FF2: Outputs H level during start-up wait time + start-up drive wait time FF1: Outputs H level during start-up wait time CHECKSUM: Checksum output (H: when normal data is transmitted, L: when abnormal data is transmitted) CHOPPING: Chopping wave output (in original oscillation mode only) 19 µPD16835 <Sixth byte> The sixth byte sets the peak output current value of α ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within the range of 200 to 500 mV, in units of 20 mV. The µPD16835 can set two values of the EVR reference voltage in advance. This is done by using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT_SET bit in the standard data. If all the bits of the sixth byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR reference voltage of 500 mV is selected. Table 5. Sixth Byte Data Configuration (Initial data) Bit D7 Data D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRα2) Bits D0 to D3: Reference voltage 1 (EVRα1) <Seventh byte> The seventh byte specifies the peak output current value of β ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within a range of 200 to 500 mV, in units of 20 mV. The µPD16835 can set two values of the EVR reference voltage in advance. This is done using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT_SET bit in the standard data. If all the bits of the seventh byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR reference voltage of 500 mV is selected. Table 6. Seventh Byte Data Configuration (Initial data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRβ2) Bits D0 to D3: Reference voltage 1 (EVRβ1) <Eighth byte> The eighth byte is checksum data. Normally, the sum of the 8-byte data is 00h. If the sum is not 00h because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is kept “L”. 20 µPD16835 (2) Standard data input <First byte> The first byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is input. Table 7. First Byte Data Configuration Bit Data D7 D6 D5 D4 1 1 1 0 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 The EXP pin goes low (current sink) when the input data is “0”, and high (high-impedance state) when the input data is “1”. Input “0” to bit D4. <Second byte> The second byte specifies the rotation direction of the α channel, enables output of the α channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in 1 cycle of FF2) of the α channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is “0”; it is in the reverse direction (CCW mode) when the bit is “1”. Bit D6 is used to enable the output of the α channel. The α channel enters the high-impedance state when this bit is “0”; it is in conduction mode when the bit is “1”. The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit uses an 8-bit counter with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually generated during start-up wait time + start-up drive wait (FF2) cycle is the number of pulses input × 4. The number of pulses can be set to a value in the range of 0 to 252, in units of four pulses. Table 8. Second Byte Data Configuration (Standard data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Rotation direction ENABLE Number of pulses 21 µPD16835 <Third and fourth bytes> The third and fourth bytes select the pulse cycle of the α channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SET α). The pulse cycle is specified using 15 bits: bits D0 (least significant bit) to D7 of the third byte, and bits D0 to D6 (most significant bit) of the fourth byte. The pulse cycle can be set to a value in the range of 0.25 to 8,191.75 µs in units of 0.25 µs (with a 4-MHz clock). CURRENT SET α is specified by bit D7 of the fourth byte. When this bit is “0”, reference voltage 1 (EVRα1) is selected; when it is “1”, reference voltage 2 (EVRα2) is selected. For further information, refer to the description of the sixth byte of the initial data. Table 9. Fourth Byte Data Configuration Table 10. Third Byte Data Configuration (Standard data) Bit D7 Data D6 D5 D4 (Standard data) D3 D2 D1 D0 D7 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 CURRENT SET α D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Most significant bit Least significant bit (Reference) Sixth Byte Data Configuration for Initial Data Bit D7 Data D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRα2) Bits D0 to D3: Reference voltage 1 (EVRα1) <Fifth byte> The fifth byte specifies the rotation direction of the β channel, enables output of the β channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in one cycle of FF2) of the β channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is “0”; it is in the reverse direction (CCW mode) when the bit is “1”. Bit D6 is used to enable the output of the β channel. The β channel goes into a high-impedance state when this bit is “0”; it is in the conduction mode when the bit is “1”. The number of pulses is set by bits D0 to D5. It is set by six bits in terms of software. However, the actual circuit uses an 8-bit decoder with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually generated during start-up wait time + start-up drive wait (FF2) cycle is the number of pulses input × 4. The number of pulses can be set in a range of 0 to 252 and in units of four pulses. Table 11. Fifth Byte Data Configuration (Standard data) Bit Data D7 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Rotation direction 22 D6 ENABLE Number of pulses µPD16835 <Sixth and seventh bytes> The sixth and seventh bytes select the pulse cycle of the β channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SET β). The pulse cycle is specified using 15 bits: bits D0 (least significant bit) to D7 of the sixth byte, and bits D0 to D6 (most significant bit) of the seventh byte. The pulse cycle can be set to a value in the range of 0.25 to 8,191.75 µs in units of 0.25 µs (with a 4-MHz clock). CURRENT SET β is specified by bit D7 of the seventh byte. When this bit is “0”, reference voltage 1 (EVRβ1) is selected; when it is “1”, reference voltage 2 (EVRβ2) is selected. For further information, refer to the description of the seventh byte of the initial data. Table 12. Seventh Byte Data Configuration Table 13. Sixth Byte Data Configuration (Standard data) Bit D7 Data D6 D5 D4 (Standard data) D3 D2 D1 D0 D7 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 CURRENT SET β D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Most significant bit Least significant bit (Reference) Seventh Byte Data Configuration for Initial Data Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRβ2) Bits D0 to D3: Reference voltage 1 (EVRβ1) <Eighth byte> The eighth byte is checksum data. Normally, the sum of the 8-byte data is 00h. If the sum is not 00h because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is held at “L”. Data Update Timing The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product are set and updated at the following latch timing. Table 14. Data Update Timing 1→1 0→1 1→0 0→0 Pulse width FF2 ↓ FF2 ↓ FF2 ↓ - Number of pulses FF2 ↓ FF2 ↓ FF2 ↓ - Rotation direction FF2 ↓ FF2 ↓ FF2 ↓ - Current setting FF2 ↓ FF1 ↓ FF2 ↓ - ENABLE FF2 ↓ FF1 ↓ FF2 ↓ - ENABLE change 23 µPD16835 The timing at which data is to be updated differs, as shown in Table 14, depending on the enabled status. For example, suppose the enable signal is currently “0” (output high-impedance) and “1” (output conduction) is input by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at FF2 (upon the completion of start-up wait), and the current setting and ENABLE signals are updated at FF1 (upon completion of start-up drive wait). VD FF1 Start-up wait FF2 Start-up wait + start-up drive wait Pulse output Pulse width, number of pulses, and rotation direction are updated. Current setting and ENABLE are updated (ENABLE change: 0 to 1). VD (1) LATCH Initial data identification (2) S2 (2) Pulse width Internal data retained. Output reset Not output Rotation direction Internal output retained Not output Number of pulses Internal data retained. Output reset Not output Current setting Internal output retained Not output ENABLE Internal output retained Not output S3 → I1 data is output. FF1, FF2 output Standard data identification (1) 24 (3) S1 I1 (3) Updated to S2 data at FF2 Updated to S2 data at either FF1 or FF2 by enable data of (2) µPD16835 The initial mode of this product is as follows. The IC operation can be initialized as follows: (1) Turns ON VDD. (2) Make RESET input “L”. (3) Input serial initial data. In initial mode, the operating status of the IC is as shown in Table 15. Table 15. Operations in Initial Mode Item Specifications Current consumption 100 µA OSC Oscillation stops. Input of external clock is inhibited. VD Input inhibited. FF1 to FF7 “L” level PULSE OUT “L” level EXP0 to EXP3 Undefined in the case of (1) above. Previous value is retained in the case of (2) above. Can be updated by serial data in the case of (3) above. Serial operation Can be accessed after initialization in the case of (1) above. Can be accessed after RESET has gone “H” in the case of (2) above. Can be accessed in the case of (3) above. Step pulse output is inhibited and FF7 is made “L” if the following conditions are satisfied. (1) If the set number of pulses (2nd/5th: standard data) is 00h. (2) If the checksum value is other than 00h. (3) If the start-up wait time is set to 1VD or longer. (4) If the start-up wait time + start-up drive wait time is set to 1VD or longer. (5) If start-up wait is completed earlier than LATCH (↓). (6) If VD is not input. 25 µPD16835 HINTS ON CORRECT USE (1) With this product, input the data for start-up wait and start-up drive wait. Because the standard data are set or updated by these wait times, if the start-up wait time and start-up drive wait time are not input, the data are not updated. (2) The start-up wait time must be longer than LATCH. (3) If the rising of the start-up drive wait time is the same as the falling of the last output pulse, a count error occurs, and the IC may malfunction. (4) Input the initial data in a manner that it does not straddle the video sync signal (VD). If it does, the initial data is not latched. (5) Transmit the standard data during the start-up wait time (FF1). If it is input at any other time, the data may not be transmitted correctly. (6) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to prevent the leakage of noise from the output circuit. 26 µPD16835 PACKAGE 38 PIN PLASTIC SHRINK SOP (300 mil) 38 20 detail of lead end P 1 19 A H F G I J S C N S L B K D M M E NOTE 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 12.45+0.26 –0.2 0.490+0.011 –0.008 B 0.51 MAX. 0.020 MAX. C 0.65 (T.P.) 0.026 (T.P.) D 0.32+0.08 –0.07 0.013 +0.003 –0.004 E 0.125±0.075 0.005±0.003 F 2.0 MAX. 0.079 MAX. G H 1.7±0.1 8.1±0.3 0.067±0.004 0.319±0.012 I 6.1±0.2 0.240±0.008 J 1.0±0.2 0.039+0.009 –0.008 K 0.17 +0.08 –0.07 0.007+0.003 –0.004 L 0.5±0.2 0.020+0.008 –0.009 M N 0.10 0.10 0.004 0.004 P 3°+7° –3° 3°+7° –3° P38GS-65-300B-2 27 µPD16835 RECOMMENDED SOLDERING CONDITIONS This product should be soldered under the following conditions. For details of the soldering method and when soldering under conditions other than those given below, contact NEC. • For details of the recommended soldering conditions, refer to the Semiconductor Device Mounting Technology Manual. Soldering method Soldering conditions Symbol indicating recommended soldering Infrared reflow Package peak temperature: 235°C, Time: 30 seconds MAX. (at 210°C MIN.), IR35-00-3 Number of times: 3 MAX., Number of days: NoneNote, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% MAX.) is recommended. VPS Package peak temperature: 215°C, Time: 40 seconds MAX. (at 200°C MIN.), VP-15-00-3 Number of times: 3 MAX., Number of days: NoneNote, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% MAX.) is recommended. Wave soldering Package peak temperature: 260°C, Time: 10 seconds MAX., Preheating temperature: 120°C MAX., Number of times: 1, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% MAX.) is recommended. WS60-00-1 Note Number of days the device can be stored after the dry pack has been opened, at conditions of 25°C, 65% RH. Caution Do not use two or more soldering methods in combination. 28 µPD16835 [MEMO] 29 µPD16835 [MEMO] 30 µPD16835 [MEMO] 31 µPD16835 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5