DATA SHEET MOS INTEGRATED CIRCUIT µPD442002-X 2M-BIT CMOS STATIC RAM 128K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD442002-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM. The µPD442002-X is packed in 48-pin TAPE FBGA. Features • 131,072 words by 16 bits organization • Fast access time : 70, 85, 100 ns (MAX.) • Byte data control : /LB (I/O1 to I/O8), /UB (I/O9 to I/O16) • Low voltage operation : VCC = 2.7 to 3.6 V (-BB70X) VCC = 2.2 to 3.6 V (-BC70X) VCC = 1.8 to 2.2 V (-DD85X, -DD10X) • Low VCC data retention : 1.0 V (MIN.) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application µPD442002 Access time Operating supply Operating ambient ns (MAX.) voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) −25 to +85 30 4 2 15 3 -BB70X 70 2.7 to 3.6 -BC70X 70 2.2 to 3.6 85, 100 1.8 to 2.2 -DD85X, -DD10X Supply current The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M14670EJ7V1DS00 (7th edition) Date Published July 2004 NS CP(K) Printed in Japan The mark Ì shows major revised points. 2000 µPD442002-X Ordering Information Part number Package µPD442002F9-BB70X-BC2-A Note Operating Operating ns (MAX.) supply voltage temperature V °C −25 to +85 70 2.7 to 3.6 Note 70 2.2 to 3.6 µPD442002F9-DD85X-BC2-A Note 85 1.8 to 2.2 µPD442002F9-BC70X-BC2-A µPD442002F9-DD10X-BC2-A 48-pin TAPE FBGA (8×6) Access time Note 100 Note Lead-free product Marking Image Part number Marking (XX) µPD442002F9-BB70X-BC2-A B2 µPD442002F9-BC70X-BC2-A C2 µPD442002F9-DD85X-BC2-A D3 µPD442002F9-DD10X-BC2-A D4 J S2M0-XX INDEX MARK 2 Data Sheet M14670EJ7V1DS Lot No. µPD442002-X Pin Configuration /xxx indicates active low signal. 48-pin TAPE FBGA (8× ×6) Bottom View Top View A B C D E F G H 1 2 3 4 5 6 6 1 2 3 4 5 6 A /LB /OE A0 A1 A2 NC B I/O9 /UB A3 A4 /CS C I/O10 I/O11 A5 A6 D GND I/O12 NC E VCC I/O13 F I/O15 G H 5 4 3 2 1 6 5 4 3 2 1 A NC A2 A1 A0 /OE /LB I/O1 B I/O1 /CS A4 A3 /UB I/O9 I/O2 I/O3 C I/O3 I/O2 A6 A5 I/O11 I/O10 A7 I/O4 VCC D VCC I/O4 A7 NC I/O12 GND NC A16 I/O5 GND E GND I/O5 A16 NC I/O13 VCC I/O14 A14 A15 I/O6 I/O7 F I/O7 I/O6 A15 A14 I/O14 I/O15 I/O16 NC A12 A13 /WE I/O8 G I/O8 /WE A13 A12 NC I/O16 NC A8 A9 A10 A11 NC H NC A11 A10 A9 A8 NC A0 to A16 : Address inputs I/O1 to I/O16 : Data inputs / outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable /LB, /UB : Byte data select VCC : Power supply GND : Ground NC : No Connection Remark Refer to Package Drawing for the index mark. Data Sheet M14670EJ7V1DS 3 µPD442002-X Block Diagram VCC GND A0 A16 Address buffer Row decoder I/O1 to I/O8 I/O9 to I/O16 Input data controller Memory cell array 2,097,152 bits Sense amplifier / Switching circuit Column decoder Address buffer /CS /LB /UB /WE /OE 4 Data Sheet M14670EJ7V1DS Output data controller µPD442002-X Truth Table /CS /OE /WE /LB /UB Mode I/O Supply current I/O1 to I/O8 I/O9 to I/O16 H × × × × Not selected High-Z High-Z × × × H H Not selected High-Z High-Z L H H L × Output disable High-Z High-Z × L Output disable High-Z High-Z L L Word read DOUT DOUT L H Lower byte read DOUT High-Z H L Upper byte read High-Z DOUT L L Word write DIN DIN L H Lower byte write DIN High-Z H L Upper byte write High-Z DIN L × H L ISB ICCA Remark × : VIH or VIL Data Sheet M14670EJ7V1DS 5 µPD442002-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Rating Unit -BB70X, -BC70X –0.5 Note -DD85X, -DD10X VCC Input / Output voltage VT Operating ambient temperature TA –25 to +85 –25 to +85 °C Storage temperature Tstg –55 to +125 –55 to +125 °C –0.5 Note to +4.0 –0.5 Note Supply voltage to VCC+0.4 (4.0 V MAX.) –0.5 Note to +2.7 V to VCC+0.4 (2.7 V MAX.) V Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Operating ambient TA Condition -BB70X -BC70X -DD85X, -DD10X Unit MIN. MAX. MIN. MAX. MIN. MAX. 2.7 3.6 2.2 3.6 1.8 2.2 V 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.4 2.4 VCC+0.4 – – V 2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.3 – – 1.8 V ≤ VCC < 2.2 V – – – – 1.6 VCC+0.2 –0.3 Note –25 +0.5 +85 –0.3 Note –25 +0.4 –0.2 Note +0.2 V +85 –25 +85 °C MIN. TYP. MAX. Unit temperature Note –1.0 V (MIN.) (Pulse width : 20 ns) Capacitance (TA = 25°°C, f = 1 MHz) Parameter Symbol Test condition Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 6 Data Sheet M14670EJ7V1DS µPD442002-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition -BB70X MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CS = VIH or –1.0 +1.0 µA mA /WE = VIL or /OE = VIH Operating supply current ICCA1 /CS = VIL, II/O = 0 mA, Minimum cycle time – 30 ICCA2 /CS = VIL, II/O = 0 mA, Cycle time = ∞ – 4 ICCA3 /CS ≤ 0.2 V, Cycle time = 1 µs, II/O = 0 mA, – 4 – 0.6 mA µA VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CS = VIH or /LB = /UB = VIH ISB1 /CS ≥ VCC – 0.2 V 0.3 4 ISB2 /LB = /UB ≥ VCC – 0.2 V, /CS ≤ 0.2 V 0.3 4 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1.0 mA Remark 2.4 V 0.4 V VIN : Input voltage VI/O : Input / Output voltage Data Sheet M14670EJ7V1DS 7 µPD442002-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition -BC70X MIN. TYP. -DD85X, -DD10X MAX. MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CS = VIH or –1.0 +1.0 –1.0 +1.0 µA mA /WE = VIL or /OE = VIH Operating supply current ICCA1 /CS = VIL, II/O = 0 mA, – 30 – – VCC ≤ 2.7 V – 25 – – VCC ≤ 2.2 V – – – 15 – 4 – – VCC ≤ 2.7 V – 2 – – VCC ≤ 2.2 V – – – 1 /CS ≤ 0.2 V, Cycle time = 1 µs, – 4 – – II/O = 0 mA, VIL ≤ 0.2 V, VCC ≤ 2.7 V – 3 – – VIH ≥ VCC – 0.2 V – – – 3 – 0.6 – – VCC ≤ 2.7 V – 0.6 – – VCC ≤ 2.2 V – – – 0.6 0.3 4 – – VCC ≤ 2.7 V 0.25 3.5 – – VCC ≤ 2.2 V – – 0.2 3 0.3 4 – – VCC ≤ 2.7 V 0.25 3.5 – – VCC ≤ 2.2 V – – 0.2 3 Minimum cycle time ICCA2 /CS = VIL, II/O = 0 mA, Cycle time = ∞ ICCA3 Standby supply current ISB ISB1 ISB2 /CS = VIH or /LB = /UB = VIH /CS ≥ VCC – 0.2 V /LB = /UB ≥ VCC – 0.2 V, /CS ≤ 0.2 V High level output voltage Low level output voltage Remark VOH VOL VCC ≤ 2.2 V IOH = –0.5 mA 2.4 – VCC ≤ 2.7 V 1.8 – VCC ≤ 2.2 V – 1.5 IOL = 1.0 mA – VCC ≤ 2.7 V 0.4 – VCC ≤ 2.2 V – 0.4 VI/O : Input / Output voltage 8 Data Sheet M14670EJ7V1DS µA V 0.4 VIN : Input voltage mA V µPD442002-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load [ -BB70X ] 1TTL + 50 pF [ -BC70X, -DD85X, -DD10X ] 1TTL + 30 pF Data Sheet M14670EJ7V1DS 9 µPD442002-X Read Cycle (1/2) Parameter VCC ≥ 2.7 V Symbol Unit Condition -BB70X MIN. MAX. Read cycle time tRC 70 ns Address access time tAA 70 ns /CS access time tACS 70 ns /OE to output valid tOE 35 ns /LB, /UB to output valid tBA 70 ns Output hold from address change tOH 10 ns /CS to output in low impedance tLZ 10 ns /OE to output in low impedance tOLZ 5 ns /LB, /UB to output in low impedance tBLZ 10 ns /CS to output in high impedance tHZ 25 ns /OE to output in high impedance tOHZ 25 ns /LB, /UB to output in high impedance tBHZ 25 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/2) Parameter Symbol VCC ≥ 2.2 V VCC ≥ 1.8 V -BC70X MIN. MAX. 70 -DD85X MIN. MAX. 85 Unit -DD10X MIN. MAX. Read cycle time tRC Address access time tAA 70 85 100 ns /CS access time tACS 70 85 100 ns /OE to output valid tOE 35 40 50 ns /LB, /UB to output valid tBA 70 85 100 ns Output hold from address change tOH 10 10 10 ns /CS to output in low impedance tLZ 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /LB, /UB to output in low impedance tBLZ 10 10 10 ns /CS to output in high impedance tHZ 25 30 35 ns /OE to output in high impedance tOHZ 25 30 35 ns /LB, /UB to output in high impedance tBHZ 25 30 35 ns Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. 10 Data Sheet M14670EJ7V1DS Condition 100 ns Note 1 Note 2 µPD442002-X Read Cycle Timing Chart tRC Address (Input) tOH tAA /CS (Input) tHZ tACS tLZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ I/O (Output) Remark High-Z Data out In read cycle, /WE should be fixed to high level. Data Sheet M14670EJ7V1DS 11 µPD442002-X Write Cycle (1/2) Parameter VCC ≥ 2.7 V Symbol Unit Condition -BB70X MIN. MAX. Write cycle time tWC 70 ns /CS to end of write tCW 55 ns /LB, /UB to end of write tBW 55 ns Address valid to end of write tAW 55 ns Address setup time tAS 0 ns Write pulse width tWP 50 ns Write recovery time tWR 0 ns Data valid to end of write tDW 30 ns Data hold time tDH 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 ns 5 Note ns Note The output load is 1TTL + 5 pF. Write Cycle (2/2) Parameter Symbol VCC ≥ 2.2 V VCC ≥ 1.8 V -BC70X MIN. MAX. -DD85X MIN. MAX. Unit -DD10X MIN. MAX. Write cycle time tWC 70 85 100 ns /CS to end of write tCW 55 70 80 ns /LB, /UB to end of write tBW 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 55 60 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 30 35 40 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 5 30 5 Note The output load is 1TTL + 5 pF. 12 Data Sheet M14670EJ7V1DS Condition 35 5 ns ns Note µPD442002-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWP tWR /WE (Input) tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High-Z tDH Data in High-Z Indefinite data out Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). 2. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M14670EJ7V1DS 13 µPD442002-X Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW High-Z tDH Data in I/O (Input) High-Z Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). 14 Data Sheet M14670EJ7V1DS µPD442002-X Write Cycle Timing Chart 3 (/LB, /UB Controlled) tWC Address (Input) tCW /CS (Input) tAW tWP tWR /WE (Input) tAS tBW /LB, /UB (Input) tDW High-Z tDH Data in I/O (Input) High-Z Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). Data Sheet M14670EJ7V1DS 15 µPD442002-X Low VCC Data Retention Characteristics (TA = –25 to +85°°C) Parameter Symbol Test Condition -BB70X -BC70X -DD85X, -DD10X Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention VCCDR1 /CS ≥ VCC − 0.2 V 1.0 3.6 1.0 3.6 1.0 2.2 supply voltage VCCDR2 /LB = /UB ≥ VCC − 0.2 V, 1.0 3.6 1.0 3.6 1.0 2.2 V /CS ≤ 0.2 V Data retention ICCDR1 VCC = 1.2 V, /CS ≥ VCC − 0.2 V 0.15 2 0.15 2 0.15 2 supply current ICCDR2 VCC = 1.2 V, 0.15 2 0.15 2 0.15 2 µA /LB = /UB ≥ VCC − 0.2 V, /CS ≤ 0.2 V Chip deselection tCDR 0 0 0 ns to data retention mode Operation tR tRC Note recovery time Note tRC : Read cycle time 16 Data Sheet M14670EJ7V1DS tRC Note tRC Note ns µPD442002-X Data Retention Timing Chart (1) /CS Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note /CS VIH (MIN.) VCCDR (MIN.) /CS ≥ VCC – 0.2 V VIL (MAX.) GND Note 2.7 V (-BB70X), 2.2 V (-BC70X), 1.8 V (-DD85X, -DD10X) Remark On the data retention mode by controlling /CS, the other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) /LB, /UB Controlled tCDR Data retention mode tR VCC Note VCC (MIN.) /LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB ≥ VCC – 0.2 V VIL (MAX.) GND Note 2.7 V (-BB70X), 2.2 V (-BC70X), 1.8 V (-DD85X, -DD10X) Remark On the data retention mode by controlling /LB and /UB, the input level of /CS must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M14670EJ7V1DS 17 µPD442002-X Package Drawing 48-PIN TAPE FBGA (8x6) ZE E w ZD S B B 6 5 4 3 2 1 A D H G F E D C B A INDEX MARK w S A INDEX MARK A A2 y1 S S y e S φb φx A1 M S AB ITEM D MILLIMETERS 6.0±0.1 E 8.0±0.1 w e 0.2 A A1 A2 0.94±0.10 0.24±0.05 0.70 b x 0.40±0.05 0.08 y y1 0.1 0.2 0.75 ZD 1.125 ZE 1.375 P48F9-75-BC2 18 Data Sheet M14670EJ7V1DS µPD442002-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD442002-X. Types of Surface Mount Device µPD442002F9-BC2-A Note : 48-pin TAPE FBGA (8x6) Note Lead-free product Data Sheet M14670EJ7V1DS 19 µPD442002-X Revision History Edition/ Date Page Type of Previous This edition edition 7th edition/ Throughout Throughout Deletion Dec. 2003 p.2, 21 p.2, 19 Modification Location (Previous edition → This edition) revision Class -BB55X, -BB85X, -BC85X, -BC10X, -DD12X Package code F9-BC1 → F9-BC2-A Addition p.2 p.2 Modification Description "Note Lead-free product" has been added. Marking image Lead-free mark has been added. Index mark has been modified. p.20 20 p.18 Modification Package Drawing Data Sheet M14670EJ7V1DS Package drawing has been changed µPD442002-X [ MEMO ] Data Sheet M14670EJ7V1DS 21 µPD442002-X [ MEMO ] 22 Data Sheet M14670EJ7V1DS µPD442002-X NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. Data Sheet M14670EJ7V1DS 23 µPD442002-X • The information in this document is current as of July, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. • NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1