DATA SHEET MOS INTEGRATED CIRCUIT µPD444004 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT Description The µPD444004 is a high speed, low power, 4,194,304 bits (1,048,576 words by 4 bits) CMOS static RAM. Operating supply voltage is 5.0 V ± 0.5 V. The µPD444004 is packaged in a 32-pin plastic SOJ and 32-pin plastic TSOP (II). Features • 1,048,576 words by 4 bits organization • Fast access time : 8, 10, 12 ns (MAX.) • Output Enable input for easy application • Single +5.0 V power supply Ordering Information Part number Package • • • Supply current mA (MAX.) ns (MAX.) At operating At standby 10 µPD444004LE-8 32-pin plastic SOJ 8 190 µPD444004LE-10 (10.16 mm (400)) 10 170 12 160 32-pin plastic TSOP (II) 8 190 (10.16 mm (400)) 10 170 (Normal bent) 12 160 µPD444004LE-12 • Access time µPD444004G5-8-7JD Note µPD444004G5-10-7JD Note µPD444004G5-12-7JD Note Note Under development The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14426EJ3V0DS00 (3rd edition) Date Published January 2001 NS CP(K) Printed in Japan The mark • shows major revised points. © 1999 µPD444004 Pin Configuration (Marking Side) /××× indicates active low signal. 32-pin plastic SOJ (10.16 mm (400)) [ µPD444004LE ] 32-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent) [ µPD444004G5-×× ] ××-7JD ×× A0 1 32 A19 A1 2 31 A18 A2 3 30 A17 A3 4 29 A16 A4 5 28 A15 /CS 6 27 /OE I/O1 7 26 I/O4 VCC 8 25 GND GND 9 24 VCC I/O2 10 23 I/O3 /WE 11 22 A14 A5 12 21 A13 A6 13 20 A12 A7 14 19 A11 A8 15 18 A10 A9 16 17 NC A0 - A19 : Address Inputs I/O1 - I/O4 : Data Inputs / Outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawings for the 1-pin index mark. 2 Data Sheet M14426EJ3V0DS µPD444004 A0 | A19 I/O1 | I/O4 Row decoder Address buffer Block Diagram Memory cell array 4,194,304 bits Input data controller Sense amplifier / Switching circuit Output data controller Column decoder Address buffer /CS /OE /WE VCC GND Truth Table /CS /OE /WE Mode I/O Supply current H × × Not selected High impedance ISB L L H Read DOUT ICC L × L Write DIN L H H Output disable High impedance Remark × : Don’t care Data Sheet M14426EJ3V0DS 3 µPD444004 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Rating –0.5 Note Unit Supply voltage VCC to +7.0 V Input / Output voltage VT –0.5 Note to VCC+0.5 V Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Note –2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 5.0 5.5 V VCC+0.5 V +0.8 V 70 °C Supply voltage VCC 4.5 High level input voltage VIH 2.2 Low level input voltage VIL –0.5 Operating ambient temperature TA 0 Note –2.0 V (MIN.) (pulse width : 2 ns) 4 Data Sheet M14426EJ3V0DS Note µPD444004 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 V to VCC –2 +2 µA Output leakage current ILO VI/O = 0 V to VCC, –2 +2 µA mA /CS = VIH or /OE = VIH or /WE = VIL Operating supply current Standby supply current ICC /CS = VIL, Cycle time : 8 ns 190 II/O = 0 mA, Cycle time : 10 ns 170 Minimum cycle time Cycle time : 12 ns 160 ISB /CS = VIH, VIN = VIH or VIL 40 ISB1 /CS ≥ VCC – 0.2 V, 10 mA VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA 2.4 V 0.4 V MAX. Unit Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M14426EJ3V0DS 5 µPD444004 AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time ≤ 3 ns) 3.0 V 1.5 V Test Points 1.5 V 1.5 V Test Points 1.5 V GND Output Waveform Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2. Figure 1 Figure 2 (tAA, tACS, tOE, tOH) (tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW ) VTT = +1.5 V +5.0 V 50 Ω 480 Ω ZO = 50 Ω I/O (Output) I/O (Output) 30 pF CL Remark 6 255 Ω CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M14426EJ3V0DS 5 pF CL µPD444004 Read Cycle Parameter Symbol µPD444004-8 µPD444004-10 µPD444004-12 MIN. MIN. MIN. MAX. 8 MAX. 10 Unit Notes MAX. Read cycle time tRC 12 ns Address access time tAA 8 10 12 ns /CS access time tACS 8 10 12 ns /OE access time tOE 4 5 6 ns Output hold from address change tOH 3 3 3 ns /CS to output in low impedance tCLZ 3 3 3 ns /OE to output in low impedance tOLZ 0 0 0 ns /CS to output in high impedance tCHZ 4 5 6 ns /OE to output hold in high impedance tOHZ 4 5 6 ns 1 2, 3 Notes 1. See the output load shown in Figure 1. 2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are periodically sampled and not 100% tested. Remark These AC characteristics are in common regardless of package types. Read Cycle Timing Chart 1 (Address Access) tRC Address (Input) tAA tOH I/O (Output) Previous data out Data out Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS = /OE = VIL Data Sheet M14426EJ3V0DS 7 µPD444004 Read Cycle Timing Chart 2 (/CS Access) tRC Address (Input) tAA tACS /CS (Input) tCLZ tCHZ /OE (Input) tOHZ tOE tOLZ I/O (Output) High impedance Data out Caution Address valid prior to or coincident with /CS low level input. Remark In read cycle, /WE should be fixed to high level. 8 Data Sheet M14426EJ3V0DS High impedance µPD444004 Write Cycle Parameter Symbol µPD444004-8 µPD444004-10 µPD444004-12 MIN. MIN. MIN. MAX. MAX. Unit MAX. Write cycle time tWC 8 10 12 ns /CS to end of write tCW 6 7 8 ns Address valid to end of write tAW 6 7 8 ns Write pulse width tWP 6 7 8 ns Data valid to end of write tDW 4 5 6 ns Data hold time tDH 0 0 0 ns Address setup time tAS 0 0 0 ns Write recovery time tWR 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 4 3 5 6 3 Notes 3 ns 1, 2 ns Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are periodically sampled and not 100% tested. Remark These AC characteristics are in common regardless of package types. Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWR tWP /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. /CS or /WE should be fixed to high level during address transition. • 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. 2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M14426EJ3V0DS 9 µPD444004 Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. • 2. Do not input data to the I/O pins while they are in the output state. Remark 10 Write operation is done during the overlap time of a low level /CS and a low level /WE. Data Sheet M14426EJ3V0DS µPD444004 Package Drawings 32-PIN PLASTIC SOJ (10.16 mm (400)) B 32 17 C 1 D 16 G J E F U M N S M Q T P S K I H NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS B 21.26±0.2 C 10.16 D 11.18±0.2 E 1.005±0.1 F 0.74 G 3.5±0.2 H 2.545±0.2 I 0.8 MIN. J 2.6 K M 1.27(T.P.) 0.40±0.10 N 0.12 P 9.4±0.20 Q T 0.1 R0.85 U 0.20 +0.10 −0.05 P32LE-400A-1 Data Sheet M14426EJ3V0DS 11 µPD444004 32-PIN PLASTIC TSOP (II) (10.16mm (400)) 32 17 detail of lead end F P E 1 16 A H G C D M N M J I S L S B NOTE Each lead centerline is located within 0.21 mm of its true position (T.P.) at maximum material condition. K ITEM MILLIMETERS A 21.17 MAX. B 1.075 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E 0.1±0.05 F 1.2 MAX. G H 0.97 11.76±0.2 I J 10.16±0.1 0.8±0.2 K 0.145 +0.025 −0.015 L 0.5±0.1 M 0.21 N 0.10 P +7° 3° −3° S32G5-50-7JD2-1 12 Data Sheet M14426EJ3V0DS µPD444004 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD444004. Types of Surface Mount Device µPD444004LE : 32-pin plastic SOJ (10.16 mm (400)) µPD444004G5-7JD : 32-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent) Data Sheet M14426EJ3V0DS 13 µPD444004 [MEMO] 14 Data Sheet M14426EJ3V0DS µPD444004 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14426EJ3V0DS 15 µPD444004 • The information in this document is current as of January, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. 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