DATA SHEET MOS INTEGRATED CIRCUIT µPD434008A 4M-BIT CMOS FAST SRAM 512K-WORD BY 8-BIT Description The µPD434008A is a high speed, low power, 4,194,304 bits (524,288 words by 8 bits) CMOS static RAM. Operating supply voltage is 5.0 V ± 0.5 V. The µPD434008A is packaged in 36-pin plastic SOJ. Features • 524,288 words by 8 bits organization • Fast access time : 12, 15, 17, 20 ns (MAX.) • Output Enable input for easy application • Single +5.0 V power supply Ordering Information Part number Package Access time Supply current mA (MAX.) ns (MAX.) At operating At standby 10 µPD434008ALE-12 36-pin plastic SOJ 12 200 µPD434008ALE-15 (10.16 mm (400)) 15 170 µPD434008ALE-17 17 160 µPD434008ALE-20 20 150 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M12226EJ4V0DS00 (4th edition) Date Published May 2000 NS CP(K) Printed in Japan The mark • shows major revised points. © 1996 µPD434008A • Pin Configuration (Marking Side) /xxx indicates active low signal. 36-pin plastic SOJ (10.16 mm (400)) [ µPD434008ALE ] A0 1 36 NC A1 2 35 A18 A2 3 34 A17 A3 4 33 A16 A4 5 32 A15 /CS 6 31 /OE I/O1 7 30 I/O8 I/O2 8 29 I/O7 VCC 9 28 GND GND 10 27 VCC I/O3 11 26 I/O6 I/O4 12 25 I/O5 /WE 13 24 A14 A5 14 23 A13 A6 15 22 A12 A7 16 21 A11 A8 17 20 A10 A9 18 19 NC A0 - A18 : Address Inputs I/O1 - I/O8 : Data Inputs / Outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawing for the 1-pin index mark. 2 Data Sheet M12226EJ4V0DS00 µPD434008A A0 | A18 I/O1 | I/O8 Row decoder Address buffer Block Diagram Memory cell array 4,194,304 bits Input data controller Sense amplifier / Switching circuit Output data controller Column decoder Address buffer /CS /OE /WE VCC GND Truth Table /CS /OE /WE Mode I/O Supply current H × × Not selected High impedance ISB L L H Read DOUT ICC L × L Write DIN L H H Output disable High impedance Remark × : Don’t care Data Sheet M12226EJ4V0DS00 3 µPD434008A Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition Rating VCC –0.5 –0.5 Note Note Unit to +7.0 V to VCC+0.5 V Input / Output voltage VT Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Note –2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 5.0 5.5 V VCC+0.5 V +0.8 V 70 °C Supply voltage VCC 4.5 High level input voltage VIH 2.2 Low level input voltage VIL –0.5 Operating ambient temperature TA 0 Note –2.0 V (MIN.) (pulse width : 2 ns) 4 Data Sheet M12226EJ4V0DS00 Note µPD434008A DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 V to VCC –2 +2 µA Output leakage current ILO VI/O = 0 V to VCC, –2 +2 µA mA /CS = VIH or /OE = VIH or /WE = VIL Operating supply current Standby supply current ICC /CS = VIL, Cycle time : 12 ns 200 II/O = 0 mA, Cycle time : 15 ns 170 Minimum cycle time Cycle time : 17 ns 160 Cycle time : 20 ns 150 ISB /CS = VIH, VIN = VIH or VIL 50 ISB1 /CS ≥ VCC – 0.2 V, 10 mA VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA 2.4 V 0.4 V MAX. Unit Remark VIN : Input voltage VI/O : Input / Output voltage Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M12226EJ4V0DS00 5 µPD434008A AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time ≤ 3 ns) 3.0 V 1.5 V Test Points 1.5 V 1.5 V Test Points 1.5 V GND Output Waveform Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2. Figure 1 Figure 2 (for tAA, tACS, tOE, tOH) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW ) VTT = +1.5 V +5.0 V 50 Ω 480 Ω ZO = 50 Ω I/O (Output) I/O (Output) 30 pF CL Remark 6 255 Ω CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M12226EJ4V0DS00 5 pF CL µPD434008A Read Cycle Parameter µPD434008A µPD434008A µPD434008A µPD434008A -12 -15 -17 -20 Symbol MIN. MAX. MIN. 12 MAX. 15 MIN. MAX. 17 MIN. Unit Notes MAX. Read cycle time tRC 20 ns Address access time tAA 12 15 17 20 ns /CS access time tACS 12 15 17 20 ns /OE access time tOE 6 7 8 10 ns Output hold from address change tOH 3 3 3 3 ns /CS to output in low impedance tCLZ 3 3 3 3 ns /OE to output in low impedance tOLZ 0 0 0 0 ns /CS to output in high impedance tCHZ 6 7 8 8 ns /OE to output hold in high impedance tOHZ 6 7 8 8 ns 1 2, 3 Notes 1. See the output load shown in Figure 1. 2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are periodically sampled and not 100% tested. Read Cycle Timing Chart 1 (Address Access) tRC Address (Input) tAA tOH I/O (Output) Previous data out Data out Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS = /OE = VIL Data Sheet M12226EJ4V0DS00 7 µPD434008A Read Cycle Timing Chart 2 (/CS Access) tRC Address (Input) tAA tACS /CS (Input) tCLZ tCHZ /OE (Input) tOHZ tOE tOLZ I/O (Output) High impedance Data out Caution Address valid prior to or coincident with /CS low level input. Remark In read cycle, /WE should be fixed to high level. 8 Data Sheet M12226EJ4V0DS00 High impedance µPD434008A Write Cycle Parameter Symbol µPD434008A µPD434008A µPD434008A µPD434008A -12 -15 -17 -20 MIN. MAX. MIN. MAX. MIN. MAX. MIN. Unit MAX. Write cycle time tWC 12 15 17 20 ns /CS to end of write tCW 8 10 11 12 ns Address valid to end of write tAW 8 10 11 12 ns Write pulse width tWP 8 10 11 12 ns Data valid to end of write tDW 6 7 8 9 ns Data hold time tDH 0 0 0 0 ns Address setup time tAS 0 0 0 0 ns Write recovery time tWR 1 1 1 1 ns /WE to output in high impedance tWHZ Output active from end of write tOW 6 7 3 3 8 3 Notes 8 3 ns 1, 2 ns Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are periodically sampled and not 100% tested. Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWR tWP /WE (Input) tOW tWHZ I/O (Input / Output) Caution Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out /CS or /WE should be fixed to high level during address transition. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. • 2. During tWHZ, I/O pins are in the output state, therefore the input signals must not be applied to the output. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M12226EJ4V0DS00 9 µPD434008A Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) Data in tDH High impedance Caution /CS or /WE should be fixed to high level during address transition. Remark Write operation is done during the overlap time of a low level /CS and a low level /WE. 10 Data Sheet M12226EJ4V0DS00 µPD434008A • Package Drawing 36-PIN PLASTIC SOJ (10.16 mm (400)) B 36 19 C 1 D 18 G H J E F U Q M N S S T P M K I NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS B 23.6±0.20 C 10.16±0.1 D 11.18±0.2 E 1.005±0.1 F 0.74 G H 3.5±0.2 2.545±0.2 I 0.8 MIN. J K 2.6 1.27 (T.P.) M 0.42 +0.08 −0.07 N 0.12 P 9.4±0.20 Q 0.1 T R 0.85 U 0.22 +0.08 −0.07 P36LE-400A-2 Data Sheet M12226EJ4V0DS00 11 µPD434008A Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD434008A. Type of Surface Mount Device µPD434008ALE : 36-pin plastic SOJ (10.16 mm (400)) 12 Data Sheet M12226EJ4V0DS00 µPD434008A [ MEMO ] Data Sheet M12226EJ4V0DS00 13 µPD434008A [ MEMO ] 14 Data Sheet M12226EJ4V0DS00 µPD434008A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M12226EJ4V0DS00 15 µPD434008A • The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. 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