NEC UPD46128953-X

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
μPD46128953-X
128M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 32-BIT
ADDRESS / DATA MULTIPLEXED
EXTENDED TEMPERATURE OPERATION
Description
The μPD46128953-X is a high speed, low power, 134,217,728 bits (4,194,304 words by 32 bits) CMOS Mobile
Specified RAM featuring synchronous burst read and synchronous burst write function.
The μPD46128953-X realizes high performance with the SDR interface, command and data inputs / outputs are
synchronized the rising edge of clock.
The μPD46128953-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
• 4,194,304 words by 32 bits organization
• Low voltage operation: 1.7 to 2.0 V (1.85±0.15 V)
• Operating ambient temperature: TA = −25 to +85 °C
• Synchronous burst mode
Burst length
: 8 double words (Wrap)
Burst sequence
: Linear burst
Maximum clock frequency : 83 / 66 MHz
• SDR (Single Data Rate) Architecture
One data transfers per one clock cycle
All inputs/outputs are synchronized with the positive edge of the clock
• Write data mask (DM) for write operation
• Output Enable: /OE pin
• Chip Enable input: /CE1 pin
• Standby Mode input: CE2 pin
• Standby Mode 1: Normal standby (Memory cell data hold valid)
• Standby Mode 2: Density of memory cell data hold is variable
μPD46128953
-E12X
-E15X
Note
Clock
Operating
Operating
frequency
supply
ambient
At operating mA
At standby μA
MHz
voltage
temperature
(MAX.)
(MAX.)
(MAX.)
V
°C
83
1.7 to 2.0
−25 to +85
60
T.B.D.
66
Supply current
55
Note Under consideration
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M17506EJ1V1DS00 (1st edition)
Date Published September 2005 CP (K)
Printed in Japan
2005
μPD46128953-X
Ordering Information
μPD46128593-X is mainly shipping by wafer.
Please consult with our sales offices for package samples and ordering information.
2
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
Pin Configuration
The following is pin configuration of package sample.
/xxx indicates active low signal.
127-pin PLASTIC FBGA (13.0 x 11.5)
Top View
Bottom View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AB CD E F GH J K L MN P
PNM L K J HG F E DC B A
Top View
A
B
14
NC
13
NC
12
NC
NC
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ26
DQ25
DQ24
VDD
VSSQ
DQ23
DQ22
DQ28
DQ27
NC
NC
NC
NC
NC
VSS
A/DQ20 A/DQ19
10
DQ29
NC
NC
NC
NC
NC
A/DQ15
A/DQ7
A/DQ14 A/DQ18
9
DQ30
NC
NC
NC
NC
11
NC
DQ31
/WE
CE2
NC
NC
NC
A/DQ4
7
NC
NC
CLK
/ADV
/WAIT
NC
VDD
A/DQ3
6
NC
DM0
DM1
NC
NC
A/DQ1
A/DQ9
5
VSS
NC
NC
NC
NC
VSSQ
/OE
NC
NC
NC
NC
NC
NC
NC
NC
DM2
DM3
VDD
VSS
NC
4
A/DQ5
A/DQ17
VDDQ
NC
A/DQ16
NC
VDDQ
A/DQ11
VDDQ
NC
A/DQ10
A/DQ2
VSSQ
A/DQ0
A/DQ8
NC
/CE1
NC
NC
NC
NC
NC
A/DQ6 A/DQ13 A/DQ12
8
NC
A/DQ21
3
NC
NC
NC
NC
2
NC
NC
NC
NC
1
NC
NC
NC
NC
A/DQ0 to A/DQ021 : Address inputs , Data inputs/ outputs
/WAIT
DQ22 to DQ31
: Data inputs / outputs
DM0 to DM3 : Write data mask input
/CE1
: Chip select input
VDD
: Power supply
CE2
: Standby mode input
VSS
: Ground
/WE
: Write enable input
VDDQ
: Power supply for DQ
/OE
: Output enable input
VSSQ
: Ground for DQ
CLK
: Clock input
/ADV
: Address valid
NC
Note
: Wait output
: No Connection
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to 10. Package Drawing for the index mark.
Preliminary Data Sheet M17506EJ1V1DS
3
μPD46128953-X
Pin Function
(1/2)
Symbol
A/DQ0 to A/DQ21
Description
Synchronous address input/data input/output
These pins are used as address input pins and data input/output pins.
When they are used as address input pins, the input address is latched at the rising edge of CLK. When the
address is latched, the setup time and hold time must be satisfied at the rising edge of CLK.
When they are used as data input/output pins, the input data is latched at the rising edge of CLK. When
data is input, the setup time and hold time must be satisfied at the rising edge of CLK. Data is output from
these pins at the rising edge of CLK.
DQ22 to DQ31
Synchronous data input/output.
While the A/DQ pins function as address input pins and data input/output pins, these pins function only as
data input/output pins.
The input data is latched at the rising edge of CLK. When data is input, the setup time and hold time must
be satisfied at the rising edge of CLK. Data is output at the rising edge of CLK.
CLK
Input clock.
Addresses and control signals are latched in synchronization with this signal.
All the synchronous input signals must satisfy the setup time and hold time at the rising edge of CLK.
/ADV
Synchronous address valid input signal.
An address is latched at the rising edge of CLK while /ADV is LOW. When the address is latched, the setup
time and hold time must be satisfied at the rising edge of CLK.
Note: This signal serves as an asynchronous signal when the mode register set or read.
/CE1
Synchronous chip enable input.
This device is active while /CE1 is LOW. When inputting /CE1, the setup time and hold time must be
satisfied at the rising edge of CLK.
Remark This signal serves as an asynchronous signal when the mode register set or read.
CE2
Asynchronous power-down mode input
When this signal is made LOW, the device enters the power-down mode status.
CE2 is not synchronized with the clock. It is an asynchronous signal.
/OE
Synchronous output enable input.
When this signal is made LOW, read data is output.
When inputting /OE, the setup time and hold time must be satisfied at the rising edge of CLK.
Remark This signal serves as an asynchronous signal when the mode register set or read.
/WE
Synchronous write enable input.
When /WE inputs a LOW at the same time as /ADV, the device recognizes a write operation. When inputting
/WE, the setup time and hold time must be satisfied at the rising edge of CLK.
Remark This signal serves as an asynchronous signal when the mode register is set or read.
4
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
(2/2)
Symbol
DM0 to DM3
Description
Synchronous write data mask input.
These signals can mask write data during burst write.
To input data mask, the setup time and hold time must be satisfied at the rising edge of CLK.
Data mask can be controlled in byte units.
DM0: A/DQ0 to ADQ7
DM1: A/DQ8 to ADQ15
DM2: A/DQ16 to ADQ21, DQ22 to DQ23
DM3: DQ24 to DQ31
/WAIT
Synchronous wait output.
/WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write
This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready.
The wait signal is output at the rising edge of CLK.
VDD
Supply voltage:
Usually, the supply voltage is 1.85 V. Refer to DC Characteristics and Recommended Operation
Conditions.
VSS
Supply voltage:
Ground
VDDQ
Supply voltage:
Supply voltage for DQ. Usually, this voltage is 1.85 V. Refer to DC Characteristics and Recommended
Operation Conditions.
VSSQ
Supply voltage:
Ground for DQ.
NC
No connection
Some signals can be applied because this pin is not internally connected.
Preliminary Data Sheet M17506EJ1V1DS
5
μPD46128953-X
Block Diagram
VDD
Standby mode control
VSS
VDDQ
Refresh
state
control
Refresh
control
VSSQ
Refresh
counter
Memory cell array
134,217,728 bits
Row
decoder
Address buffer
/ADV
Address latch
Sense amplifier /
Switching circuit
Column decoder
/CE1
Data control
/WAIT
CE2
Command
control
Burst
counter
/WE
CLK
Latch circuit
Clock
control
Input / Output buffer
A/DQ0 to A/DQ21 DQ22 to DQ31
6
Preliminary Data Sheet M17506EJ1V1DS
DM0 to DM3
/OE
μPD46128953-X
Truth Table
Mode
Deselect (Standby Mode 1)
Power Down (Standby Mode 2)
Output Disable
Start Address Latch
Note1
/CE1
CE2
H
H
×
L
L
H
CLK
×
Note2
Start Address not Latch
Note3
/ADV
/OE
/WE
A/DQ0-A/DQ21 , DQ22-DQ31
×
×
×
High-Z
×
×
×
High-Z
×
H
×
High-Z
L
H
×
High-Z
H
×
×
Low-Z or High-Z
Read Command input
Note2
L
H
H
High-Z
Write Command input
Note2
L
H
L
High-Z
×
×
×
Low-Z to High-Z
×
×
×
High-Z
Burst Read Termination
Note4
Burst Write Termination
Note4
Notes 1.
2.
L to H
CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition).
Start address latch and read/write command input are performed at the next rising edge of clock when /ADV
is transferred HIGH to LOW.
3.
It is impossible that Start address latch and read/write command input are performed at the first rising edge
of clock during /ADV is fixed HIGH.
4.
Remark
Refer to 3.6 Burst Read Termination, 3.7 Burst Write Termination.
H, HIGH: VIH, L, LOW: VIL, ×: VIH or VIL
For read/write operation, refer to 7 Timing Charts.
Preliminary Data Sheet M17506EJ1V1DS
7
μPD46128953-X
CONTENTS
1. Initialization ................................................................................................................................................ 10
2. Partial Refresh ........................................................................................................................................... 11
2. 1 Standby Mode......................................................................................................................................................... 11
2. 2 Density Switching ................................................................................................................................................... 11
2. 3 Standby Mode Status Transition............................................................................................................................. 11
2. 4 Addresses for Which Partial Refresh Is Supported................................................................................................. 12
3. Burst Operation ......................................................................................................................................... 13
3. 1 Features of Burst Operation ................................................................................................................................... 13
3. 2 Latency ................................................................................................................................................................... 13
3. 3 Burst Length, Burst Sequence, Wrap Around ......................................................................................................... 16
3. 4 Burst Read End ...................................................................................................................................................... 17
3. 5 Burst Write End ...................................................................................................................................................... 18
3. 6 Burst Read Termination.......................................................................................................................................... 19
3. 7 Burst Write Termination .......................................................................................................................................... 20
3. 8 /WAIT signal behavior............................................................................................................................................. 21
3. 9 /WAIT output........................................................................................................................................................... 21
4. Mode Register Settings............................................................................................................................. 23
4. 1 Mode Register Setting Method ............................................................................................................................... 23
4. 1. 1 Cautions for Setting Mode Register............................................................................................................. 23
4. 1. 2 Mode Register Setting/Reading................................................................................................................... 25
4. 1. 3 Partial refresh Density ................................................................................................................................. 25
4. 1. 4 Burst length ................................................................................................................................................. 25
4. 1. 5 Function mode............................................................................................................................................. 26
4. 1. 6 Driver strength ............................................................................................................................................. 26
4. 1. 7 Read Latency .............................................................................................................................................. 26
4. 1. 8 Single Write ................................................................................................................................................. 26
4. 1. 9 Valid Clock Edge ......................................................................................................................................... 26
4. 1. 10 Reset to Asynchronous.............................................................................................................................. 26
4. 1. 11 /WE control................................................................................................................................................ 26
4. 1. 12 Setting of unused bits ................................................................................................................................ 26
4. 2 Mode Register Reading .......................................................................................................................................... 27
4. 2. 1 Cautions for Setting Mode Register............................................................................................................. 27
4. 2. 2 Data read from mode register...................................................................................................................... 27
5. Address, /OE, /WE, DM control ................................................................................................................ 29
5. 1 Relation of address inputs and /OE control ............................................................................................................ 29
5. 2 Address Latching .................................................................................................................................................... 30
5. 3 Read / Write Command Loading............................................................................................................................. 32
5. 4 /OE control during burst read operation.................................................................................................................. 34
5. 4. 1 /OE HIGH to LOW during burst read operation ........................................................................................... 34
5. 4. 2 /OE LOW to HIGH during burst read operation ........................................................................................... 35
5. 5 Write data mask signal (DM) control....................................................................................................................... 36
5. 5. 1 Controlling write data mask signal (DM) in write cycle ................................................................................. 36
5. 5. 2 Write data mask (DM) truth table................................................................................................................. 37
8
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
6. Electrical Specifications ........................................................................................................................... 38
7. Timing Charts............................................................................................................................................. 43
8. Mode Register Setting/Read Timing........................................................................................................ 49
8. 1 Mode Register Setting Timing ................................................................................................................................ 49
8. 2 Mode Register Setting Flow Chart .......................................................................................................................... 50
8. 3 Mode Register Read Timing ................................................................................................................................... 51
8. 4 Mode Register Read Flow Chart............................................................................................................................. 52
9. Standby Mode Timing Charts................................................................................................................... 53
10. Package Drawing..................................................................................................................................... 54
11. Recommended Soldering Conditions ................................................................................................... 55
Preliminary Data Sheet M17506EJ1V1DS
9
μPD46128953-X
1. Initialization
Initialize the μPD46128953-X at power application using the following sequence to stabilize internal circuits.
(1) Following power application, make CE2 HIGH after fixing CE2 to LOW for the period of tVHMH.
Make /CE1 HIGH before making CE2 HIGH.
(2) /CE1 and CE2 are fixed HIGH for the period of tMHCL.
Normal operation is possible after the completion of initialization.
Figure 1-1. Initialization Timing Chart
Normal Operation
Initialization
/CE1 (Input)
tCHMH
tMHCL
tVHMH
CE2 (Input)
VDD
Cautions 1.
2.
VDD (MIN.)
Make CE2 LOW when starting the power supply.
tVHMH is specified from when the power supply voltage reaches the prescribed minimum value
(VDD (MIN.)).
Initialization Timing
Parameter
Symbol
MIN.
MAX.
Unit
Power application to CE2 LOW hold
tVHMH
50
μs
/CE1 HIGH to CE2 HIGH
tCHMH
0
ns
Following power application CE2 HIGH hold to /CE1 LOW
tMHCL
300
μs
10
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
2. Partial Refresh
2. 1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 128M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2. 2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 64M bits, 32M bits, 16M bits, and 0M
bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the
mode register, these settings are retained until they are set again, while applying the power supply. However, the mode
register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 4. Mode Register Settings.)
2. 3 Standby Mode Status Transition
In Standby Mode 1, /CE1 and CE2 are HIGH. In Standby Mode 2, CE2 is LOW. In Standby Mode 2, if 0M bit is set as
the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal
operation from Standby Mode 2. When the density has been set to 64M bits, 32M bits, or 16M bits in Standby Mode 2, it
is not necessary to perform initialization to return to normal operation from Standby Mode 2.
For the timing charts, refer to Figure 9-1. Standby Mode 2 (data hold: 64M bits / 32M bits / 16M bits) Entry / Exit
Timing Chart, Figure 9-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
Preliminary Data Sheet M17506EJ1V1DS
11
μPD46128953-X
Figure 2-1. Standby Mode State Machine
Power On
Initialization
Mode Register
Setting
CE2 = V IH
/CE1 = V IL
Active
CE2 = V IL
CE2 = V IL
/CE1 = V IH,
CE2 = V IH
/CE1 = V IL,
CE2 = V IH
Standby
Mode 1
/CE1 = V IL,
CE2 = V IH
CE2 = V IL
Standby Mode 2
(64M bits / 32M bits
/ 16M bits)
CE2 = V IL
Standby Mode 2
(Data not held)
2. 4 Addresses for Which Partial Refresh Is Supported
Data hold density
12
Correspondence address
64M bits
000000H to 1FFFFFH
32M bits
000000H to 0FFFFFH
16M bits
000000H to 07FFFFH
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
3. Burst Operation
3. 1 Features of Burst Operation
Function
Features
Burst Length
8 double words
Burst Wrap
Wrap
Burst Sequence
Linear
Valid Clock Edge
CLK Rising Edge
Latency Count
Read Latency
6, 7, 8
Write Latency
5, 6, 7
3. 2 Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through Mode Register Set sequence after power-up. Once
RL is set through Mode Register Set sequence, write latency, that is the number of clock cycles between address being
latched and first write data being latched, is automatically set to RL−1.
Latency Count
Grade
Clock Frequency
Read Latency
Write Latency
-E12X
<83 MHz
7, 8
6, 7
-E15X
<66 MHz
6, 7, 8
5, 6, 7
Note
Note Write Latency = Read Latency−1
Preliminary Data Sheet M17506EJ1V1DS
13
μPD46128953-X
Figure 3-1. Latency Configuration (Read)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK (Input)
/ADV (Input)
/CE1 (Input)
Read Latency = 6
A/DQ0 to A/DQ21 (Input/Output)
DQ22 to DQ31 (Output)
High-Z
Add
High-Z
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q0
Q1
Q2
Q3
Q4
Q5
Q0
Q1
Q2
Q3
Q4
Q5
Read Latency = 7
A/DQ0 to A/DQ21 (Input/Output)
DQ22 to DQ31 (Output)
High-Z
Add
High-Z
Read Latency = 8
A/DQ0 to A/DQ21 (Input/Output)
DQ22 to DQ31 (Output)
14
High-Z
Add
High-Z
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
Figure 3-2. Latency Configuration (Write)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK (Input)
/ADV (Input)
/CE1 (Input)
Write Latency = 5
A/DQ0 to A/DQ21 (Input)
DQ22 to DQ31 (Input)
High-Z
Add
High-Z
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
Write Latency = 6
A/DQ0 to A/DQ21 (Input)
DQ22 to DQ31 (Input)
High-Z
Add
High-Z
Write Latency = 7
A/DQ0 to A/DQ21 (Input)
DQ22 to DQ31 (Input)
High-Z
Add
High-Z
Preliminary Data Sheet M17506EJ1V1DS
15
μPD46128953-X
3. 3 Burst Length, Burst Sequence, Wrap Around
The burst length is 8 double words and the corresponding address is (A/DQ2, A/DQ1, A/DQ0). A burst operation that
extends over addresses higher than A/DQ3 cannot be executed.
Wrap-around is performed within the burst length of 8 double words. Refer to Table 3-1. Burst Sequence.
Table 3-1. Burst Sequence
Start Address
Burst Sequence
(A/DQ2 , A/DQ1, A/DQ0)
Linear , Wrap
1st data - 2nd data - 3rd data - 4th data - 5th data - 6th data - 7th data - 8th data
16
(0, 0, 0)
(0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1)
(0, 0, 1)
(0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0)
(0, 1, 0)
(0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1)
(0, 1, 1)
(0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0)
(1, 0, 0)
(1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1)
(1, 0, 1)
(1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0)
(1, 1, 0)
(1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1)
(1, 1, 1)
(1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0)
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
3. 4 Burst Read End
The memory output goes into a high impedance state after completion of the burst read operation of the eighth double
word. Therefore, no data is output from the memory even if CLK is kept input while /CE1 = LOW after the burst read
operation of 8 words has been completed.
Figure 3-3. Burst Read End
T9
T10
T11
T12
T13
T14
T15
CLK (Input)
/ADV (Input)
H
/CE1 (Input)
L
/OE (Input)
L
tAC
tHZ
A/DQ0 to A/DQ21 (Output)
Q5
Q6
Q7
DQ22 to DQ31 (Output)
Q5
Q6
Q7
High-Z
High-Z
Remark Memory output goes into a high impedance state after the last data (Q7) read by the burst operation has
been output.
Preliminary Data Sheet M17506EJ1V1DS
17
μPD46128953-X
3. 5 Burst Write End
The memory does not input write data to internal circuits even if CLK is kept input with /CE1 = LOW and write data is
input from the controller after completion of a burst write operation of 8 double words.
Figure 3-4. Burst Write End
T8
T9
T10
T11
T12
T13
T14
CLK (Inout)
/ADV (Input)
H
/CE1 (Input)
L
/WE (Input)
tWDS tWDH
A/DQ0 to A/DQ21 (Input)
D5
D6
D7
A
B
C
DQ22 to DQ31 (Input)
D5
D6
D7
A
B
C
High-Z
High-Z
Remark The memory does not input any write data to internal circuits even if write data (A, B, or C) is input after the
last burst write data (D7) has been input, as shown in Figure 3-4.
18
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
3. 6 Burst Read Termination
A burst read termination is executed when /CE1 is made HIGH during a burst read operation. The command that the
burst read termination (/CE1 = HIGH) is recognized at the next rising edge of CLK when /CE1 = HIGH, the read data is
output before the command of the burst read termination (/CE1 = HIGH) is input.
Figure 3-5. Burst Read Termination
T4
T5
T6
T7
T8
T9
T10
CLK (Input)
/ADV (Input)
H
tCEH tCES
/CE1 (Input)
/OE (Input)
L
tAC
tHZ
A/DQ0-A/DQ21 (Output)
Q0
Q1
Q2
Q3
Q4
DQ22-DQ31 (Output)
Q0
Q1
Q2
Q3
Q4
High-Z
High-Z
Remark If the burst read termination is performed (/CE1: LOW → HIGH) before the rising edge of CLK in T8, as
shown in Figure 3-5, determined data is output as the read data (Q4) from the rising edge of CLK in T7.
The burst read termination is valid after the initial read data has been output.
(For the burst read termination, refer to Figure 7-5. Burst Read Termination Cycle Timing Chart (/CE1 control).)
Preliminary Data Sheet M17506EJ1V1DS
19
μPD46128953-X
3. 7 Burst Write Termination
A burst write termination is executed when /CE1 is made HIGH during a burst write operation. The command that the
burst write termination (/CE1 = HIGH) is recognized at the next rising edge of CLK when /CE1 = HIGH, the write data is
written before the command of the burst write termination (/CE1 = HIGH) is input.
Figure 3-6. Burst Write Termination
T3
T4
T5
T6
T7
T8
T9
CLK (Input)
/ADV (Input)
H
tCEH tCES
/CE1 (Input)
/WE (Input)
tWDS tWDH
A/DQ0 to A/DQ21 (Input)
D0
D1
D2
D3
D4
D5
DQ22 to DQ31 (Input)
D0
D1
D2
D3
D4
D5
High-Z
High-Z
Remark If the burst write termination is performed (/CE1: LOW → HIGH) before the rising edge of CLK in T8, as
shown in Figure 3-6, the write data is input to memory at the rising edge of CLK in T7. The write data input
in cycle T8 (D5) is invalid.
The burst termination is valid after the initial write data has been input.
(For the burst write termination refer to Figure 7-6. Burst Write Termination Cycle Timing Chart (/CE1 control).)
20
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
3. 8 /WAIT signal behavior
/WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write
This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready.
The wait signal is output at the rising edge of CLK.
Table 3-2. Relation Between Internal Operation of Memory and /WAIT Output
Internal Operation of Memory
/WAIT output
Preparation for burst read/burst write in progress
LOW
Completion of preparation for burst read/burst write
HIGH
3. 9 /WAIT output
The /WAIT output is enabled after specified time from CLK. /WAIT output is transferred LOW to HIGH one cycle before
1st burst read data output and 1st burst write data input.
Figure 3-7. /WAIT Output Timing (Read Cycle)
T0
T1
T2
T3
T4
T5
T6
CLK (Input)
/ADV (Input)
Read Latency = 6
A/DQ0 to A/DQ21 (Input/Output)
DQ22 to DQ31 (Output)
High-Z
Add
High-Z
Q0
tCEWA
1 cycle before latency cycle
Q0
tCLWA
/WAIT (Output)
Preliminary Data Sheet M17506EJ1V1DS
21
μPD46128953-X
Figure 3-8. /WAIT Output Timing (Write Cycle)
T0
T1
T2
T3
T4
T5
T6
D0
D1
D0
D1
CLK (Input)
/ADV (Input)
Write Latency = 5
A/DQ0 to A/DQ21 (Input)
DQ22 to DQ31 (Input)
High-Z
Add
High-Z
tCEWA
1 cycle before latency cycle
22
/WAIT (Output)
Preliminary Data Sheet M17506EJ1V1DS
tCLWA
μPD46128953-X
4. Mode Register Settings
The default value of the mode register of the μPD46128953-X is undefined upon power application. Therefore, be sure
to set the mode register after power application and initialization.
4. 1 Mode Register Setting Method
Each mode can be set by performing a total of six cycles of operations in succession after reading the most significant
address (3FFFFFH) – two consecutive cycles for writing any data and three consecutive cycles for writing specific data
(codes 1 to 3) – by an asynchronous access (with CLK fixed HIGH or LOW).
Table 4-1. Mode Register Settings
Cycle
Operation
Address
Data
1st cycle
Read
3FFFFFH
Don’t care
2nd cycle
Write
3FFFFFH
Don’t care
3rd cycle
Write
3FFFFFH
Don’t care
4th cycle
Write
3FFFFFH
Code 1 (A/DQ0 = 1)
5th cycle
Write
3FFFFFH
Code 2
6th cycle
Write
3FFFFFH
Code 3
Codes 1 to 3 are set at the register. The register has a function to latch an address and data necessary for instruction
execution, and does not occupy the memory.
Whether the mode register is set or read can be selected by code 1 in the 4th bus cycle. If setting of the mode register
is selected (A/DQ0 = 1) by code 1 in the 4th bus cycle, the contents of the mode register are set by code 2 in the 5th bus
cycle and code 3 in the 6th bus cycle.
The command contents are shown in Table 4-2. Mode Register Code 1 Definition (4th cycle), Table 4-3. Mode
Register Code 2 Definition (5th cycle), and Table 4-4. Mode Register Code 3 Definition (6th cycle).
For the timing chart and flowchart, refer to Figure 8-1. Mode Register Setting Timing Chart and Figure 8-2. Mode
Register Setting Flowchart.
If reading the mode register is selected by code 1 in the 4th bus cycle (A/DQ = 0), the contents of the mode register
currently set in the 5th and 6th bus cycles can be read. If the mode register is read before it is set, any (undefined) data
is read.
For the mode register, refer to 4.2 Mode Register Reading.
4. 1. 1 Cautions for Setting Mode Register
When the mode register is set, the status of the internal counter is identified by the toggle operation of /CE1 and /OE.
When setting a mod entry, therefore, perform a toggle operation of /CE1 in each cycle (one read cycle and five write
cycles).
In the 1st bus cycle (read cycle), perform a toggle operation of /OE in the same manner as /CE1. If an illegal address
or data is written or if an address and data are written in an incorrect sequence, the mode register is not correctly set.
If the most significant address (3FFFFFH) is read (in the 1st bus cycle), written (2nd bus cycle), and then written (3rd
bus cycle), a sequence of setting/reading the mode register is started. Therefore, setting of the mode register cannot be
stopped after the 4th bus cycle. If the normal sequence is executed up to the 5th bus cycle, setting of the mode register
cannot be stopped until the 6th bus cycle is completed.
Preliminary Data Sheet M17506EJ1V1DS
23
μPD46128953-X
Once the mode register has been set, the setting is retained while power is supplied and CE2 = HIGH, until it is re-set.
If data is not retained by turning off the power or making CE2 LOW (except partial), however, the setting of the mode
register is undefined. Re-set the register after power application or when returning from a data non-retention status.
For the timing chart and flowchart, refer to Figure 8-1. Mode Register Setting Timing Chart and Figure 8-2. Mode
Register Setting Flowchart.
Table 4-2. Mode Register Code1 Definition (4th Bus Cycle)
Data Code
A/DQ0
Symbol
RW
Function
Value
Description
Mode Register Setting /
0
Mode Register Reading
Mode Register Reading
1
Mode Register Setting
A/DQ21 to A/DQ1
−
−
All “1”
Reserved
DQ31 to DQ22
−
−
All “1”
Reserved
Table 4-3. Mode Register Code2 Definition (5th Bus Cycle)
Data Code
A/DQ1 to A/DQ0
A/DQ4 to A/DQ2
A/DQ5
A/DQ7 to A/DQ6
Symbol
PR
Function
Partial Refresh Density
BL
Burst length
M
Function Mode
DS
Driver Strength
Value
Description
00
32M
01
16M
10
64M
11
0M
000
Reserved
001
Reserved
010
8 double words
011
Reserved
100
Reserved
101
Reserved
110
Reserved
111
Reserved
0
Synchronous Burst
1
Reserved
00
Strong
01
Reserved
10
Weak
11
Middle
A/DQ21 to A/DQ8
–
–
All “1”
Reserved
DQ31 to DQ22
–
–
All “1”
Reserved
24
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
Table 4-4. Mode Register Code3 Definition (6th Bus Cycle)
Data Code
A/DQ2 to A/DQ0
Symbol
RL
Function
Read Latency
Value
Description
000
Reserved
001
Reserved
010
Reserved
011
Reserved
100
6
101
7
110
8
111
Reserved
A/DQ3
N/A
N/A
1
Reserved
A/DQ4
SW
Single Write
0
Burst Read & Burst Write
1
Reserved
0
Reserved
1
Rising Edge
A/DQ5
VE
Valid Clock Edge
A/DQ6
RP
Reset to Asynchronous
1
Reserved
A/DQ7
WC
/WE Control
0
/WE Pulse Control
1
Reserved
A/DQ21 to A/DQ8
−
−
1
Reserved
DQ31 to DQ22
−
−
1
Reserved
4. 1. 2 Mode Register Setting/Reading
Select whether to set the mode register or read the set contents of the register by this item.
If 1 is input to A/DQ0 in the 4th cycle, the mode register setting mode is set. If 0 is input to A/DQ0 in the 4th cycle, the
mode register reading mode is set.
For how to read the mode register, refer to 4.2 Mode Register Reading.
4. 1. 3 Partial refresh Density
The partial refresh area is set by this item. If 00 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that 32M bits
are retained. If 01 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that 16M bits are retained. If 10 are input to
A/DQ1 and A/DQ0 in the 5th cycle, it is set that 64M bits are retained. If 11 are input to A/DQ1 and A/DQ0 in the 5th
cycle, it is set that all bits are not retained.
4. 1. 4 Burst length
The burst length is set by this item. If 010 are input to A/DQ4, A/DQ3, and A/DQ2 in the 5th cycle, the burst length is
set to 8. This product supports only a burst length of 8.
Preliminary Data Sheet M17506EJ1V1DS
25
μPD46128953-X
4. 1. 5 Function mode
The burst read mode is set by this item. If 0 is input to A/DQ5 in the 5th cycle, the burst mode is set.
Be sure to input 0 to A/DQ5.
4. 1. 6 Driver strength
The output driver strength is set by this item. If 00 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver
strength is set to Strong. If 11 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver strength is set to Middle.
If 10 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver strength is set to Weak.
4. 1. 7 Read Latency
The read latency count is set by this item. If 100 are input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read
latency is set to 6. If 101 are input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read latency is set to 7. If 110 are
input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read latency is set to 8. Write latency is automatically set RL-1.
4. 1. 8 Single Write
The write mode is set by this item, if 0 is input to A/DQ4 in the 6th cycle, the write mode is set to burst write.
Be sure to input 0 to A/DQ4.
4. 1. 9 Valid Clock Edge
The valid clock edge (Rising edge or Falling edge) is set in the burst mode. If 1 is input to A/DQ5 in the 6th cycle,
rising edge is set to valid clock edge.
4. 1. 10 Reset to Asynchronous
This function is not available now and reserved for future function. Be sure to input 1 to A/DQ6.
4. 1. 11 /WE control
The input timing of /WE is set by this item. If 0 is input to A/DQ7 in the 6th cycle, the input timing of /WE is set to be
the same as the timing of loading an address (/WE = LOW while /ADV = LOW). Refer to 5.3 Loading Command
(read/write).
Be sure to input 0 to A/DQ7.
4. 1. 12 Setting of unused bits
Some of the undefined bits are used to enter a test mode that is not disclosed. Therefore, be sure to input 1 to the
undefined bits (A/DQ21 to A/DQ1 and DQ31 to DQ22 in the 4th cycle, A/DQ21 to A/DQ8 and DQ31 to DQ22 in the 5th
cycle, and A/DQ3, A/DQ21 to A/DQ8, and DQ31 to DQ22 in the 6th cycle).
26
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
4. 2 Mode Register Reading
If 0 is set to A/DQ0 in the 4th cycle after reading the most significant address (3FFFFFH) – two consecutive cycles for
writing any data, it is possible to read current setting value of code 2 in the 5th cycle and current setting value of code 3 in
the 6th cycle
Table 4-5. Mode Register Settings
Cycle
Operation
Address
Data
1st cycle
Read
3FFFFFH
Don’t care
2nd cycle
Write
3FFFFFH
Don’t care
3rd cycle
Write
3FFFFFH
Don’t care
4th cycle
Write
3FFFFFH
Code 1 (A/DQ0 = 0)
5th cycle
Read
3FFFFFH
Code 2
6th cycle
Read
3FFFFFH
Code 3
Codes 1 to 3 are written to the register. The register has a function to latch an address and data necessary for
instruction execution, and does not occupy the memory.
For the timing chart and flowchart, refer to Figure 8-3. Mode Register Read Timing Chart and Figure 8-4. Mode
Register Read Flowchart.
4. 2. 1 Cautions for Setting Mode Register
When the mode register is set, the status of the internal counter is identified by the toggle operation of /CE1 and /OE.
When setting the mode register, therefore, perform a toggle operation of /CE1 in each cycle (one read cycle, three write
cycles, and two mode register read cycles). In the 1st bus cycle (read cycle) and 5th and 6th bus cycles, perform a
toggle operation of /OE in the same manner as /CE1. If an illegal address or data is written or if the codes are written in
an incorrect sequence, reading the mode register fails and the mode register is not read correctly.
If the most significant address (3FFFFFH) is read (in the 1st bus cycle), written (2nd bus cycle), and then written (3rd
bus cycle), a sequence of setting/reading the mode register is started. Therefore, setting of the mode register cannot be
stopped after the 4th bus cycle. If the normal sequence is executed up to the 3rd bus cycle, setting of the mode register
cannot be stopped until the 6th bus cycle is completed.
4. 2. 2 Data read from mode register
If reading the mode register is started, the contents of currently set code 2 (partial refresh density, burst length, function
mode, and driver strength) can be read in the 5th bus cycle. In the 6th bus cycle, the contents of currently set code 3
(read latency, single write, valid clock edge, reset to asynchronous, and /WE control) can be read. If the mode register is
read before it is set, any (undefined) data is output.
Set or read the mode register in compliance with the AC specifications in Table 4-6.
Preliminary Data Sheet M17506EJ1V1DS
27
μPD46128953-X
Table 4-6. AC Specification of Mode Register Setting / Reading
Item
Symbol
-E12X, -E15X
MIN.
MAX.
10000
Unit
Specification of Mode Register Setting / Reading
Cycle time
tMSC
90
ns
Address setup time to /ADV = HIGH
tAS
6
ns
Address hold time to /ADV = HIGH
tAH
1
ns
/CE1 setup time to /ADV = HIGH
tCS
6
ns
Address setup time to /OE = LOW
tAOSM
0
ns
/ADV Low pulse width
tVPL
6
ns
/OE to output in low impedance
tOLZM
5
ns
/OE to output valid
tACM
30
ns
/CE1 to output in high impedance
tCHZM
10
ns
/OE to output in high impedance
tOHZM
10
ns
Write data setup time to /WE = HIGH
tDW
20
ns
Write data hold time to /WE = HIGH
tDH
0
ns
/CE1 HIGH pulse width
tCP
10
ns
/WE LOW pulse width
tWP
50
ns
/OE LOW pulse width
tOVL
50
ns
For the timing chart and flowchart, refer to Figure 8-1. Mode Register Setting Timing Chart, Figure 8-2. Mode
Register Setting Flowchart, Figure 8-3. Mode Register Read Timing Chart and Figure 8-4. Mode Register Read
Flowchart.
28
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
5. Address, /OE, /WE, DM control
5. 1 Relation of address inputs and /OE control
This product uses only one pin to input an address and input/output DQ. Consequently, a bus fight may occur between
an address input from the controller and data output from the memory and, therefore, the timing must be considered.
Data is output after specified tOLZ from the first rising edge of CLK when /OE has changes its level from HIGH to LOW.
Therefore, complete inputting an address from the controller before the first rising edge of CLK when /OE has changed
its level from HIGH to LOW.
Figure 5-1. Address inputs and /OE Timing
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK (Input)
/ADV (Input)
tAH
/CE1 (Input)
tOEH tOES
tOLZ
/OE (Input)
tACH
A/DQ0 to A/DQ21 (Input/Output)
Add
tAOS
High-Z
Q0
Q1
Q2
Q0
Q1
Q2
Read Latency = 6
DQ22 to DQ31 (Output)
High-Z
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
Preliminary Data Sheet M17506EJ1V1DS
29
μPD46128953-X
5. 2 Address Latching
An address is latched at the first rising edge of CLK when /ADV changes its level from HIGH to LOW while /CE1 =
LOW. An address can be latched and a read or write operation can be started as soon as the memory has changed its
status from standby (/CE1 = HIGH) to active (/CE1 = LOW). If the period in which /ADV = LOW while /CE1 = LOW
extends over two or more CLK as shown in Figure 5-4, an address is latched at the first rising edge of CLK after /ADV =
LOW.
Figure 5-2. Address Latched Timing 1
T0
T1
T2
CLK (Input)
tCHV tCSV tCHV
/ADV (Input)
tAH
tCES
/CE1 (Input)
tACS
A/DQ0 to A/DQ21 (Input)
tACH
Add
Address Latched
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
30
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
Figure 5-3. Address Latched Timing 2
T0
T1
T2
CLK (Input)
tCHV tCSV tCHV
/ADV (Input)
tAH
tCES
/CE1 (Input)
tACS
A/DQ0 to A/DQ21 (Input)
tACH
Add
Address Latched
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
Figure 5-4. Address Latched Timing 3
T0
T1
T2
CLK (Input)
tCHV tCSV
tCHV
/ADV (Input)
tAH
tCES
/CE1 (Input)
tACS
A/DQ0 to A/DQ21 (Input)
tACH
Add
Address Latched
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
Preliminary Data Sheet M17506EJ1V1DS
31
μPD46128953-X
5. 3 Read / Write Command Loading
A command (read/write) is loaded in the same timing as an address (refer to 6.2 Address Latching). If /WE = HIGH
at that time, a read operation is started; if /WE = LOW, a write operation is started. Figure 5-5 shows a read operation
and Figure 5-6 shows a write operation. If /WE = LOW in the cycle next to that in which an address is loaded as shown in
Figure 5-7, a write operation is not recognized. The operation in Figure 5-7 is a read operation.
Figure 5-5. Command Loading Timing 1
T0
T1
T2
CLK (Input)
tCHV tCSV tCHV
/ADV (Input)
tCES
/CE1 (Input)
/OE (Input)
H
tWES tWEH
/WE (Input)
Command Input
Remarks 1.
2.
32
Figure 5-5 shows a read operation
Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
Figure 5-6. Command Loading Timing 2
T0
T1
T2
CLK (Input)
tCHV tCSV tCHV
/ADV (Input)
tCES
/CE1 (Input)
/OE (Input)
H
tWES tWEH
/WE (Input)
Command Input
Remarks 1.
2.
Figure 5-6 shows a write operation
Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
Figure 5-7. Command Loading Timing 3
T0
T1
T2
CLK (Input)
tCHV tCSV
tCHV
/ADV (Input)
tCES
/CE1 (Input)
/OE (Input)
H
tWES tWEH tWES tWEH
/WE (Input)
Command Input
Remarks 1.
2.
Figure 5-7 shows a read operation
Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
Preliminary Data Sheet M17506EJ1V1DS
33
μPD46128953-X
5. 4 /OE control during burst read operation
5. 4. 1 /OE HIGH to LOW during burst read operation
The output is controlled depending on the status of /OE (HIGH or LOW) when CLK rises. As shown in Figure 5-8, if
/OE is made from LOW to HIGH before the rising edge of CLK in T8 during burst read, the read data (Q4) output from the
rising edge of CLK in T7 is output. However, the read data that is output from the rising edge of CLK in T8 is not output.
Figure 5-8. /OE HIGH to LOW during burst read operation Timing
T4
T5
T6
T7
T8
T9
T10
CLK (Input)
/ADV (Input)
H
/CE1 (Input)
L
tOEH tOES
/OE (Input)
tAC
tOH
tHZ
A/DQ0 to A/DQ21 (Output)
Q0
Q1
Q2
Q3
Q4
DQ22 to DQ31 (Output)
Q0
Q1
Q2
Q3
Q4
High-Z
High-Z
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
34
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
5. 4. 2 /OE LOW to HIGH during burst read operation
The output is controlled depending on the status of /OE (HIGH or LOW) when CLK rises. As shown in Figure 5-9, if
/OE is made from HIGH to LOW before the rising edge of CLK in T8 during burst read, the read data (Q5) output from the
rising edge of CLK in T8 is output. Because /OE = HIGH until cycle T7, the read data (Q0, Q1, Q2, Q3, and Q4) that
should be output when /OE = LOW are not output, but go into a high impedance state.
Figure 5-9. /OE LOW to HIGH during burst read operation Timing
T4
T5
T6
T7
T8
T9
T10
CLK (Input)
/ADV (Input)
H
/CE1 (Input)
L
tOEH tOES
/OE (Input)
tOAC
tOLZ
High-Z
A/DQ0 to A/DQ21 (Output)
Q0
DQ22 to DQ31 (Output)
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
High-Z
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
Preliminary Data Sheet M17506EJ1V1DS
35
μPD46128953-X
5. 5 Write data mask signal (DM) control
This section explains how to control the write data mask signal (DM). DM is a signal that masks input data.
Data mask is valid only in the write cycle. Therefore, data can be masked in the burst write cycle but cannot in the
burst read cycle.
The write data mask signal (DM) controls byte unit with one pin.
- DM0 controls A/DQ7 to A/DQ0.
- DM1 controls A/DQ15 to A/DQ8.
- DM2 controls A/DQ21 to A/DQ16 and DQ23 to DQ22.
- DM3 controls DQ31 to DQ24.
5. 5. 1 Controlling write data mask signal (DM) in write cycle
As shown in Figure 5-10, the corresponding write data is masked when the write data mask signal (DM) is HIGH.
Figure 5-10. Command Loading Timing 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK (Input)
/ADV (Inout)
/WE (Input)
tBDH tBDS tBDH tBDS
DM (Input)
A/DQ0 to A/DQ21 (Input)
DQ22 to DQ31 (Input)
High-Z
High-Z
Add
D0
Mask
D2
Mask
D4
D0
Mask
D2
Mask
D4
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification
36
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
5. 5. 2 Write data mask (DM) truth table
Table 5-1. Write data mask (DM) truth table
Function
DM
DM0
DM1
All A/DQ and DQ write permission
L
All A/DQ and DQ write prohibition
H
DM2
DM3
A/DQ7 to A/DQ0 write permission
L
×
×
×
A/DQ15 to A/DQ8 write permission
×
L
×
×
DQ23 to DQ22, A/DQ21 to A/DQ16 write permission
×
×
L
×
DQ31 to DQ24 write permission
×
×
×
L
A/DQ7 to A/DQ0 write prohibition
H
×
×
×
A/DQ15 to A/DQ8 write prohibition
×
H
×
×
DQ23 to DQ22, A/DQ21 to A/DQ16 write prohibition
×
×
H
×
DQ31 to DQ24 write prohibition
×
×
×
H
Remark
H: VIH, L: VIL, ×: VIH or VIL
Preliminary Data Sheet M17506EJ1V1DS
37
μPD46128953-X
6. Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Condition
Rating
VDD
Input / Output Supply voltage
VDDQ
Unit
−0.5
Note
to +2.5
V
−0.5
Note
to +2.5
V
−0.5
Note
to +2.5
V
Input / Output voltage
VT
Operating ambient temperature
TA
−25 to +85
°C
Storage temperature
Tstg
−55 to +125
°C
Note –1.0 V (MIN.) (Pulse width: 30 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VDD
Condition
Note1
Note1
MIN.
MAX.
Unit
1.7
2.0
V
1.7
2.0
V
VDDQ +0.3
V
0.2VDDQ
V
+85
°C
Input / Output Supply voltage
VDDQ
Input HIGH voltage
VIH
0.8VDDQ
Input LOW voltage
VIL
Note2
Operating ambient temperature
TA
Notes 1.
2.
−0.3
−25
Use same voltage condition (VDD = VDDQ).
−0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
VIN = 0 V, Input pins
8
pF
Output capacitance
COUT
VOUT = 0 V, /WAIT pin
8
pF
Input / Output capacitance
CDQ
VDQ = 0 V, A/DQ, DQ pins
10
pF
Remarks 1.
2.
38
VIN : input voltage, VOUT : output voltage, VDQ : input / output voltage
These parameters are not 100% tested.
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
Density of
MIN.
TYP.
MAX.
Unit
data hold
Input leakage current
ILI
VIN = 0 V to VDDQ
−1.0
+1.0
μA
A/DQ, DQ, /WAIT
ILO
VDQ , VOUT = 0 V to VDDQ, /CE1 = VIH
−1.0
+1.0
μA
/CE1 = VIL, Burst length = 1, frequency = 83 MHz
60
mA
IDQ = 0 mA
frequency = 66 MHz
55
/CE1 = VIL, Burst length = 8, frequency = 83MHz
40
IDQ = 0 mA
35
leakage current
Operating supply current
Operating supply
or /WE = VIL or /OE = VIH
ICCA1
ICCA2
Burst current
Standby supply current
ISB1
frequency = 66MHz
/CE1 ≥ VDDQ−0.2 V,
128M bits
T.B.D.
/CE1 ≥ VDDQ−0.2 V,
64M bits
T.B.D.
CE2 ≤ 0.2 V
32M bits
T.B.D.
16M bits
T.B.D.
0M bit
T.B.D.
mA
μA
CE2 ≥ VDDQ−0.2 V
ISB2
Output HIGH voltage
VOH
IOH = −0.5 mA
Output LOW voltage
VOL
IOL = 1 mA
0.8VDDQ
V
0.2VDDQ
V
Remark VIN: Input voltage, VOUT: output voltage, VDQ: Input / Output voltage
Preliminary Data Sheet M17506EJ1V1DS
39
μPD46128953-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 3 ns)
VDDQ
0.8VDDQ
0.2VDDQ
VSSQ
VDDQ / 2
Test points
VDDQ / 2
VDDQ / 2
Test Points
VDDQ / 2
3 ns
Output Waveform
Output Load
30 pF
Remark CL includes capacitance of the probe and jig, and stray capacitance.
40
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
AC Specifications
(1/2)
Parameter
Symbol
-E12X
MIN.
-E15X
MAX.
MIN.
Unit
Note
MAX.
Clock Specifications
Cycle frequency
tCLK
83
66
CLK HIGH width
tCH
3
3
ns
CLK LOW width
tCL
3
3
ns
CLK rise / fall time
tCHCL
3
3
MHz
ns
Address Latching Specifications
Address hold time from /ADV = HIGH
tAH
1
1
ns
Address setup time to CLK
tACS
5
5
ns
Address hold time to CLK
tACH
7
7
ns
/ADV = LOW setup time to CLK
tCSV
5
5
ns
/ADV = LOW hold time from CLK
tCHV
1
1
ns
Address setup time to /OE = LOW
tAOS
0
0
ns
/ADV = LOW pulse width
tVPL
6
6
ns
/ADV = LOW to next /ADV = LOW
tCVCV
10
10
μs
1
Control Signals Specifications
/CE1 setup time to CLK
tCES
5
5
ns
/CE1 hold time to CLK
tCEH
1
1
ns
/OE setup time to CLK
tOES
5
5
ns
/OE hold time to CLK
tOEH
1
1
ns
/WE setup time to CLK
tWES
5
5
ns
/WE hold time to CLK
tWEH
1
1
ns
Note 1. tCVCV (MAX.) is applied while /CE1 is being hold at LOW.
Preliminary Data Sheet M17506EJ1V1DS
41
μPD46128953-X
(2/2)
Parameter
Symbol
-E12X
MIN.
-E15X
MAX.
MIN.
Unit
Note
ns
1, 3
ns
1
ns
2
MAX.
Read Specifications
Burst access time
tAC
Output data hold
tOH
CLK to output in high impedance
tHZ
8
2
8
2
7
7
Write Specifications
Write data valid of CLK
tWDS
5
5
ns
Write data hold of CLK
tWDH
1
1
ns
DM setup time to CLK
tBDS
5
5
ns
DM hold time to CLK
tBDH
1
1
ns
/WAIT Specifications
/WAIT LOW output time from CLK
tCEWA
8
8
ns
1
/WAIT HIGH output time from CLK
tCLWA
8
8
ns
1
/WAIT in high impedance from CLK
tCWHZ
10
10
ns
2
ns
2
ns
1, 3, 4
Others
/OE to output in low impedance
tOLZ
Output time from /OE HIGH to LOW
tOAC
1
1
9
9
during burst read
Notes 1.
42
Output load: 30 pF
2.
Output load: 5 pF
3.
In case output driver size is ‘Middle’
4.
For tOAC, refer to Figure 5-9. /OE HIGH to LOW during burst read operation timing.
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
7. Timing Charts
Figure 7-1. Burst Read Cycle Timing Chart (/CE1 = LOW Consecutive Access)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T0
T1
tCLK
CLK (Input)
tCH
tCL
tCHCL
tCVCV
tCHCL
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tAH
tVPL
tAH
tCES
/CE1 (Input)
tOEH tOES
tOLZ
tOEH tOES
tOLZ
tOEH tOES tOLZ
tOEH
tOES
tOEH tOES
/OE (Input)
tWES tWEH
tWEH
tWES
/WE (Input)
tCEWA
tCEWA
tCLWA
High-Z
/WAIT (Output)
Read Latency = 6
tACH
tACS
A/DQ0 to A/DQ21 (Input/Output)
High-Z
tAOS
tAOS
tAC
tAOS
Add
tAC
tOH
tHZ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
tACS
High-Z
tACH
Add
tAOS
High-Z
High-Z
tHZ
DQ22 to DQ31 (Output)
High-Z
High-Z
Remark The above timing chart assumes read latency is set 6.
Preliminary Data Sheet M17506EJ1V1DS
43
μPD46128953-X
Figure 7-2. Burst Read Cycle Timing Chart (/CE1 Toggle Access)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T0
T1
tCLK
CLK (Input)
tCH
tCL
tCHCL
tCVCV
tCHCL
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tAH
tVPL
tAH
tCEH tCES tCEH tCES tCEH tCES
tCES
/CE1 (Input)
tOEH tOES
tOEH
tOLZ
tOES
tOEH tOES
/OE (Input)
tWES tWEH
tWEH
tWES
/WE (Input)
tCEWA
tCWHZ
tCLWA
tCEWA
tCLWA
High-Z
/WAIT (Output)
Read Latency = 6
tACH
tACS
A/DQ0 to A/DQ21 (Input/Output)
High-Z
Add
tAC
tAOS
High-Z
tAC
tOH
tHZ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
tACS
High-Z
tACH
Add
tAOS
High-Z
tHZ
DQ22 to DQ31 (Output)
High-Z
Remark The above timing chart assumes read latency is set 6.
44
Preliminary Data Sheet M17506EJ1V1DS
High-Z
μPD46128953-X
Figure 7-3. Burst Write Cycle Timing Chart (/CE1 = LOW Consecutive Access)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T0
T1
tCLK
CLK (Input)
tCH
tCL
tCVCV
tCHCL
tCHCL
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tAH
tVPL
tAH
tCES
/CE1 (Input)
/OE (Input)
H
tWES tWEH
tWEH
tWES
/WE (Input)
tCEWA
tCEWA
tCLWA
High-Z
/WAIT (Output)
tBDS
tBDH
DM (Input)
Write Latency = 5
High-Z
tWDS tWDH
tACH
tACS
A/DQ0 to A/DQ21 (Input)
Add
tACS
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
tACH
Add
High-Z
High-Z
DQ22 to DQ31 (Input)
High-Z
High-Z
Remark The above timing chart assumes write latency is set 5.
Preliminary Data Sheet M17506EJ1V1DS
45
μPD46128953-X
Figure 7-4. Burst Write Cycle Timing Chart (/CE1 Toggle Access)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T0
T1
tCLK
CLK (Input)
tCH
tCL
tCVCV
tCHCL
tCHCL
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tAH
tVPL
tCES
tAH
tCEH tCES tCEH tCES tCEH tCES
/CE1 (Input)
/OE (Input)
H
tWES tWEH
tWEH
tWES
/WE (Input)
tCEWA
tCWHZ
tCLWA
tCEWA
tCLWA
High-Z
/WAIT (Output)
tBDS
tBDH
DM (Input)
Write Latency = 5
A/DQ0 to A/DQ21 (Input/Output)
tWDS tWDH
tACH
tACS
High-Z
Add
tACS
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
tACH
Add
High-Z
High-Z
DQ22 to DQ31 (Input)
High-Z
Remark The above timing chart assumes write latency is set 5.
46
Preliminary Data Sheet M17506EJ1V1DS
High-Z
μPD46128953-X
Figure 7-5. Burst Read Termination Cycle Timing Chart (/CE1 Controlled)
T0
T1
T2
T3
T4
T5
T6
T7
T0
T1
T2
T3
T4
T5
T6
T7
tCLK
CLK (Input)
tCH
tCL
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tAH
tVPL
tCES
tCEH tCES tCEH
tAH
tCES
/CE1 (Input)
tOEH tOES
tOLZ
tOEH
tOES
tOEH tOES tOLZ
/OE (Input)
tWES tWEH
tWES tWEH
/WE (Input)
tCEWA
tCWHZ
tCLWA
tCEWA
High-Z
/WAIT (Output)
Read Latency = 6
tACS
A/DQ0 to A/DQ21 (Input/Output)
DQ22 to DQ31 (Output)
High-Z
tACH
Add
High-Z
tCLWA
High-Z
tAOS
High-Z
Read Latency = 6
tAC
tHZ
Q0
tACS
High-Z
tACH
Add
Q0
tAOS
High-Z
High-Z
tAC
tAC
tOH
Q0
Q1
Q2
Q0
Q1
Q2
Note Burst Read Termination is available after the first read data output.
Figure 7-5 is the minimum cycle at Burst Read Termination to next operation.
Remark The above timing chart assumes read latency is set 6.
Preliminary Data Sheet M17506EJ1V1DS
47
μPD46128953-X
Figure 7-6. Burst Write Termination Cycle Timing Chart (/CE1 Controlled)
T0
T1
T2
T3
T4
T5
T6
T7
T0
T1
T2
T3
T4
T5
T6
tCLK
CLK (Input)
tCH
tCL
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tAH
tVPL
tCES
tCEH tCES tCEH
tAH
tCES
/CE1 (Input)
/OE (Input)
H
tWES tWEH
tWES tWEH
/WE (Input)
tCEWA
tCWHZ
tCLWA
High-Z
/WAIT (Output)
tCEWA
Write Latency = 5
tACS
A/DQ0 to A/DQ21 (Input)
High-Z
Write Latency = 5
tWDS tWDH
High-Z
High-Z
DQ22 to DQ31 (Input)
DM0 to DM3 (Input)
tACH
Add
D0
tACS
High-Z
tACH
Add
D0
L
Note Burst Write Termination is available after the first write data input.
Figure 7-6 is the minimum cycle at Burst Write Termination to next operation.
Remark The above timing chart assumes write latency is set 5.
48
tCLWA
High-Z
Preliminary Data Sheet M17506EJ1V1DS
tWDS tWDH
High-Z
High-Z
D0
D1
D0
D1
6th Cycle
5th Cycle
4th Cycle
3rd Cycle
2nd Cycle
1st Cycle
H
CLK (Input)
L
tVPL
tVPL
tVPL
tVPL
tVPL
tVPL
/ADV (Input)
tCP
tCS
tCS
tCP
tMSC
tCS
tCP
tMSC
Preliminary Data Sheet M17506EJ1V1DS
/CE1 (Input)
tCS
tCP
tMSC
tCS
tCP
tMSC
tCS
tCP
tMSC
tMSC
tCHZM
8. Mode Register Setting/Read Timing
8. 1 Mode Register Setting Timing
Figure 8-1. Mode Register Setting Timing Chart
tOVL
/OE (Input)
tWP
/WE (Input)
tWP
tWHP
tWP
tWHP
tWP
tWHP
tWP
tWHP
tWHP
tACM
tOLZM
tOHZM
tAOSM
tAS tAH
A/DQ0 to A/DQ21 (Input/Output)
Note
DQ22 to DQ31 (Input/Output)
tAS
Don't
Care
Don't
Care
tAH
Note
tDW
tDH
Don't
Care
Don't
Care
tAS
tAH
Note
tDW
tDH
Don't
Care
Don't
Care
tAS
tAH
Note
tDW
tDH
Code1
tAS
tAH
Note
Code1
Remark When setting the mode register, fix CLK to HIGH or LOW. If CLK is toggled, the mode register is not correctly set.
When the mode register is set, DM0 to DM3 are don’t care (HIGH or LOW).
tDH
Code2
Code2
tAS
tAH
Note
tDW
tDH
Code3
Code3
49
μPD46128953-X
Note Address → All “1” (3FFFFFH)
tDW
μPD46128953-X
8. 2 Mode Register Setting Flow Chart
Figure 8-2. Mode Register Setting Flow Chart
Start
No
Read Operation
Address = 3FFFFFH
toggled the
/CE1 and /OE
Yes
No
Write Operation
Address = 3FFFFFH
toggled the /CE1
Yes
No
Write Operation
Address = 3FFFFFH
toggled the /CE1
Yes
Write Operation
Address = 3FFFFFH
toggled the /CE1
Mode register setting exit
No
Yes
Write Data = Code1 Note 1
(A/DQ = 1)
No
Yes
Write Operation
Address = 3FFFFFH
toggled the /CE1
No
Yes
Write Data = Code2 Note 2
No
Yes
Write Operation
Address = 3FFFFFH
toggled the /CE1
No
Yes
No
Write Data = Code3 Note 3
Yes
End
Notes 1.
Refer to Table 4-2.
2.
Refer to Table 4-3.
3.
Refer to Table 4-4.
50
Preliminary Data Sheet M17506EJ1V1DS
Re-setup the mode register
8. 3 Mode Register Read Timing
Figure 8-3. Mode Register Read Timing Chart
6th Cycle
5th Cycle
4th Cycle
3rd Cycle
2nd Cycle
1st Cycle
H
CLK (Input)
L
tVPL
tVPL
tVPL
tVPL
tVPL
tVPL
/ADV (Input)
tCS
tCP
tCS
tCP
tMSC
tCS
tCP
tMSC
Preliminary Data Sheet M17506EJ1V1DS
/CE1 (Input)
tCS
tCP
tMSC
tCS
tCP
tMSC
tCS
tCP
tMSC
tMSC
tCHZM
tOVL
tOVL
tOVL
/OE (Input)
tWP
/WE (Input)
tWP
tWHP
tWP
tWHP
tACM
tACM
tOLZM
tOHZM
tAOSM
tAS tAH
A/DQ0 to A/DQ21 (Input/Output)
Note
DQ22 to DQ31 (Input/Output)
tACM
tOLZM
tAOSM
tAS
Don't
Care
Don't
Care
tOLZM
tAH
Note
tDW
tDH
Don't
Care
Don't
Care
tAS
tAH
Note
tDW
tDH
Don't
Care
Don't
Care
tAS
tAH
Note
tDW
tDH
Code1
tDW
Note
Code2
Code1
Remark When setting the mode register, fix CLK to HIGH or LOW. If CLK is toggled, the mode register is not correctly set.
tDH
Code2
tAS
tAH
Note
tDW
tDH
Code3
Code3
51
μPD46128953-X
Note Address → All “1” (3FFFFFH)
When the mode register is set, DM0 to DM3 are don’t care (HIGH or LOW).
tAOSM
tAS tAH
μPD46128953-X
8. 4 Mode Register Read Flow Chart
Figure 8-4. Mode Register Read Flow Chart
Start
No
Read Operation
Address = 3FFFFFH
toggled the
/CE1 and /OE
Yes
No
Write Operation
Address = 3FFFFFH
toggled the /CE1
Yes
No
Write Operation
Address = 3FFFFFH
toggled the /CE1
Yes
Write Operation
Address = 3FFFFFH
toggled the /CE1
Mode register setting exit
No
Yes
Write Data = Code1 Note 1
(A/DQ = 0)
No
Yes
Read Operation
Address = 3FFFFFH
toggled the
/CE1 and /OE
No
Yes
Read Data = Code2 Note 2
Read Operation
Address = 3FFFFFH
toggled the
/CE1 and /OE
No
Yes
Read Data = Code3 Note 3
End
Notes 1.
Refer to Table 4-2.
2.
Refer to Table 4-3.
3.
Refer to Table 4-4.
52
Preliminary Data Sheet M17506EJ1V1DS
Impossible Mode Register Read
μPD46128953-X
9. Standby Mode Timing Charts
Figure 9-1. Standby Mode 2 (data hold: 64M bits / 32M bits / 16M bits) Entry / Exit Timing Chart
CLK (Input)
tCE2S
CE2 (Input)
tCES
tCES
tCHML
tMHCL1
/CE1 (Input)
Standby
mode 1
Standby mode 2
(Data hold: 64M bits / 32M bits / 16M bits)
Figure 9-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart
CLK (Input)
tCE2S
CE2 (Input)
tCES
tCES
tCHML
tMHCL2
/CE1 (Input)
Standby
mode 1
Standby mode 2
(Data not held)
Standby Mode 2 Entry / Exit Timing
Parameter
Symbol
MIN.
MAX.
Unit
Note
Standby mode 2 entry /CE1 HIGH to CE2 LOW
tCHML
0
ns
Standby mode 2 exit to normal operation CE2 HIGH to /CE1 LOW
tMHCL1
30
ns
1
Standby mode 2 exit to normal operation CE2 HIGH to /CE1 LOW
tMHCL2
300
μs
2
/CE1 setup time to CLK
tCES
5
ns
CE2 hold time to CLK
tCE2S
1
ns
Notes 1.
This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 64M bits / 32M bits /
16M bits).
2.
This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
Preliminary Data Sheet M17506EJ1V1DS
53
μPD46128953-X
10. Package Drawing
The following is a package drawing of package sample.
127-PIN PLASTIC FBGA (13.0x11.5)
D
ZD
ZE
W S A
A
14
13
12
11
10
9
8
7
6
5
4
3
2
1
B
E
W S B
x4
INDEX MARK
PNM L K J HG F E D C B A
v
A
y1
A2
S
S
y
e
S
b
x
A1
M
S AB
This package drawing is a preliminary version. It may be changed in the future.
54
Preliminary Data Sheet M17506EJ1V1DS
ITEM
D
(UNIT :mm)
MILLIMETERS
13.00
E
11.50
v
0.15
w
e
0.20
0.80
A
A1
A2
1.50
0.22
1.28
b
x
0.40
0.08
y
y1
0.10
0.20
ZD
1.30
ZE
0.55
μPD46128953-X
11. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD46128953-X.
Type of Surface Mount Device
μPD46128953F1-EB1: 127-pin PLASTIC FBGA (13.0 x 11.5)
Preliminary Data Sheet M17506EJ1V1DS
55
μPD46128953-X
[ MEMO ]
56
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
[ MEMO ]
Preliminary Data Sheet M17506EJ1V1DS
57
μPD46128953-X
[ MEMO ]
58
Preliminary Data Sheet M17506EJ1V1DS
μPD46128953-X
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Preliminary Data Sheet M17506EJ1V1DS
59
μPD46128953-X
• The information in this document is current as of September, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1