PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4632312A-X 32M-BIT CMOS MOBILE SPECIFIED RAM 2M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD4632312A-X is a high speed, low power, 33,554,432 bits (2,097,152 words by 16 bits) CMOS Mobile Specified RAM featuring Low Power Static RAM compatible function and pin configuration. The µPD4632312A-X is fabricated with advanced CMOS technology using one-transistor memory cell. The µPD4632312A-X is packed in 48-pin TAPE FBGA. Features • 2,097,152 words by 16 bits organization • Fast access time: 60, 65, 75, 85 ns (MAX.) • Fast page access time: 18, 25, 30 ns (MAX.) • Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15) • Low voltage operation: 2.7 to 3.1 V (-B60X, -B65X) 2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X, -BE85X) • Operating ambient temperature: TA = –25 to +85 °C • Output Enable input for easy application • Chip Enable input: /CS pin • Standby Mode input: MODE pin • Standby Mode1: Normal standby (Memory cell data hold valid) • Standby Mode2: Density of memory cell data hold is variable µPD4632312A Access Operating supply Operating time voltage ambient ns (MAX.) V -B60X Note, -B65X -BE75X Note , -BE85X Note Supply current At standby µA (MAX.) At operating temperature mA (MAX.) Chip I/O °C 60, 65 2.7 to 3.1 – –25 to +85 75, 85 2.7 to 3.1 1.65 to 2.1 Density of data hold 32M bits 16M bits 8M bits 4M bits 50 100 70 60 50 0M bit 30 45 Note Under development The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. Document No. M15874EJ5V0DS00 (5th edition) Date Published January 2003 NS CP (K) Printed in Japan The mark ★ shows major revised points. 2001 µPD4632312A-X Ordering Information Part number µPD4632312AF9-B60X-BC2 Package Note µPD4632312AF9-B65X-BC2 48-pin TAPE FBGA (8 x 6) Access time Operating supply voltage Operating ns (MAX.) V temperature 60 I/O °C 2.7 to 3.1 – –25 to +85 2.7 to 3.1 1.65 to 2.1 65 µPD4632312AF9-BE75X-BC2 Note 75 µPD4632312AF9-BE85X-BC2 85 Note Note Under development 2 Chip Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X Pin Configurations /xxx indicates active low signal. 48-pin TAPE FBGA (8 x 6) [ µPD4632312AF9-B60X-BC2 ] [ µPD4632312AF9-B65X-BC2 ] Top View Bottom View A B C D E F G H 1 2 3 4 5 6 6 5 4 3 2 1 1 2 3 4 5 6 6 5 4 3 2 1 A /LB /OE A0 A1 A2 MODE A MODE A2 A1 A0 /OE /LB B I/O8 /UB A3 A4 /CS I/O0 B I/O0 /CS A4 A3 /UB I/O8 C I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O2 I/O1 A6 A5 I/O10 I/O9 D VCC I/O3 A7 A17 I/O11 GND D GND I/O11 A17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 GND E GND I/O4 A16 NC I/O12 VCC I/O6 I/O5 A15 A14 I/O13 I/O14 F I/O14 I/O13 A14 A15 I/O5 I/O6 F G I/O15 A19 A12 A13 /WE I/O7 G I/O7 /WE A13 A12 A19 I/O15 A20 H A20 A11 A10 A9 A8 A18 H A18 A8 A9 A10 A11 /OE : Output enable I/O0 to I/O15 : Data inputs / outputs /LB, /UB : Byte data select /CS : Chip select VCC : Power supply MODE : Standby mode GND : Ground /WE : Write enable NC : No connection A0 to A20 : Address inputs Note Note Some signals can be applied because this pin is not internally connected. Remark Refer to Package Drawing for the index mark. Preliminary Data Sheet M15874EJ5V0DS 3 µPD4632312A-X 48-pin TAPE FBGA (8 x 6) [ µPD4632312AF9-BE75X-BC2 ] [ µPD4632312AF9-BE85X-BC2 ] Top View Bottom View A B C D E F G H 1 2 3 1 2 3 4 A /LB /OE A0 B I/O8 /UB A3 4 5 6 6 5 4 6 5 6 A1 A2 MODE A A4 /CS I/O0 B 2 1 5 4 3 2 1 MODE A2 A1 A0 /OE /LB I/O0 /CS A4 A3 /UB I/O8 C I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O2 I/O1 A6 A5 I/O10 I/O9 D GND I/O11 A17 A7 I/O3 VCC D VCC I/O3 A7 A17 I/O11 GND E VCCQ I/O12 NC A16 I/O4 GND E GND I/O4 A16 NC I/O12 VCCQ F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O6 I/O5 A15 A14 I/O13 I/O14 G I/O15 A19 A12 A13 /WE I/O7 G I/O7 /WE A13 A12 A19 I/O15 H A18 A8 A9 A10 A11 A20 H A20 A11 A10 A9 A8 A18 /OE : Output enable I/O0 to I/O15 : Data inputs / outputs /LB, /UB : Byte data select /CS : Chip Select VCC : Power supply MODE : Standby mode VCCQ : Input / Output power supply /WE : Write enable GND : Ground NC : No connection A0 to A20 : Address inputs Note Note Some signals can be applied because this pin is not internally connected. Remark Refer to Package Drawing for the index mark. 4 3 Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X Block Diagram Standby mode control VCC Refresh control VCCQ GND Memory cell array 33,554,432 bits Refresh counter Row decoder A0 A20 Address buffer I/O0 to I/O7 I/O8 to I/O15 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CS MODE /LB /UB /WE /OE Remark VCCQ is the input / output power supply for -BE75X and -BE85X. Preliminary Data Sheet M15874EJ5V0DS 5 µPD4632312A-X Truth Table /CS MODE /OE /WE /LB /UB Mode I/O Supply I/O0 to I/O7 I/O8 to I/O15 current ISB1 H H × × × × Not selected (Standby Mode 1) High-Z High-Z × H × × H H Not selected (Standby Mode 1) High-Z High-Z × L × × × × Not selected (Standby Mode 2) Note High-Z High-Z ISB2 L H H H × × Output disable High-Z High-Z ICCA L H L L Word read DOUT DOUT L H Lower byte read DOUT High-Z H L Upper byte read High-Z DOUT L L Word write DIN DIN L H Lower byte write DIN High-Z H L Upper byte write High-Z DIN H L Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Standby Mode Status Transition). Remark ×: VIH or VIL, H: VIH, L: VIL 6 Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X CONTENTS 1. Initialization .................................................................................................................................................................... 8 2. Partial Refresh ............................................................................................................................................................... 9 2.1 Standby Mode........................................................................................................................................................... 9 2.2 Density Switching...................................................................................................................................................... 9 2.3 Standby Mode Status Transition............................................................................................................................... 9 2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................ 10 3. Page Read Operation .................................................................................................................................................. 11 3.1 Features of Page Read Operation .......................................................................................................................... 11 3.2 Page Length ........................................................................................................................................................... 11 3.3 Page-Corresponding Addresses............................................................................................................................. 11 3.4 Page Start Address................................................................................................................................................. 11 3.5 Page Direction ........................................................................................................................................................ 11 3.6 Interrupt during Page Read Operation.................................................................................................................... 11 3.7 When page read is not used................................................................................................................................... 11 4. Mode Register Settings................................................................................................................................................ 12 4.1 Mode Register Setting Method ............................................................................................................................... 12 4.2 Cautions for Setting Mode Register ........................................................................................................................ 13 5. Electrical Specifications ............................................................................................................................................... 14 6. Timing Charts............................................................................................................................................................... 19 7. Package Drawing ......................................................................................................................................................... 29 8. Recommended Soldering Conditions .......................................................................................................................... 30 9. Revision History ........................................................................................................................................................... 31 Preliminary Data Sheet M15874EJ5V0DS 7 µPD4632312A-X 1. Initialization Initialize the µPD4632312A-X at power application using the following sequence to stabilize internal circuits. (1) Following power application, make MODE high level after fixing MODE to low level for the period of tVHMH. Make /CS high level before making MODE high level. (2) /CS and MODE are fixed to high level for the period of tMHCL. Normal operation is possible after the completion of initialization. Figure1-1. Initialization Timing Chart Normal Operation Initialization /CS (Input) tCHMH tMHCL tVHMH MODE (Input) VCC VCC (MIN.) Cautions 1. Make MODE low level when starting the power supply. 2. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VCC (MIN.)). Initialization Timing Parameter Symbol MIN. Power application to MODE low level hold tVHMH 50 µs /CS high level to MODE high level tCHMH 0 ns Following power application MODE high level hold to /CS low level tMHCL 200 µs 8 Preliminary Data Sheet M15874EJ5V0DS MAX. Unit µPD4632312A-X 2. Partial Refresh 2.1 Standby Mode In addition to the regular standby mode (Standby Mode 1) with a 32M bits density, Standby Mode 2, which performs partial refresh, is also provided. 2.2 Density Switching In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit. The density for performing refresh can be set with the mode register. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. (For how to perform mode register settings, refer to section 4. Mode Register Settings.) 2.3 Standby Mode Status Transition In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are high level. In Standby Mode 2, MODE is low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits, 8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from Standby Mode 2. For the timing charts, refer to Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart, Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart. Preliminary Data Sheet M15874EJ5V0DS 9 µPD4632312A-X Figure 2-1. Standby Mode State Machine Power On Initialization Initial State /CS = VIL MODE = VIH Active MODE = VIL MODE = VIL MODE = VIH, /CS = VIH or /LB, /UB = VIH /CS = VIL, MODE = VIH Standby Mode 1 /CS = VIL, MODE = VIH MODE = VIL Standby Mode 2 (16M bits / 8M bits / 4M bits) MODE = VIL Standby Mode 2 (Data not held) 2.4 Addresses for Which Partial Refresh Is Supported Data hold density 10 Correspondence address 16M bits 000000H to 0FFFFFH 8M bits 000000H to 07FFFFH 4M bits 000000H to 03FFFFH Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X 3. Page Read Operation 3.1 Features of Page Read Operation Features 8 Words Mode Page length 8 words Page read-corresponding addresses A2, A1, A0 Page read start address Don’t care Page direction Don’t care Enabled Note Interrupt during page read operation Note An interrupt is output when /CS = H or in case A3 or a higher address changes. 3.2 Page Length 8 words is supported as the page lengths. 3.3 Page-Corresponding Addresses The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read operation. 3.4 Page Start Address Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address. 3.5 Page Direction Since random page read is possible, there is not restriction on the page direction. 3.6 Interrupt during Page Read Operation When generating an interrupt during page read, either make /CS high level or change A3 and higher addresses. 3.7 When page read is not used Since random page read is supported, even when not using page read, random access is possible as usual. Preliminary Data Sheet M15874EJ5V0DS 11 µPD4632312A-X 4. Mode Register Settings The partial refresh density can be set using the mode register. Since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. When setting the density of partial refresh, data before entering the partial refresh mode is not guaranteed. (This is the same for resetup.) However, since partial refresh mode is not entered unless MODE = L when partial refresh is not used, it is not necessary to set the mode register. Moreover, when using page read without using partial refresh, it is not necessary to set the mode register. 4.1 Mode Register Setting Method The mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address (1FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two write cycles). Commands are written to the command register. The command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode Register Setting Flow Chart. Table 4-1. shows the commands and command sequences. Table 4-1. Command sequence Command sequence Partial refresh density 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle (Read cycle) (Read cycle) (Write cycle) (Write cycle) Address Data Address Data Address Data Address Data 16M bits 1FFFFFH – 1FFFFFH – 1FFFFFH 00H 1FFFFFH 04H 8M bits 1FFFFFH – 1FFFFFH – 1FFFFFH 00H 1FFFFFH 05H 4M bits 1FFFFFH – 1FFFFFH – 1FFFFFH 00H 1FFFFFH 06H 0M bit 1FFFFFH – 1FFFFFH – 1FFFFFH 00H 1FFFFFH 07H 4th bus cycle (Write cycle) I/O 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Mode Register setting 0 0 0 0 0 0 0 0 0 0 0 0 0 PL Page length 12 1 8 words I/O1 I/O0 Density Partial refresh 0 0 16M bits density 0 1 8M bits 1 0 4M bits 1 1 0M bit Preliminary Data Sheet M15874EJ5V0DS 1 0 PD µPD4632312A-X 4.2 Cautions for Setting Mode Register Since, for the mode register setting, the internal counter status is judged by toggling /CS and /OE, toggle /CS at every cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CS at the first and second read cycles. If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register are not performed correctly. When the highest address (1FFFFFH) is read consecutively three or more times, the mode register setting entries are cancelled. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode Register Setting Flow Chart. Preliminary Data Sheet M15874EJ5V0DS 13 µPD4632312A-X 5. Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output supply voltage Symbol Condition Rating VCC Unit -B60X, -B65X -BE75X, -BE85X –0.5 Note to +4.0 –0.5 Note to +4.0 VCCQ – –0.5 Note –0.5 to VCC + 0.4 (4.0 V MAX.) –0.5 Note Note V to +4.0 V Input / Output voltage VT Operating ambient temperature TA –25 to +85 to VCCQ + 0.4 (4.0 V MAX.) –25 to +85 °C V Storage temperature Tstg –55 to +125 –55 to +125 °C Note –1.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage Input / Output supply voltage Symbol Condition -B60X, -B65X -BE75X, -BE85X Unit MIN. MAX. MIN. MAX. VCC 2.7 3.1 2.7 3.1 V VCCQ – – 1.65 2.1 V High level input voltage VIH 0.8VCC VCC+0.3 0.8VCCQ VCCQ+0.3 V Low level input voltage VIL –0.3 Note 0.2VCC –0.3 Note 0.2VCCQ V Operating ambient temperature TA –25 +85 –25 +85 °C Note –0.5 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25°°C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN: Input voltage, VI/O: Input / Output voltage 2. These parameters are not 100% tested. 14 Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition Density of data hold -B60X, -B65X MIN. Unit TYP. MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CS = VIH or –1.0 +1.0 µA 50 mA µA /WE = VIL or /OE = VIH Operating supply current ICCA /CS = VIL, Minimum cycle time, II/O = 0 mA Standby supply current ISB1 /CS ≥ VCC − 0.2 V, MODE ≥ VCC − 0.2 V 32M bits 100 ISB2 /CS ≥ VCC − 0.2 V, MODE ≤ 0.2 V 16M bits 70 8M bits 60 4M bits 50 0M bit 30 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1 mA 0.8VCC V 0.2VCC V Remark VIN: Input voltage, VI/O: Input / Output voltage DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition Density of data hold -BE75X, -BE85X MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCCQ –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCCQ, /CS = VIH or –1.0 +1.0 µA 45 mA µA /WE = VIL or /OE = VIH Operating supply current ICCA /CS = VIL, Minimum cycle time, II/O = 0 mA Standby supply current ISB1 /CS ≥ VCCQ − 0.2 V, MODE ≥ VCCQ − 0.2 V 32M bits 100 ISB2 /CS ≥ VCCQ − 0.2 V, MODE ≤ 0.2 V 16M bits 70 8M bits 60 4M bits 50 0M bit 30 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1 mA 0.8VCCQ V 0.2VCCQ V Remark VIN: Input voltage, VI/O: Input / Output voltage Preliminary Data Sheet M15874EJ5V0DS 15 µPD4632312A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ -B60X, -B65X ] Input Waveform (Rise and Fall Time ≤ 5 ns) Vcc 0.8Vcc Vcc / 2 Test points Vcc / 2 0.2Vcc GND 5ns Output Waveform Vcc / 2 Test points Vcc / 2 [ -BE75X, -BE85X ] Input Waveform (Rise and Fall Time ≤ 5 ns) VccQ 0.8VccQ VccQ / 2 Test points VccQ / 2 0.2VccQ GND 5ns Output Waveform VccQ / 2 Test points VccQ / 2 Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 5-1, Figure 5-2. Figure 5-1. Figure 5-2. [ -B60X, -B65X ] [ -BE75X, -BE85X ] CL: 30 pF CL: 30 pF 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ) 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ) ZO = 50 Ω ZO = 50 Ω I/O (Output) I/O (Output) 50 Ω CL VCC / 2 Remark CL includes capacitance of the probe and jig, and stray capacitance. 16 Preliminary Data Sheet M15874EJ5V0DS 50 Ω VCCQ / 2 CL µPD4632312A-X Read Cycle Parameter Symbol -B60X MIN. -B65X MAX. 65 MIN. -BE75X MAX. 65 MIN. MAX. MIN. Unit Note ns 1 MAX. Read cycle time tRC Address access time tAA 60 65 75 85 ns /CS access time tACS 63 65 75 85 ns /OE to output valid tOE 45 45 50 55 ns /LB, /UB to output valid tBA 63 65 75 85 ns Output hold from address change tOH 5 5 5 5 ns Page read cycle time tPRC 18 18 25 30 ns Page access time tPAA /CS to output in low impedance tCLZ 10 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 5 ns /LB, /UB to output in low impedance tBLZ 5 5 5 5 ns /CS to output in high impedance tCHZ 25 25 25 25 ns /OE to output in high impedance tOHZ 25 25 25 25 ns /LB, /UB to output in high impedance tBHZ 25 25 25 25 ns Address set to /OE low level tASO 0 0 0 0 ns /OE high level to address hold tOHAH –5 –5 –5 –5 ns /CS high level to address hold tCHAH 0 0 0 0 ns 3 /LB, /UB high level to address hold tBHAH 0 0 0 0 ns 3, 4 /CS low level to /OE low level tCLOL 0 ns 5 /OE low level to /CS high level tOLCH 45 45 50 55 ns /CS high level pulse width tCP 10 10 10 10 ns /LB, /UB high level pulse width tBP 10 10 10 10 ns /OE high level pulse width tOP 2 18 10,000 10,000 75 -BE85X 18 0 2 85 25 10,000 0 10,000 2 10,000 10,000 30 0 2 10,000 10,000 ns ns 2 5 Notes 1. Output load: 30 pF 2. Output load: 5 pF 3. When tASO ≥ | tCHAH |, | tBHAH |, tCHAH and tBHAH (MIN.) are –15 ns. tCHAH, tBHAH Address (Input) /LB, /UB, /CS (Input) /OE (Input) tASO 4. tBHAH is specified from when both /LB and /UB become high level. 5. tCLOL and tOP (MAX.) are applied while /CS is being hold at low level. Preliminary Data Sheet M15874EJ5V0DS 17 µPD4632312A-X Write Cycle Parameter Symbol -B60X MIN. MAX. -B65X MIN. MAX. -BE75X MIN. MAX. -BE85X MIN. Unit Note MAX. Write cycle time tWC 65 65 75 85 ns /CS to end of write tCW 55 55 60 70 ns Address valid to end of write tAW 55 55 60 70 ns /LB, /UB to end of write tBW 55 55 60 70 ns Write pulse width tWP 50 50 55 60 ns Write recovery time tWR 0 0 0 0 ns /CS pulse width tCP 10 10 10 10 ns /LB, /UB high level pulse width tBP 10 10 10 10 ns tWHP 10 10 10 10 ns tAS 0 0 0 0 ns /OE high level to address hold tOHAH –5 –5 –5 –5 ns /CS high level to address hold tCHAH 0 0 0 0 ns 1 /LB, /UB high level to address hold tBHAH 0 0 0 0 ns 1, 2 Data valid to end of write tDW 30 30 35 35 ns Data hold time tDH 0 0 0 0 ns /OE high level to /WE set tOES 0 10,000 0 10,000 0 10,000 0 10,000 ns /WE high level to /OE set tOEH 10 10,000 10 10,000 10 10,000 10 10,000 ns /WE high level pulse width Address setup time Notes 1. When tAS ≥ | tCHAH |, | tBHAH | and tCP ≥ 18 ns, tCHAH and tBHAH (MIN.) are –15 ns. tCHAH, tBHAH Address (Input) /LB, /UB, /CS (Input) /WE (Input) tAS 2. tBHAH is specified from when both /LB and /UB become high level. 3. tOES and tOEH (MAX.) are applied while /CS is being hold at low level. 18 Preliminary Data Sheet M15874EJ5V0DS 3 µPD4632312A-X 6. Timing Charts Figure 6-1. Read Cycle Timing Chart 1 (/CS Controlled) tRC tRC tACS tCHAH tACS A3 A2 A1 Address (Input) tCHAH /CS (Input) tCP tCP tCLZ /OE (Input) L /LB, /UB (Input) L tCLZ tCHZ High-Z I/O (Output) tCHZ High-Z High-Z Data Out Q1 Data Out Q2 Remark In read cycle, MODE and /WE should be fixed to high level. Figure 6-2. Read Cycle Timing Chart 2 (/OE Controlled) tRC Address (Input) A3 A2 A1 tAA /CS (Input) tRC tAA tBHAH tBHAH L tASO tOE tASO tOHAH tOE tASO tOHAH /OE (Input) tOP tOP /LB, /UB (Input) tOLZ I/O (Output) tOHZ High-Z tOLZ tOHZ High-Z Data Out Q1 High-Z Data Out Q2 Remark In read cycle, MODE and /WE should be fixed to high level. Preliminary Data Sheet M15874EJ5V0DS 19 µPD4632312A-X Figure 6-3. Read Cycle Timing Chart 3 (/CS, /OE Controlled) tRC Address (Input) tRC A2 A1 tAA tOHAH tACS A3 tCHAH tOLCH tBHAH tBHAH /CS (Input) tCHZ tCLZ tCLOL tOE tASO tOHZ tOE tOHAH /OE (Input) tOHZ tOLZ tOLZ /LB, /UB (Input) High-Z I/O (Output) High-Z High-Z Data Out Q1 Data Out Q2 Remark In read cycle, MODE and /WE should be fixed to high level. Figure 6-4. Read Cycle Timing Chart 4 (Address Controlled) Address (Input) tRC tRC A1 A2 tAA tAA /CS (Input) L /OE (Input) L /LB, /UB (Input) L tOH I/O (Output) tOH tOH Data Out Q1 Remark In read cycle, MODE and /WE should be fixed to high level. 20 A3 Preliminary Data Sheet M15874EJ5V0DS Data Out Q2 µPD4632312A-X Figure 6-5. Read Cycle Timing Chart 5 (/LB, /UB Controlled) tRC Address (Input) tRC A2 A1 /CS (Input) L /OE (Input) L A3 tBHAH tBHAH /LB, /UB (Input) tBP tBP tBA tBA tBHZ tBLZ High-Z I/O (Output) tBHZ tBLZ High-Z Data Out Q1 High-Z Data Out Q2 Remark In read cycle, MODE and /WE should be fixed to high level. Figure 6-6. Page Read Cycle Timing Chart tRC Address (A3 to A20) (Input) tPRC AN AN+1 tPRC tPRC tPRC tPRC tPRC tPRC AN+2 AN+3 AN+4 AN+5 AN+6 AN+7 Page Address (A0 to A2) (Input) tOH /CS (Input) tCHZ tOE /OE (Input) tAA I/O (Output) tOHZ tPAA tPAA tPAA tPAA tPAA tPAA tPAA tOH tOH tOH tOH tOH tOH tOH High-Z QN QN+1 QN+2 QN+3 QN+4 QN+5 QN+6 QN+7 Remarks 1. In read cycle, MODE and /WE should be fixed to high level. 2. /LB and /UB are low level. Preliminary Data Sheet M15874EJ5V0DS 21 µPD4632312A-X Figure 6-7. Write Cycle Timing Chart 1 (/CS Controlled) Address (Input) tAS tWC tWC A1 A2 tAS tWR tCW A3 tCW tAS tWR /CS (Input) tCP /WE (Input) L /LB, /UB (Input) L tCP tOHAH tASO tOES tOEH /OE (Input) tDW High-Z I/O (Input) tDH Data In D1 tDW High-Z tDH Data In D2 High-Z Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark 22 Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB. Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X Figure 6-8. Write Cycle Timing Chart 2 (/WE Controlled) tWC Address (Input) tWC A3 A2 A1 tCHAH tCW tCHAH tCW /CS (Input) tAS tWP tWR tCP /WE (Input) tAS tWP tWR tCP tWHP tBHAH tBHAH /LB, /UB (Input) tOHAH tASO tOES tOEH /OE (Input) tDW I/O (Input) High-Z tDH Data In D1 tDW High-Z tDH Data In D2 High-Z Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB. Preliminary Data Sheet M15874EJ5V0DS 23 µPD4632312A-X Figure 6-9. Write Cycle Timing Chart 3 (/WE Controlled) Address (Input) tWC tWC A1 A2 tAW /CS (Input) A3 tAW L tAS tWP tWR tAS tWP tWR /WE (Input) tWHP tBHAH tBHAH /LB, /UB (Input) tOHAH tASO tOES tOEH /OE (Input) tDW tDH High-Z I/O (Input) tDW tDH High-Z Data In D1 High-Z Data In D2 Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark 24 Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB. Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X Figure 6-10. Write Cycle Timing Chart 4 (/LB, /UB Controlled) Address (Input) /CS (Input) tWC tWC A1 A2 A3 L /WE (Input) tAS tBW /LB, /UB (Input) tBW tAS tWR tWR tBP tBP tOHAH tASO tOES tOEH /OE (Input) tDW High-Z I/O (Input) tDH Data In D1 tDW High-Z tDH Data In D2 High-Z Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB. Preliminary Data Sheet M15874EJ5V0DS 25 µPD4632312A-X Figure 6-11. Write Cycle Timing Chart 5 (/LB, /UB Independent Controlled) Address (Input) /CS (Input) tWC tWC A1 A2 A3 L /WE (Input) tAS tWR tBW /LB (Input) tAS /UB (Input) tBW tWR tBP tOHAH tASO tOES tOEH /OE (Input) tDW I/O0 to I/O7 (Input) High-Z tDH Data In D1 High-Z tDW I/O8 to I/O15 (Input) High-Z tDH Data In D2 High-Z Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark 26 Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB. Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X Figure 6-12. Mode Register Setting Timing Chart Mode Register Setting tRC Address (Input) tRC 1FFFFFH 1FFFFFH tWC tWC 1FFFFFH 1FFFFFH /CS (Input) /OE (Input) tWP tWR tWP tWR /WE (Input) tDW High-Z I/O (Input) tDH xxxxH tDW High-Z tDH xxxxH High-Z /LB, /UB (Input) Figure 6-13. Mode Register Setting Flow Chart Start No Address= 1FFFFFH Read with toggled the /CS, /OE No Address= 1FFFFFH Read with toggled the /CS, /OE No Address = 1FFFFFH Write No Data = 00H? No Mode register setting exit Address = 1FFFFFH Write Data = xxH? Note Fail No End Note xxH = 04H, 05H, 06H, 07H Preliminary Data Sheet M15874EJ5V0DS 27 µPD4632312A-X Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart MODE (Input) tCHML tMHCL1 /CS (Input) Standby mode 1 Standby mode 2 (Data hold: 16M bits / 8M bits / 4M bits) Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart MODE (Input) tCHML tMHCL2 /CS (Input) Standby mode 2 (Data not held) Standby mode 1 Standby Mode 2 Entry / Exit Timing Parameter Standby mode 2 entry Symbol MIN. MAX. Unit Note tCHML 0 ns tMHCL1 30 ns 1 tMHCL2 200 µs 2 /CS high level to MODE low level Standby mode 2 exit to normal operation MODE high level to /CS low level Standby mode 2 exit to normal operation MODE high level to /CS low level Notes 1. This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits). 2. 28 This is the time it takes to return to normal operation from Standby Mode 2 (data not held). Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X 7. Package Drawing 48-PIN TAPE FBGA (8x6) ZE E w ZD S B B 6 5 4 3 2 1 A D H G F E D C B A INDEX MARK w S A INDEX MARK A A2 y1 S S y e S φb φx A1 M S AB ITEM D MILLIMETERS 6.0±0.1 E 8.0±0.1 w e 0.2 0.75 A A1 A2 0.94±0.10 0.24±0.05 0.70 b x 0.40±0.05 0.08 y y1 0.1 0.2 ZD 1.125 ZE 1.375 P48F9-75-BC2 Preliminary Data Sheet M15874EJ5V0DS 29 µPD4632312A-X 8. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD4632312A-X. Type of Surface Mount Device µPD4632312AF9-BC2: 48-pin TAPE FBGA (8 x 6) 30 Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X 9. Revision History Edition/ Date Page This Previous edition edition 5th edition/ pp.1, 2 pp.1, 2 Jan. 2003 pp.1, 15 pp.1, 15 Type of Location Description (Previous edition → This edition) revision Addition Features, Ordering Information -B60X: The note under development was added. Modification Features, DC Characteristics Operating supply current (MAX.): -B65X: 45 mA → 50 mA -BE75X, -BE85X: 40 mA → 45 mA Standby supply current (MAX.): Density of data hold 32M bits: 70 µA → 100 µA 16M bits: 50 µA → 70 µA 8M bits: 45 µA → 60 µA 4M bits: 42 µA → 50 µA 0M bit : 10 µA → 30 µA p.17 p.17 Modification Read Cycle tOLCH (MIN.): -BE75X: 45 ns → 50 ns -BE85X: 45 ns → 55 ns Preliminary Data Sheet M15874EJ5V0DS 31 µPD4632312A-X [MEMO] 32 Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X [MEMO] Preliminary Data Sheet M15874EJ5V0DS 33 µPD4632312A-X [MEMO] 34 Preliminary Data Sheet M15874EJ5V0DS µPD4632312A-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet M15874EJ5V0DS 35 µPD4632312A-X • The information in this document is current as of January, 2003. The information is subject to change without notice. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1