DATA SHEET MOS INTEGRATED CIRCUIT µPD4632312-X 32M-BIT CMOS MOBILE SPECIFIED RAM 2M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD4632312-X is a high speed, low power, 33,554,432 bits (2,097,152 words by 16 bits) CMOS mobile specified RAM featuring low power static RAM compatible function and pin configuration. The µPD4632312-X is fabricated with advanced CMOS technology using one-transistor memory cell. The µPD4632312-X is packed in 77-pin TAPE FBGA. Features • 2,097,152 words by 16 bits organization • Fast access time: 85, 95, 105 ns (MAX.) • Fast page access time: 35, 40, 45 ns (MAX.) • Byte data control: /LB (I/O0 - I/O7), /UB (I/O8 - I/O15) • Low voltage operation (B version: VCC = 2.6 to 3.1 V, C version: VCC = 2.3 to 2.7 V, BE version: VCC = 2.6 to 3.1 V (Chip), VCCQ = 1.65 to 1.95 V (I/O), CE version: VCC = 2.3 to 2.7 V (Chip), VCCQ = 1.65 to 1.95 V (I/O)) • Operating ambient temperature: TA = –25 to +85 °C • Output Enable input for easy application • Chip Enable input: /CS pin • Standby Mode input: MODE pin • Standby Mode1: Normal standby (Memory cell data hold valid) • Standby Mode2: Density of memory cell data hold is variable Product name µPD4632312-BxxX Access Operating time supply voltage ns (MAX.) V 80 Note Operating ambient Supply current At standby µA (MAX.) At operating temperature mA (MAX.) Chip I/O °C 2.7 to 3.1 – –25 to +85 85 2.6 to 3.1 µPD4632312-CxxX 95 2.3 to 2.7 µPD4632312-BExxX 95 2.6 to 3.1 1.65 to 1.95 µPD4632312-CExxX 105 2.3 to 2.7 Density of data hold 32M bits 16M bits 8M bits 4M bits 35 100 70 60 50 0M bit 10 Note Under Development The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M15406EJ7V0DS00 (7th edition) Date Published March 2002 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 2001 µPD4632312-X Ordering Information Part number Package Access time Operating Operating ns (MAX.) supply voltage temperature V °C Chip I/O 85 2.6 to 3.1 – µPD4632312F9-C95X-BT3 95 2.3 to 2.7 µPD4632312F9-BE95X-BT3 95 2.6 to 3.1 µPD4632312F9-CE10X-BT3 105 2.3 to 2.7 µPD4632312F9-B85X-BT3 2 77-pin TAPE FBGA (12 x 7) Data Sheet M15406EJ7V0DS –25 to +85 Remark B version C version 1.65 to 1.95 BE version CE version µPD4632312-X Pin Configuration /xxx indicates active low signal. 77-pin TAPE FBGA (12 x 7) [µPD4632312F9-BxxX-BT3] [µPD4632312F9-CxxX-BT3] [µPD4632312F9-BExxX-BT3] [µPD4632312F9-CExxX-BT3] Top View Bottom View 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P P N M L K J H G F E D C B A Top View E F G H J K A15 NC NC A16 NC GND A11 A12 A13 A14 NC I/O15 I/O7 I/O14 6 A8 A19 A9 A10 I/O6 I/O13 I/O12 I/O5 5 /WE MODE A20 I/O4 VCC VCCQ 4 NC NC NC I/O3 NC I/O11 3 /LB /UB A18 A17 I/O1 I/O9 I/O10 I/O2 A7 A6 A5 A4 GND /OE I/O0 A3 A2 A1 A0 NC /CS 8 A B C NC NC NC NC NC 7 2 1 NC NC NC NC NC D L M N P NC NC NC NC NC I/O8 NC NC NC NC NC A0 - A20 : Address inputs /LB, /UB : Byte data select I/O0 - I/O15 : Data inputs / outputs VCC : Power supply /CS : Chip Select VCCQ MODE : Standby mode GND /WE : Write enable /OE : Output enable NC Note1 Note2 NC : Input / Output power supply : Ground : No Connection Notes 1. B, C version : NC 2. Some signals can be applied because this pin is not internally connected. Remark Refer to Package Drawing for the index mark. Data Sheet M15406EJ7V0DS 3 µPD4632312-X Block Diagram Standby mode control VCC Refresh control VCCQ Note GND Memory cell array 33,554,432 bits Refresh counter A0 A20 Row decoder Address buffer I/O0 - I/O7 I/O8 - I/O15 Input data controller Sense amplifier / Switching circuit Column decoder Address buffer /CS MODE /LB /UB /WE /OE Note BE, CE versions only. 4 Data Sheet M15406EJ7V0DS Output data controller µPD4632312-X Truth Table /CS MODE /OE /WE /LB /UB Mode H H × × × × Not selected (Standby Mode 1) H L × × × × L H H H × × L H L L H L Upper byte read High impedance DOUT H H Output disable High impedance High impedance × L Not selected (Standby Mode 2) I/O Note1 Supply I/O0 - I/O7 I/O8 - I/O15 current High impedance High impedance ISB1 High impedance High impedance ISB2 Output disable High impedance High impedance ICCA L Word read DOUT DOUT H Lower byte read DOUT High impedance L L Word write DIN DIN L H Lower byte write DIN High impedance H L Upper byte write High impedance DIN H H Write-abort Note2 High impedance High impedance Caution MODE pin must be fixed to High except Standby Mode 2. Notes 1. During normal operation, make /CS = VIH, MODE = VIL, the device enters the Standby Mode 2. However, make /CS = VIH or VIL, and MODE = VIL at power application, the device enters the Standby Mode 2. 2. Write data can not be written to the memory cell. Remark ×: VIH or VIL, H: VIH, L: VIL, Data Sheet M15406EJ7V0DS 5 µPD4632312-X CONTENTS 1. Initialization ..................................................................................................................................................................7 2. Partial Refresh ..............................................................................................................................................................8 2.1 Standby Mode..........................................................................................................................................................8 2.2 Density Switching.....................................................................................................................................................8 2.3 Standby Mode Status Transition..............................................................................................................................8 2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................9 3. Page Read Operation ................................................................................................................................................10 3.1 Features of Page Read Operation ........................................................................................................................10 3.2 Page Length .........................................................................................................................................................10 3.3 Page-Corresponding Addresses............................................................................................................................10 3.4 Page Start Address...............................................................................................................................................10 3.5 Page Direction ......................................................................................................................................................10 3.6 Interrupt during Page Read Operation..................................................................................................................10 3.7 Eight-Word Start Page Read Operation Prohibition .............................................................................................10 3.8 Cautions for Eight-Word Page Read Operation....................................................................................................11 4. Mode Register Settings...............................................................................................................................................12 4.1 Mode Register Setting Method .............................................................................................................................12 4.2 Cautions for Setting Mode Register ......................................................................................................................13 5. Electrical Specifications .............................................................................................................................................14 6. Timing Charts.............................................................................................................................................................21 7. Package Drawing .......................................................................................................................................................42 8. Recommended Soldering Conditions ........................................................................................................................43 9. Revision History .........................................................................................................................................................44 6 Data Sheet M15406EJ7V0DS µPD4632312-X 1. Initialization The µPD4632312-X is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, before turning on the power, a 200 µs or longer wait time must precede any signal toggling. (2) After the wait time, read operation must be performed at least 3 times. After that, it can be normal operation. Figure1-1. Initialization Timing Chart VCC, VCCQ VCC (MIN.) VCCQ (MIN.) Address (Input) MODE (Input) VIH (MIN.) tRC /CS (Input) tCP VIH (MIN.) Power On Wait Time Read Operation 3 times 200µ s Normal Operation Cautions 1. Following power application, make MODE and /CS high level during the wait time interval. 2. Following power application, make MODE high level during the wait time and three read operations. 3. The read operation must satisfy the specs described on page 17 (Read Cycle). 4. The address is don’t care (VIH or VIL) during read operation. 5. Read operation must be executed with toggled the /CS pin. 6. To prevent bus contention, it is recommended to set /OE to high level. 7. Do not input data to the I/O pins if /OE is low level during a read operation. Data Sheet M15406EJ7V0DS 7 µPD4632312-X 2. Partial Refresh 2.1 Standby Mode In addition to the regular standby mode (Standby Mode 1) with a 32M bits density, Standby Mode 2, which performs partial refresh, is also provided. 2.2 Density Switching In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit. The density for performing refresh can be set with the mode register. (For how to perform mode register settings, refer to section 4. Mode Register Settings.) 2.3 Standby Mode Status Transition In Standby Mode 1, both /CS and MODE are high level, and in Standby Mode 2, /CS is high level and MODE is low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits, 8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from Standby Mode 2. For the timing charts, refer to Figure 6-26. Standby Mode Timing Chart, Figure 6-27. Standby Mode 2 (Data Invalid) Entry / Recovery Timing Chart. 8 Data Sheet M15406EJ7V0DS µPD4632312-X Figure 2-1. Standby Mode State Machine Power On /CS = VIH, MODE = VIH Wait time 200 µs Dummy Read 3 times Initial State /CS = VIL MODE = VIH Active /CS = VIH, MODE = VIH /CS = VIH, MODE = VIL /CS = VIL, MODE = VIH Standby Mode 1 /CS = VIH, MODE = VIL /CS = VIL, MODE = VIH /CS = VIH, MODE = VIL Standby Mode 2 (16M bits / 8M bits / 4M bits) /CS = VIH, MODE = VIL Standby Mode 2 (Data Invalid) 2.4 Addresses for Which Partial Refresh Is Supported Data hold density Correspondence address 16M bits 000000H to 0FFFFFH 8M bits 000000H to 07FFFFH 4M bits 000000H to 03FFFFH Data Sheet M15406EJ7V0DS 9 µPD4632312-X 3. Page Read Operation 3.1 Features of Page Read Operation Features 4 Word Mode 8 Word Mode Page length 4 words 8 words Page read-corresponding addresses A1, A0 A2, A1, A0 Page read start address Don’t care (A2, A1, A0) = (VIL, VIL, VIL) Page direction Don’t care Sequential increment Interrupt during page read operation Enabled Note Prohibited Note An interrupt is output when /CS = H or in case A2 or a higher address changes. 3.2 Page Length Four words and eight words are supported as the page lengths. The page length is set with the Mode register. Once the page length is set in the mode register, this setting is retained until it is set again. (For how to perform mode register settings, refer to section 4. Mode Register Settings.) 3.3 Page-Corresponding Addresses The four-word page read-enabled addresses are A1 and A0. Fix addresses other than A1 and A0 during four -word page read. The eight-word page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during 8-word page read operation. 3.4 Page Start Address Since random page read is supported for four-word pages, any address can be used as the page start address. Random page read is not supported for eight-word pages. Since the page read start addresses are only (A2, A1, A0) = (VIL, VIL, VIL), it is not possible to start page read from any address other than (A2, A1, A0) = (VIL, VIL, VIL). 3.5 Page Direction Since random page read is possible for four-word pages, there is not restriction on the page direction. Random page read is not supported for eight-word pages. The page direction in this case is sequential increment. 3.6 Interrupt during Page Read Operation When generating an interrupt during four-word page read, either make /CS high level or change A2 and higher addresses. Generating an interrupt during eight-word read is prohibited. 3.7 Eight-Word Start Page Read Operation Prohibition When an eight-word page read has been started, starting a page read with write-modify-read is prohibited. To start page read, do so from normal read. Also, when an eight-word page read has been started, the /OE pin cannot be toggled. For the timing chart, refer to Figure 6-9. 8 Words Page Read Start after Write Modify Read Cycle Timing Chart, Figure 6-11. 8 Words 2 Continuous Read Cycles Timing Chart. 10 Data Sheet M15406EJ7V0DS µPD4632312-X 3.8 Cautions for Eight-Word Page Read Operation To perform normal read (A20 to A3: fixed) from normal read of (A2, A1, A0) = (VIL, VIL, VIL) to (A2, A1, A0) = (VIL, VIL, VIH) with the eight-word page set with the mode register, be sure to toggle /OE for normal read (A2, A1, A0) = (VIL, VIL, VIL). At this time, observe the /OE to address setup time (tOAS) and /OE pulse width (tOP) standard value. When /OE is fixed to low level with normal read (A20 to A3: fixed) from normal read of (A2, A1, A0) = (VIL, VIL, VIL) to (A2, A1, A0) = (VIL, VIL, VIH), eight-word page read starts. Also, when performing a read operation to (A2, A1, A0) = (VIL, VIL, VIH) (A20 to A3 are fixed) from when (A2, A1, A0) = (VIL, VIL, VIL) are in a write-abort state (/WE = L, however, write data cannot be written to the memory cell because /LB, /UM = H), an 8-word page read operation is started. For the timing chart, refer to Figure 6-6. 8 Words Page Read Cycle Timing Chart, Figure 6-12. 8 Words Normal Read Cycle Timing Chart and Figure 6-13 8 Words Write-Abort to Read Cycle Timing Chart. Data Sheet M15406EJ7V0DS 11 µPD4632312-X 4. Mode Register Settings The page length and partial refresh density can be set using the mode register. Since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. When not using page read, set the mode register to random-accessible 4-word page read mode. When not using partial refresh, set the mode register to any value. Partial refresh mode will not be entered unless /CS = H, MODE = L, regardless of the register setting. Once the page length and partial refresh density have been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. 4.1 Mode Register Setting Method The mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address (1FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two write cycles). Commands are written to the command register. The command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. For the timing chart and flow chart, refer to Figure 6-24. Mode Register Setting Timing Chart, Figure 6-25. Mode Register Setting Flow Chart. Table 4-1. shows the commands and command sequences. 12 Data Sheet M15406EJ7V0DS µPD4632312-X Table 4-1. Command sequence Command sequence Partial refresh 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle (Read cycle) (Read cycle) (Write cycle) (Write cycle) Page length Address Data Address Data Address Data Address Data density 16M bits 8M bits 4M bits 0M bit 4 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 00H 8 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 04H 4 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 01H 8 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 05H 4 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 02H 8 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 06H 4 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 03H 8 words 1FFFFFH 1FFFFFH 1FFFFFH 00H 1FFFFFH 07H 4th bus cycle (Write cycle) I/O 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Mode Register setting 0 0 0 0 0 0 0 0 0 0 0 0 0 PL Page length 0 4 words 1 8 words I/O1 I/O0 1 0 PD Density Partial refresh 0 0 16M bits density 0 1 8M bits 1 0 4M bits 1 1 0M bit 4.2 Cautions for Setting Mode Register Since, for the mode register setting, the internal counter status is judged by toggling /CS and /OE, toggle /CS at every cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CS at the first and second read cycles. If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register are not performed correctly. When the highest address (1FFFFFH) is read consecutively three or more times, the mode register setting entries are cancelled. Once the page length and partial refresh density have been set in the mode register, these settings are retained until they are set again. For the timing chart and flow chart, refer to Figure 6-24. Mode Register Setting Timing Chart, Figure 6-25. Mode Register Setting Flow Chart. Data Sheet M15406EJ7V0DS 13 µPD4632312-X 5. Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Supply voltage Rating µPD4632312-BxxX, µPD4632312-BExxX, µPD4632312-CxxX µPD4632312-CExxX –0.5 Note to +4.0 –0.5 Note to +4.0 VCC Input / Output supply voltage Unit VCCQ – –0.5 Note –0.5 to VCC + 0.4 (4.0 V MAX.) –0.5 Note Note V to +4.0 V to VCCQ + 0.4 (4.0 V MAX.) V Input / Output voltage VT Operating ambient temperature TA –25 to +85 –25 to +85 °C Storage temperature Tstg –55 to +125 –55 to +125 °C Note –1.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter µPD4632312 -BxxX Symbol Condition µPD4632312 -CxxX µPD4632312 -BExxX µPD4632312 -CExxX MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Supply voltage VCC 2.6 3.1 2.3 2.7 2.6 3.1 2.3 2.7 V Input / Output supply voltage VCCQ – – – – 1.65 1.95 1.65 1.95 V High level input voltage VIH 0.8VCC VCC+0.3 0.8VCC Low level input voltage VIL –0.3 Note 0.2VCC –0.3 Note 0.2VCC Operating ambient temperature TA –25 +85 –25 +85 VCC+0.3 0.8VCCQ VCCQ+0.3 0.8VCCQ VCCQ+0.3 V –0.3 Note 0.2VCCQ –0.3 Note 0.2VCCQ V –25 +85 –25 +85 °C Note –0.5 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25°°C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN: Input voltage VI/O: Input / Output voltage 2. These parameters are not 100% tested. 14 Data Sheet M15406EJ7V0DS µPD4632312-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition Density of µPD4632312-BxxX, data hold µPD4632312-CxxX MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CS = VIH or –1.0 +1.0 µA 35 mA µA /WE = VIL or /OE = VIH Operating supply current ICCA /CS = VIL, Minimum cycle time, II/O = 0 mA Standby supply current ISB1 /CS ≥ VCC − 0.2 V, MODE ≥ VCC − 0.2 V 32M bits 100 ISB2 /CS ≥ VCC − 0.2 V, MODE ≤ 0.2 V 16M bits 70 8M bits 60 4M bits 50 0M bit 10 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1 mA 0.8VCC V 0.2VCC V Remarks 1. VIN: Input voltage VI/O: Input / Output voltage 2. These DC characteristics are in common regardless of product classifications. DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition Density of µPD4632312-BExxX, data hold µPD4632312-CExxX MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCCQ –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCCQ, /CS = VIH or –1.0 +1.0 µA 35 mA µA /WE = VIL or /OE = VIH Operating supply current ICCA /CS = VIL, Minimum cycle time, II/O = 0 mA Standby supply current ISB1 /CS ≥ VCC − 0.2 V, MODE ≥ VCC − 0.2 V 32M bits 100 ISB2 /CS ≥ VCC − 0.2 V, MODE ≤ 0.2 V 16M bits 70 8M bits 60 4M bits 50 0M bit 10 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1 mA 0.8VCCQ V 0.2VCCQ V Remarks 1. VIN: Input voltage VI/O: Input / Output voltage 2. These DC characteristics are in common regardless of product classifications. Data Sheet M15406EJ7V0DS 15 µPD4632312-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD4632312-B85X, µPD4632312-C95X ] Input Waveform (Rise and Fall Time ≤ 5 ns) Vcc 0.8Vcc Vcc / 2 Test points Vcc / 2 0.2Vcc GND 5ns Output Waveform Vcc / 2 Test points Vcc / 2 [ µPD4632312-BE95X, µPD4632312-CE10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) VccQ 0.8VccQ VccQ / 2 Test points VccQ / 2 0.2VccQ GND 5ns Output Waveform VccQ / 2 Test points VccQ / 2 Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 5-1, Figure 5-2. Figure 5-2. (BE, CE version) Figure 5-1. (B, C version) CL: 30 pF CL: 30 pF 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW ) 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW ) ZO = 50 Ω ZO = 50 Ω I/O (Output) I/O (Output) 50 Ω CL VCC / 2 16 50 Ω VCCQ / 2 Data Sheet M15406EJ7V0DS CL µPD4632312-X Read Cycle Parameter Symbol µPD4632312 µPD4632312 µPD4632312 µPD4632312 -B85X -C95X -BE95X -CE10X MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Note Read cycle time tRC 85 10,000 95 10,000 95 10,000 105 10,000 ns 1 Identical address read cycle time tRC1 85 10,000 95 10,000 95 10,000 105 10,000 ns 2 15 ns 3 Address skew time tSKEW 15 10 15 10 15 /CS pulse width tCP 10 10 ns Address access time tAA 85 95 95 105 ns /CS access time tACS 85 95 95 105 ns /OE to output valid tOE 35 45 45 50 ns /LB, /UB to output valid tBA 35 45 45 50 ns Output hold from address change tOH 10 10 10 10 ns /CS to output in low impedance tCLZ 10 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 5 ns /LB, /UB to output in low impedance tBLZ 5 5 5 5 ns /CS to output in high impedance tCHZ 25 25 25 25 ns /OE to output in high impedance tOHZ 25 25 25 25 ns /LB, /UB to output in high impedance tBHZ 25 25 25 25 ns 4 5 Notes 1. One read cycle (tRC) must satisfy the minimum value (tRC(MIN.)) and maximum value (tRC(MAX.) = 10 µs). tRC indicates the time from the /CS low level input point or address change start point, whichever is later, to the /CS high level input point or the next address change start point, whichever is earlier. As a result, there are the following four conditions for tRC. 1) Time from address change start point to /CS high level input point (address access) 2) Time from address change start point to next address change start point (address access) 3) Time from /CS low level input point to next address change start point (/CS access) 4) Time from /CS low level input point to /CS high level input point (/CS access) 2. The identical address read cycle time (tRC1) is the cycle time of one read operation when performing continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CS low level. Perform settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less. 3. tSKEW indicates the following three types of time depending on the condition. 1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until the next address is determined. 2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to the /CS high level input point. 3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is switched from high level to low level following address determination, or when the address is changed after /CS is switched from low level to high level. 4. Regarding tAA and tACS, only tAA is satisfied during address access (refer to 1) and 2) of Note 1), and only tACS is satisfied during /CS access (refer to 3) of Note 1). 5. Regarding tBA and tOE, only tBA is satisfied if /OE becomes active later than /UB and /LB, and only tOE is satisfied if /UB and /LB become active before /OE. Data Sheet M15406EJ7V0DS 17 µPD4632312-X Page Read Cycle Parameter Symbol µPD4632312 µPD4632312 µPD4632312 µPD4632312 -B85X -C95X -BE95X -CE10X MIN. MAX. 40 MIN. MAX. 45 MIN. MAX. MIN. 40 Unit Note MAX. Page read cycle time tPRC 45 ns Page access time tPAA 35 40 40 45 ns Normal to page read cycle time tNPRC 10,000 10,000 10,000 10,000 ns 1 /OE to address setup time tOAS –5 –5 –5 –5 ns 2 /OE pulse width tOP 10 10 10 10 ns Notes 1. Normal to page read cycle time (tNPRC) is the total cycle time for one 4 word page read and one 8 word page read. Perform settings to that (tNPRC) is 10 µs or less. 2. /OE to address setup time (tOAS) and /OE pulse width (tOP) are effective only when 8 word page read is set. (Refer to section 3.8. Cautions for Eight-Word Page Read Operation.) Standby Mode Entry / Exit Parameter Symbol MIN. MAX. /CS High to MODE Low tCM 0 ns MODE High to /CS Low tMC 30 ns Cautions 1. Make MODE and /CS high level during the wait time interval. 2. Make MODE high level during the wait time and three read operations. 3. The read operation must satisfy the specs described on page 17 (Read Cycle). 4. The address is don’t care (VIH or VIL) during read operation. 5. Read operation must be executed with toggled the /CS pin. 6. To prevent bus contention, it is recommended to set /OE to high level. 7. Do not input data to the I/O pins if /OE is low level during a read operation. 18 Data Sheet M15406EJ7V0DS Unit Note µPD4632312-X Write Cycle Parameter Symbol µPD4632312 µPD4632312 µPD4632312 µPD4632312 -B85X -C95X -BE95X -CE10X MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Note Write cycle time tWC 85 10,000 95 10,000 95 10,000 105 10,000 ns 1 Identical address write cycle time tWC1 85 10,000 95 10,000 95 10,000 105 10,000 ns 2 Address skew time tSKEW 15 ns 3 /CS to end of write tCW 40 50 50 55 ns 4 /LB, /UB to end of write tBW 30 35 35 40 ns Address valid to end of write tAW 35 40 40 45 ns Write pulse width tWP 30 35 35 40 ns Write recovery time tWR 20 20 20 20 ns /CS pulse width tCP 10 10 10 10 ns Address setup time tAS 0 0 0 0 ns Byte write hold time tBWH 20 20 20 20 ns Data valid to end of write tDW 20 30 30 40 ns Data hold time tDH 0 0 0 0 ns /OE to output in low impedance tOLZ 5 5 5 5 ns /WE to output in high impedance tWHZ 25 25 25 25 ns /OE to output in high impedance tOHZ 25 25 25 25 ns Output active from end of write tOW 15 5 15 5 15 5 5 5 ns Notes 1. One write cycle (tWC) must satisfy the minimum value (tWC(MIN.)) and the maximum value (tWC(MAX.) = 10 µs). tWC indicates the time from the /CS low level input point or address change start point, whichever is after, to the /CS high level input point or the next address change start point, whichever is earlier. As a result, there are the following four conditions for tWC. 1) Time from address change start point to /CS high level input point 2) Time from address change start point to next address change start point 3) Time from /CS low level input point to next address change start point 4) Time from /CS low level input point to /CS high level input point 2. The identical address read cycle time (tWC1) is the cycle time of one write cycle when performing continuous write operations with the address fixed and /CS low level, changing /LB and /UB at the same time, and toggling /WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that the sum (tWC) of the identical address write cycle times (tWC1) is 10 µs or less. 3. tSKEW indicates the following three types of time depending on the condition. 1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until the next address is determined. 2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to the /CS high level input point. 3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is switched from high level to low level following address determination, or when the address is changed after /CS is switched from low level to high level. Data Sheet M15406EJ7V0DS 19 µPD4632312-X 4. Definition of write start and write end Write start pattern 1 /CS /WE /LB, /UB Status H to L L L If /WE, /LB, /UB are low level, time when /CS changes from high level to low level Write start pattern 2 L H to L L Write start pattern 3 L L H to L If /CS, /LB, /UB are low level, time when /WE changes from high level to low level If /CS, /WE are low level, time when /LB or /UB changes from high level to low level Write end pattern 1 L L to H L If /CS, /WE, /LB, /UB are low level, time when /WE changes from low level to high level Write end pattern 2 L L L to H When /CS, /WE, /LB, /UB are low level, time when /LB or /UB changes from low level to high level 5. Definition of write end recovery time (tWR) 1) Time from write end to address change start point, or from write end to /CS high level input point 2) When /CS, /LB, /UB are low level and continuously written to the identical address, time from /WE high level input point to /WE low level input point 3) When /CS, /WE are low level and continuously written to the identical address, time from /LB or /UB high level input point, whichever is later, to /LB or /UB low level input point, whichever is earlier. 4) When /CS is low level and continuously written to the identical address, time from write end to point at which /WE , /LB, or /UB starts to change from high level to low level, whichever is earliest. Read Write Cycle Parameter Symbol MIN. MAX. Unit Note 10,000 ns 1, 2 Read write cycle time tRWC Byte write setup time tBWS 20 ns Byte read setup time tBRS 20 ns Notes 1. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. 2. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a read is performed at the identical address using /UB following a write using /LB with /CS low level, or when a read is performed using /LB following a write using /UB. 20 Data Sheet M15406EJ7V0DS µPD4632312-X 6. Timing Charts Figure 6-1. Read Cycle Timing Chart 1 tSKEW tSKEW Address (Input) tCP tRC tCP /CS (Input) tACS tCHZ tCLZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ High impedance I/O (Output) tOH Data out tRC tSKEW tSKEW Address (Input) tCP tCP tACS /CS (Input) tCHZ tCLZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ High impedance Data out I/O (Output) Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed. Remark In read cycle, /WE should be fixed to High. Data Sheet M15406EJ7V0DS 21 22 Figure 6-2. Read Cycle Timing Chart 2 tRC tRC tSKEW tSKEW tSKEW tSKEW Address (Input) tCP tACS tRC tRC tCP tRC tAA Data Sheet M15406EJ7V0DS tAA /CS (Input) tCLZ tCHZ tACS tCHZ tCLZ /OE (Input) tACS tCHZ tCLZ tOE tOLZ tOHZ /LB, /UB (Input) tBA tBHZ tOH tBLZ tBA tBHZ tBLZ I/O (Output) High impedance Data out Data out tBA tBHZ tOH tOH tBLZ Data out Data out Data out time (tRC), none of the data can be guaranteed. Remark In read cycle, /WE should be fixed to High. µPD4632312-X Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle Figure 6-3. Read Cycle Timing Chart 3 tRC tRC tSKEW tRC tSKEW tRC tSKEW tSKEW tRC tSKEW Address (Input) tACS tAA tAA /CS (Input) tCLZ Data Sheet M15406EJ7V0DS tOE tOE tOE /OE (Input) tOHZ tOHZ tOHZ tOLZ tOLZ tOLZ tBA tBA /LB (Input) tBHZ tBLZ I/O0~7 (Output) Hi-Z Data out tOH Data out tBA /UB (Input) tBA tBHZ tBLZ High impedance tOH Data out tBHZ tBLZ tOH Data out Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed. 23 Remark In read cycle, /WE should be fixed to High. µPD4632312-X I/O8~15 (Output) tOH tBHZ tBLZ µPD4632312-X Figure 6-4. Read Cycle Timing Chart 4 tRC tSKEW tSKEW Address (Input) tRC1 Note tRC1 Note tACS /CS (Input) tOE tOE tOLZ tOLZ /OE (Input) tOHZ tBA tBA tOHZ tBLZ tBLZ /LB, /UB (Input) I/O (Output) High impedance tBHZ tBHZ Data out Data out High impedance Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed. Note To perform a continuous read toggling /OE, /UB, and /LB with /CS low level at an identical address, make settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less. Remark In read cycle, /WE should be fixed to High. 24 Data Sheet M15406EJ7V0DS µPD4632312-X Figure 6-5. 4 Words Page Read Cycle Timing Chart tNPRC tRC tPRC tPRC tPRC AN+1 AN+2 AN+3 tSKEW Address (A2 - A20) (Input) AN tSKEW Page Address (A0, A1) (Input) /CS (Input) tACS I/O (Output) tPAA tPAA tOH tOH QN tCHZ tPAA tOH tOH QN+1 QN+2 QN+3 tOHZ tOE tBA tBHZ /OE, /LB, /UB (Input) Figure 6-6. 8 Words Page Read Cycle Timing Chart tNPRC tRC tSKEW Address (A3 - A20) (Input) AN tPRC tPRC tPRC tPRC tPRC tPRC tPRC AN+1 AN+2 AN+3 AN+4 AN+5 AN+6 AN+7 tSKEW Page Address (A0 - A2) (Input) /CS (Input) tACS I/O (Output) tPAA tPAA tPAA tPAA tPAA tPAA tPAA tOH tOH tOH tOH tOH tOH tOH QN QN+1 QN+2 QN+3 tQE tBA QN+4 QN+5 QN+6 tCHZ tOH QN+7 tOHZ tBHZ /OE, /LB, /UB (Input) Data Sheet M15406EJ7V0DS 25 26 Figure 6-7. 4 / 8 Words Continuous Page Read Cycle Timing Chart 4 word page read continuous operation tNPRC Address (Input) tNPRC tNPRC tRC tPRC tPRC tPRC tRC tPRC tPRC tPRC tRC tPRC tPRC tPRC AM AM+1 AM+2 AM+3 AN AN+1 AN+2 AN+3 AP AP+1 AP+2 AP+3 /CS (Input) Data Sheet M15406EJ7V0DS /OE (Input) tOE tOLZ tPAA tAA, tACS, tOE tOH tCLZ tOLZ QM I/O (Output) tPAA tPAA tOH QM+1 tOH QM+2 tOE tOLZ tOHZ tPAA tOH tPAA tOH QM+3 tPAA tOH QN tOHZ tOH QN+1 QN+2 tPAA tOH tOH QN+3 tPAA tOH QP tPAA tOH QP+1 QP+2 tCHZ tOHZ tOH High impedance QP+3 High impedance High impedance High impedance 8 word page read continuous operation tNPRC Address (Input) tNPRC tRC tPRC tPRC tPRC tPRC tPRC tPRC tPRC tRC tPRC tPRC tPRC tPRC tPRC tPRC tPRC AM AM+1 AM+2 AM+3 AM+4 AM+5 AM+6 AM+7 AN AN+1 AN+2 AN+3 AN+4 AN+5 AN+6 AN+7 /CS (Input) tOE tAA, tACS, tOE tCLZ tOLZ I/O (Output) High impedance tPAA tOH QM tPAA tPAA tPAA tPAA tOH tOH tOH tOH QM+1 QM+2 QM+3 QM+4 tPAA tOH QM+5 tPAA tOHZ tOH tOH QM+6 QM+7 tOLZ High impedance tPAA tOH QN tPAA tPAA tPAA tPAA tPAA tPAA tOH tOH tOH tOH tOH tOH QN+1 QN+2 QN+3 QN+4 QN+5 QN+6 tCHZ tOHZ tOH QN+7 µPD4632312-X /OE(Input) µPD4632312-X Figure 6-8. Prohibition of 8 Words Page Read Start after Write Modify Read Cycle Timing Chart tNPRC tWC tRC AN Address (Input) tPRC tPRC tPRC tPRC tPRC tPRC tPRC AN+1 AN+2 AN+3 AN+4 AN+5 AN+6 AN+7 /CS (Input) tAS tWP /WE(Input) tWR /OE (Input) Caution 8 words page read cannot be started with write modify read. 8 words page read can be started by unselecting /CS after writing to AN and then reading AN again. Figure 6-9. 8 Words Page Read Start after Write Modify Read Timing Chart tNPRC tWC tRC AN Address (Input) tPRC tPRC tPRC tPRC tPRC AN+1 AN+2 AN+3 AN+4 AN+5 tPRC AN+6 tPRC AN+7 tCP /CS (Input) tAS tWP /WE (Input) tWR /OE (Input) tDW I/O (Input/Output) High impedance tDH Data in tACS tOE tPAA tPAA tPAA tOH tOH tOH tOH QN+1 QN+2 QN+3 QN Data Sheet M15406EJ7V0DS tPAA tPAA tCHZ tOHZ tPAA tPAA tOH tOH tOH tOH QN+4 QN+5 QN+6 QN+7 27 µPD4632312-X Figure 6-10. Prohibition of 8 Words 2 Continuous Read Cycles Timing Chart tNPRC tRC tRC AN Address (Input) tPRC tPRC tPRC tPRC tPRC tPRC tPRC AN+1 AN+2 AN+3 AN+4 AN+5 AN+6 AN+7 /CS (Input) /OE (Input) Figure 6-11. 8 Words 2 Continuous Read Cycles Timing Chart tNPRC tWC tRC Address (Input) AN tPRC tPRC tPRC tPRC tPRC tPRC tPRC AN+1 AN+2 AN+3 AN+4 AN+5 AN+6 AN+7 tCP /CS (Input) tCLZ tCHZ /OE (Input) tAA tACS tOE tOHZ tOLZ tOLZ High impedance tPAA tOH QN QN I/O (Output) 28 tACS tOE tPAA tOH QN+1 tPAA tOH QN+2 tPAA tPAA tOH tOH QN+3 QN+4 High impedance Data Sheet M15406EJ7V0DS tPAA tOH QN+5 tPAA tOH QN+6 tCHZ tOHZ tOH QN+7 µPD4632312-X Figure 6-12. 8 Words Normal Read Cycle Timing Chart tRC tRC tSKEW tSKEW tSKEW Note Note Address (Input) (A2, A1, A0) = (VIL, VIL, VIL) tACS (A2, A1, A0) = (VIL, VIL, VIH) tAA tOAS /CS (Input) tCLZ tOP tOE tOE /OE (Input) tOLZ tOHZ tOLZ tBA tOHZ tBA /LB,/UB (Input) tBLZ tBHZ I/O (Output) tBLZ Data out tBHZ Data out Caution Always toggle /OE. If /OE is fixed to low level, page read starts. Note A3 and higher address do not change. (A20 to A3) addresses are constant. Figure 6-13. 8 Words Write-Abort to Read Cycle Timing Chart tWC tRC tSKEW Address (Input) tSKEW (A2, A1, A0) = (VIL, VIL, VIL) Note tSKEW (A2, A1, A0) = Note (VIL, VIL, VIH) tAA /CS (Input) tAS tWP tCHZ tWR /WE (Input) tOE /OE (Input) tOLZ tOHZ tBA /LB, /UB (Input) tDW I/O (Output) tDH tBLZ Data in tBHZ Data out Caution When performing a read operation to (A2, A1, A0) = (VIL, VIL, VIH) from when (A2, A1, A0) = (VIL, VIL, VIL) are in a write-abort state, it is recognized as a page read. Note A3 and higher address do not change. (A20 toA3) addresses are constant. Data Sheet M15406EJ7V0DS 29 µPD4632312-X Figure 6-14. Write Cycle Timing Chart 1 tWC tWC tSKEW tSKEW Address (Input) tCW tCP tCW /CS (Input) tWP tWR tAS tWP tWR /WE (Input) tAS tBW tBW /LB, /UB (Input) tDW tDH tDW High impedance tDH High impedance I/O (Input) Data in tSKEW Data in tWC tSKEW tWC tSKEW Address (Input) tCW tCP tCW /CS (Input) tWP tWR tWP tWR /WE (Input) tBW tBW /LB, /UB (Input) tDW High impedance I/O (Input) tDH tDW tDH High impedance Data in Data in Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark 30 Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15406EJ7V0DS µPD4632312-X Figure 6-15. Write Cycle Timing Chart 2 (/WE Controlled) tWC tWC tSKEW tWC tSKEW tSKEW tSKEW tSKEW Address (Input) tCW tAW tCP tAW /CS (Input) tAS tAS /WE (Input) tWP tAS tWR tAW tWP tOW tWR tWP tWR tWHZ /OE (Input) tDW tDH tOLZ tOHZ Indefinite data out Data in I/O (Input/Output) High impedance High impedance tDW tDH Data in High impedance tWC tDW tDH Data in High impedance High impedance tSKEW tSKEW Address (Input) Note Note tWC1 tWC1 /CS (Input) tAS tWP tWR tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW I/O (Input) High impedance tDH Data in tDW High impedance tDH Data in High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or less. Remarks 1. Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 2. When /WE is at Low, the I/O pins are always high impedance. When /WE is at High, read operation is executed. Therefore /OE should be at High to make the I/O pins high impedance. Data Sheet M15406EJ7V0DS 31 µPD4632312-X Figure 6-16. Write Cycle Timing Chart 3 (/CS Controlled) Address (Input) tWC tWC /CS (Input) tAS tCW tWR tAS tCW tWR /WE (Input) /LB, /UB (Input) tDW tDH tDW Data in I/O (Input) High impedance tDH Data in High impedance High impedance Address (Input) tWC tWC /CS (Input) tAS tCW tWR tAS tCW tWR /WE (Input) /LB, /UB (Input) tDW tDH tDW Data in I/O (Input) High impedance tDH Data in High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 32 Data Sheet M15406EJ7V0DS µPD4632312-X Figure 6-17. Write Cycle Timing Chart 4 (/LB, /UB Controlled 1) tWC tWC tSKEW tSKEW Address (Input) tCW tAW /CS (Input) tWP /WE (Input) tAS tBW tWR tAS tBW tWR /LB, /UB (Input) tDW High impedance I/O (Input) tDH tDW High impedance Data in tDH Data in tWC tSKEW tWC tSKEW Address (Input) tCW tAW /CS (Input) tWP /WE (Input) tAS tBW tWR tAS tBW tWR /LB, /UB (Input) tDW I/O (Input) High impedance tDW tDH Data in High impedance tDH Data in Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15406EJ7V0DS 33 µPD4632312-X Figure 6-18. Write Cycle Timing Chart 5 (/LB, /UB Controlled 2) tWC tSKEW tSKEW Address (Input) Note Note tWC1 tWC1 /CS (Input) tWP /WE (Input) tAS tBW tWR tBW tWR /LB, /UB (Input) tDW I/O (Input) High impedance tDH Data in tDW High impedance tDH Data in High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or less. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 34 Data Sheet M15406EJ7V0DS µPD4632312-X Figure 6-19. Write Cycle Timing Chart 6 (/LB, /UB Independent Controlled 1) tWC Address (Input) Note Note tWC1 tWC1 /CS (Input) tCW tWP /WE (Input) /LB (Input) tAS tBW tWR tBW tWR /UB (Input) tDW tDH Data in I/O0~7 (Input) High impedance High impedance tDW tDH Data in I/O8~15 (Input) High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or less. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15406EJ7V0DS 35 µPD4632312-X Figure 6-20. Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 2) Address (Input) tWC /CS (Input) tCW tCW tWP tWP /WE (Input) tBW tWR /LB (Input) tAS tBWH tBW tWR /UB (Input) tAS tDW I/O0~7 (Input) tDH Data in High impedance High impedance tDW tDH Data in I/O8~15 (Input) High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 36 Data Sheet M15406EJ7V0DS µPD4632312-X Figure 6-21. Read Write Cycle Timing Chart 1 (/LB, /UB Independent Controlled 1) tRWC Address (Input) Note Note tRC1 tWC1 tAA /CS (Input) tACS tWP /WE (Input) tBWS /LB (Input) tWR tBW /UB (Input) tCLZ tBLZ tBHZ Data out I/O0~7 (Output) High impedance High impedance tDW I/O8~15 (Input) tDH Data in High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed. Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15406EJ7V0DS 37 µPD4632312-X Figure 6-22. Read Write Cycle Timing Chart 2 (/LB, /UB Independent Controlled 2) tRWC Address (Input) Note Note tWC1 tRC1 tCW /CS (Input) tWR tWP /WE (Input) tBW /LB (Input) tAS tBRS /UB (Input) tDW I/O0~7 (Input) tDH Data in High impedance High impedance tBA tBHZ tBLZ I/O8~15 (Output) Data out High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed. Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 38 Data Sheet M15406EJ7V0DS µPD4632312-X Figure 6-23. Read Write Cycle Timing Chart 3 (/LB, /UB Independent Controlled 3) tRWC Address (Input) Note Note tWC1 tRC1 tCW /CS (Input) tWP tWR /WE (Input) tAS tBW /LB (Input) /UB (Input) tDW I/O0~7 (Input) tDH Data in High impedance High impedance tBHZ tBA tBLZ I/O8~15 (Output) Data out High impedance High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed. Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. Data Sheet M15406EJ7V0DS 39 µPD4632312-X Figure 6-24. Mode Register Setting Timing Chart Mode register setting Address (Input) tRC tRC tWC tWC 1FFFFFH 1FFFFFH 1FFFFFH 1FFFFFH /CS (Input) /OE (Input) tWP tWR tWP tWR /WE (Input) tDW tDH xxxxH I/O (Input) tDW tDH xxxxH /LB, /UB (Input) Figure 6-25. Mode Register Setting Flow Chart Start No Address= 1FFFFFH Read with toggled the /CS, /OE No Address= 1FFFFFH Read with toggled the /CS, /OE No Address = 1FFFFFH Write No Data = 00H? No Mode register setting exit Address = 1FFFFFH Write Data = xxH? Note End Note xxH = 00H, 01H, 02H, 03H, 04H, 05H, 06H, 07H 40 Data Sheet M15406EJ7V0DS Fail No µPD4632312-X Figure 6-26. Standby Mode Timing Chart MODE (Input) tCM tMC /CS (Input) Standby mode 1 Standby mode 2 (Data hold 16M bits / 8M bits / 4M bits) Figure 6-27. Standby Mode 2 (Data Invalid) Entry / Recovery Timing Chart Address (Input) MODE (Input) tRC /CS (Input) tCP tCM Standby Mode 2 (Data invalid) Wait Time 200 µs Data Sheet M15406EJ7V0DS Read Operation 3 times Normal Operation 41 µPD4632312-X 7. Package Drawing 77-PIN TAPE FBGA (12x7) E w S B ZD ZE B 8 7 6 5 4 3 2 1 A D P N M L K J H G F E D C B A INDEX MARK w S A A A2 y1 S S y e S φb A1 φ x M S AB ITEM D MILLIMETERS 7.0±0.1 E 12.0±0.1 w A 0.2 1.1±0.1 A1 A2 e 0.26±0.05 0.84 b 0.45±0.05 x y 0.08 0.1 y1 0.1 ZD ZE 0.7 0.8 0.8 P77F9-80-BT3 42 Data Sheet M15406EJ7V0DS µPD4632312-X 8. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD4632312-X. Types of Surface Mount Device µPD4632312F9-BxxX-BT3: 77-pin TAPE FBGA (12 x 7) µPD4632312F9-CxxX-BT3: 77-pin TAPE FBGA (12 x 7) µPD4632312F9-BExxX-BT3: 77-pin TAPE FBGA (12 x 7) µPD4632312F9-CExxX-BT3: 77-pin TAPE FBGA (12 x 7) Data Sheet M15406EJ7V0DS 43 µPD4632312-X 9. Revision History Edition/ Date Page This edition 6th edition/ Throughout Jan.2002 p.9 Previous edition Type of revision Location Preliminary Data Sheet → Data Sheet Modification p.9 Modification Description (Previous edition → This edition) 2.4 Addresses for Which 5cross beam → 6cross beam Partial Refresh Is Supported 7th edition/ p.4 p.4 Addition Block Diagram Note Mar. 2002 p.5 p.5 Modification Truth Table Standby Mode 2 : /CS = ×→H Notes 1 revision 44 Data Sheet M15406EJ7V0DS µPD4632312-X [ MEMO ] Data Sheet M15406EJ7V0DS 45 µPD4632312-X [ MEMO ] 46 Data Sheet M15406EJ7V0DS µPD4632312-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M15406EJ7V0DS 47 µPD4632312-X • The information in this document is current as of March, 2002. The information is subject to change without notice. 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