NEC UPD784216AYGF

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD784214A, 784215A, 784216A, 784217A, and 784218A are products of the µPD784216A/784218A
Subseries in the 78K/IV Series. Besides a high-speed and high performance CPU, these controllers have ROM,
RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt
functions, and various other peripheral hardware.
The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are based on the µPD784216Y/784218Y
Subseries with the addition of a multimaster-supporting I2C bus interface.
The µPD78F4218A and 78F4218AY, products with a flash memory instead of the internal ROM of mask ROM
versions, and various development tools are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD784216A, 784216AY Subseries User’s Manual Hardware: U13570E
µPD784218A, 784218AY Subseries User’s Manual Hardware: U12970E
78K/IV Series User’s Manual Instructions:
U10905E
FEATURES
• 78K/IV Series
• Inherits peripheral functions of µPD78078, 78078Y
Subseries
• Minimum instruction execution time
160 ns
(@fXX = 12.5 MHz operation with main system clock)
61 µs
(@fXT = 32.768 kHz operation with subsystem clock)
• I/O port: 86 pins
• Timer/event counter:
• 16-bit timer/event counter × 1 unit
• 8-bit timer/event counter × 6 units
• Serial interface: 3 channels
• UART/IOE (3-wire serial I/O): 2 channels
• CSI (3-wire serial I/O, I2C bus supporting
multimaster Note): 2 channels
Note µPD784216AY/784218AY Subseries only
• Supply voltage: VDD = 1.8 to 5.5 V
• Standby function
HALT/STOP/IDLE mode
In low-power consumption mode: HALT/IDLE mode
(with subsystem clock)
• Clock division function
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Clock output function
Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25,
fXX/26, fXX/27, fXT
• Buzzer output function
10
11
12
13
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
APPLICATIONS
Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment
Unless otherwise specified, references in this document to the µPD784218A, 784218AY refer to the
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, and
784218AY.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14121EJ2V0DS00 (2nd edition)
Date Published August 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
2000
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
ORDERING INFORMATION
Part Number
Package
Internal ROM (Bytes)
Internal RAM (Bytes)
µPD784214AGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
96 K
3,584
µPD784214AGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
96 K
3,584
µPD784215AGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
128 K
5,120
µPD784215AGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
128 K
5,120
µPD784216AGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
128 K
8,192
µPD784216AGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
128 K
8,192
µPD784217AGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
192 K
12,800
µPD784217AGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
192 K
12,800
µPD784218AGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
256 K
12,800
µPD784218AGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
256 K
12,800
µPD784214AYGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
96 K
3,584
µPD784214AYGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
96 K
3,584
µPD784215AYGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
128 K
5,120
µPD784215AYGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
128 K
5,120
µPD784216AYGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
128 K
8,192
µPD784216AYGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
128 K
8,192
µPD784217AYGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
192 K
12,800
µPD784217AYGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
192 K
12,800
µPD784218AYGC-×××-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14 mm)
256 K
12,800
µPD784218AYGF-×××-3BA
100-pin plastic QFP
(14 × 20 mm)
256 K
12,800
Remark ××× indicates ROM code suffix.
2
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
78K/IV SERIES LINEUP
: Products in mass-production
: Products under development
Supports I2C bus
µ PD784038Y
µ PD784038
Standard models
µ PD784026
Enhanced
A/D converter,
16-bit timer, and
power management
Enhanced internal memory capacity
Pin-compatible with the µ PD784026
Supports multimaster I2C bus
µ PD784225Y
µ PD784225
80-pin, ROM correction added
Supports multimaster I2C bus
Supports multimaster I2C bus
µPD784216AY
µPD784218AY
µ PD784216A
100-pin, enhanced I/O and
internal memory capacity
µ PD784218A
Enhanced internal memory
capacity, ROM correction added
µ PD784054
µPD784046
ASSP models
On-chip 10-bit A/D converter
µ PD784956A
For DC inverter control
µ PD784908
On-chip IEBusTM controller
µPD784938A
Enhanced functions of the
µ PD784908, enhanced
internal memory capacity,
ROM correction added.
µ PD784967
Enhanced functions of the
µ PD784938A, enhanced
I/O and internal memory
capacity.
Supports multimaster I2C bus
µ PD784928Y
µPD784915
Software servo control
On-chip analog circuit for VCRs
Enhanced timer
µ PD784928
Enhanced functions
of the µ PD784915
µ PD784976A
On-chip VFD controller/driver
Data Sheet U14121EJ2V0DS00
3
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
OVERVIEW OF FUNCTIONS (1/2)
Part Number
Item
µPD784214A,
µPD784215A,
µPD784216A,
µPD784217A,
µPD784218A,
µPD784214AY
µPD784215AY
µPD784216AY
µPD784217AY
µPD784218AY
Number of basic instructions (mnemonics)
113
General-purpose registers
8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory
mapping)
Minimum instruction execution time
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@fXX = 12.5 MHz operation with
main system clock)
• 61 µs (@fXT = 32.768 kHz operation with subsystem clock)
Internal
memory
96 KB
128 KB
3,584 bytes
5,120 bytes
ROM
RAM
Memory space
I/O ports
Pins with
additional
functionsNote 1
192 KB
8,192 bytes
12,800 bytes
1 MB with program and data spaces combined
Total
86
CMOS input
8
CMOS I/O
72
N-ch open-drain I/O
6
Pins with pull-up resistor
70
LED direct drive output
22
Middle-voltage pin
6
Real-time output port
4 bits × 2 or 8 bits × 1
Timer/event counter
Timer/event counter:
(16-bit)
Timer counter × 1
Pulse output
Capture/compare register × 2 • PPG output
• Square wave output
• One-shot pulse output
Timer/event counter 1: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 2: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 5: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 6: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 7: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 8: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Serial interface
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, multimaster supporting I2C busNote 2): 1 channel
A/D converter
8-bit resolution × 8 channels
D/A converter
8-bit resolution × 2 channels
Notes 1. Pins with additional functions are included with the I/O pins.
2. µPD784216AY/784218AY Subseries only
4
256 KB
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
OVERVIEW OF FUNCTIONS (2/2)
µPD784214A,
µPD784215A,
µPD784216A,
µPD784217A,
µPD784218A,
Item
µPD784214AY
µPD784215AY
µPD784216AY
µPD784217AY
µPD784218AY
Clock output
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
Part Number
2
10
11
3
12
4
5
6
7
13
Buzzer output
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
Watch timer
1 channel
Watchdog timer
1 channel
Standby
• HALT/STOP/IDLE modes
• In low power consumption mode (with subsystem clock): HALT/IDLE modes
Interrupt
Hardware sources
29 (internal: 20, external: 9)
Software sources
BRK instruction, BRKCS instruction, operand error
Non-maskable
Internal: 1, external: 1
Maskable
Internal: 19, external: 8
• 4 programmable priority levels
• 3 service modes: Vectored interrupt/macro service/context switching
Supply voltage
VDD = 1.8 to 5.5 V
Package
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Data Sheet U14121EJ2V0DS00
5
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
CONTENTS
1. DIFFERENCES AMONG MODELS IN µPD784216A, 784216AY/784218A, 784218AY SUBSERIES....... 8
2. MAJOR DIFFERENCES FROM µPD78078Y SUBSERIES ................................................................ 9
3. PIN CONFIGURATION (TOP VIEW).................................................................................................. 10
4. BLOCK DIAGRAM ............................................................................................................................... 13
5. PIN
5.1
5.2
5.3
FUNCTIONS .................................................................................................................................. 14
Port Pins ...................................................................................................................................... 14
Non-Port Pins .............................................................................................................................. 16
Pin I/O Circuits and Recommended Connections of Unused Pins ........................................ 18
6. CPU ARCHITECTURE ......................................................................................................................... 22
6.1 Memory Space ............................................................................................................................. 22
6.2 CPU Registers.............................................................................................................................. 29
6.2.1 General-purpose registers ..............................................................................................................29
6.2.2 Control registers..............................................................................................................................30
6.2.3 Special function registers (SFRs)....................................................................................................31
7. PERIPHERAL HARDWARE FUNCTIONS.......................................................................................... 36
7.1 Ports ............................................................................................................................................. 36
7.2 Clock Generator........................................................................................................................... 37
7.3 Real-Time Output Port ................................................................................................................ 39
7.4 Timer/Event Counter ................................................................................................................... 40
7.5 A/D Converter .............................................................................................................................. 42
7.6 D/A Converter .............................................................................................................................. 43
7.7 Serial Interface............................................................................................................................. 44
7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ..........................................................45
7.7.2 Clocked serial interface (CSI) .........................................................................................................47
7.8 Clock Output Function................................................................................................................ 49
7.9 Buzzer Output Function.............................................................................................................. 49
7.10 Edge Detection Function .......................................................................................................... 50
7.11 Watch Timer ............................................................................................................................... 50
7.12 Watchdog Timer ........................................................................................................................ 51
8. INTERRUPT FUNCTIONS.................................................................................................................... 52
8.1 Interrupt Sources......................................................................................................................... 52
8.2 Vectored Interrupt ....................................................................................................................... 54
8.3 Context Switching ....................................................................................................................... 55
8.4 Macro Service .............................................................................................................................. 56
8.5 Application Example of Macro Service ..................................................................................... 57
6
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
9.
LOCAL BUS INTERFACE................................................................................................................. 58
9.1 Memory Expansion ..................................................................................................................... 59
9.2 Programmable Wait .................................................................................................................... 59
10. STANDBY FUNCTION ....................................................................................................................... 60
11. RESET FUNCTION ............................................................................................................................ 62
12. INSTRUCTION SET ........................................................................................................................... 63
13. ELECTRICAL SPECIFICATIONS ...................................................................................................... 68
14. PACKAGE DRAWINGS ..................................................................................................................... 88
15. RECOMMENDED SOLDERING CONDITIONS................................................................................ 90
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 92
APPENDIX B. RELATED DOCUMENTS................................................................................................ 95
Data Sheet U14121EJ2V0DS00
7
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
1. DIFFERENCES AMONG MODELS IN µPD784216A, 784216AY/784218A, 784218AY
SUBSERIES
The only difference among the µPD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal
memory capacity.
The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I2C bus
control function.
The µPD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory
instead of the mask ROM of the above models.
These differences are summarized in Table 1-1.
Table 1-1. Differences Among Models in µPD784216A, 784216AY/784218A, 784218AY Subseries
µPD784214A,
µPD784215A,
µPD784216A,
µPD784217A,
µPD784218A,
µPD78F4216A,
µPD78F4218A,
Item
µPD784214AY
µPD784215AY
µPD784216AY
µPD784217AY
µPD784218AY
µPD78F4216AY
µPD78F4218AY
Internal ROM
96 KB
(Mask
ROM)
128 KB (Mask ROM)
192 KB
(Mask
ROM)
256 KB
(Mask
ROM)
128 KB
(Flash
memory)
256 KB
(Flash
memory)
Internal RAM
3,584 bytes
5,120 bytes
12,800 bytes
5,120 bytes
12,800
bytes
Internal memory size
switching register
(IMS)
Not provided
ROM correction
Not provided
Provided
Not
provided
Provided
External access status
function
Not provided
Provided
Not
provided
Provided
Supply voltage
VDD = 1.8 to 5.5 V
Electrical
specifications
Refer to the data sheet for each device.
Part Number
8,192 bytes
ProvidedNote
VDD = 1.9 to 5.5 V
Recommended
soldering conditions
EXA pin
Not provided
Provided
Not
provided
TEST pin
Provided
Not provided
VPP pin
Not provided
Provided
Provided
Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory
size switching register (IMS).
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (not engineering samples) of the mask ROM version.
8
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
2. MAJOR DIFFERENCES FROM µPD78078Y SUBSERIES
µPD784216A, 784216AY/784218A,
784218AY Subseries
Series Name
Item
CPU
µPD78078Y Subseries
16-bit CPU
8-bit CPU
With main system
clock
160 ns (@12.5 MHz operation)
400 ns (@5.0 MHz operation)
With subsystem clock
61 µs (@32.768 kHz operation)
122 µs (@32.768 kHz operation)
1 MB
64 KB
Total
86
88
CMOS input
8
2
CMOS I/O
72
78
N-ch open-drain I/O
6
8
Pins with pull-up
resistor
70
86
LED direct drive
output
22
16
Middle-voltage pin
6
8
Timer/counter
• 16-bit timer/event counter × 1 unit
• 8-bit timer/event counter × 6 units
• 16-bit timer/event counter × 1 unit
• 8-bit timer/event counter × 4 units
Serial interface
• UART/IOE (3-wire serial I/O) × 2
channels
• CSI (3-wire serial I/O, multimaster
2
supporting I C busNote 2) × 1 channel
• UART/IOE (3-wire serial I/O) × 1
channel
• CSI (3-wire serial I/O, 2-wire serial
2
I/O, I C bus) × 1 channel
• CSI (3-wire serial I/O, 3-wire serial
I/O with automatic transmit/receive
function) × 1 channel
NMI pin
Provided
Not provided
Macro service
Provided
Not provided
Context switching
Provided
Not provided
Programmable priority
4 levels
Not provided
Standby function
• HALT/STOP/IDLE modes
• In low power consumption mode:
HALT/IDLE modes
HALT/STOP modes
Package
• 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
• 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
• 100-pin ceramic WQFN
(14 × 20 mm) (µPD78P078Y only)
Minimum instruction
execution time
Memory space
I/O ports
Pins with
additional
functionsNote 1
Interrupts
Notes 1. Pins with additional functions are included with the I/O pins.
2. µPD784216AY/784218AY Subseries only
Data Sheet U14121EJ2V0DS00
9
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
3. PIN CONFIGURATION (TOP VIEW)
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
×××-8EU,
×××-8EU,
×××-8EU,
×××-8EU,
×××
×××
×××
×××
µPD784214AGC-×××
µPD784215AGC-×××
µPD784216AGC-×××
µPD784217AGC-×××
×××-8EU, µPD784214AYGC-×××
×××-8EU,
×××-8EU,
×××
×××
×××
µPD784218AGC-×××
µPD784215AYGC-×××
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P63/A19
P30/TO0
P103/TI8/TO8
P102/TI7/TO7
P101/TI6/TO6
P100/TI5/TO5
VDD
P36/TI01
P35/TI00
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P37/EXANote 5
P62/A18
P61/A17
P60/A16
VSS
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
P84/A4
P83/A3
P80/A0
P81/A1
P82/A2
P26/SO0
P27/SCK0/SCL0Note 4
P23/PCL
P24/BUZ
P25/SI0/SDA0Note 4
P70/RxD2/SI2
P71/TxD2/SO2
P72/ASCK2/SCK2
P20/RxD1/SI1
P21/TxD1/SO1
P22/ASCK1/SCK1
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AVSSNote 3
P130/ANO0
P131/ANO1
AVREF1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
74
2
73
3
72
4
71
5
70
6
69
7
68
8
67
9
66
10
65
11
64
12
63
13
62
14
61
15
60
16
59
17
58
18
57
19
56
20
55
21
54
22
53
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P11/ANI1
P12/ANI2
P120/RTP0
P121/RTP1
P122/RTP2
P123/RTP3
P124/RTP4
P125/RTP5
P126/RTP6
P127/RTP7
VDD
X2
X1
VSS
XT2
XT1
RESET
P00/INTP0
P01/INTP1
P02/INTP2/NMI
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
AVDDNote 2
AVREF0
P10/ANI0
P90
TESTNote 1
P95
P94
P93
P92
P91
×××-8EU,
×××-8EU,
×××-8EU
×××
×××
×××
µPD784216AYGC-×××
µPD784217AYGC-×××
µPD784218AYGC-×××
Notes 1. Connect the TEST pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is
recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
4. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only.
5. The EXA pin is available in µPD784218A, 784218AY Subseries products only.
10
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
• 100-pin plastic QFP (14 × 20 mm)
×××-3BA,
×××-3BA,
×××-3BA,
×××-3BA,
×××
×××
×××
×××
µPD784214AGF-×××
µPD784215AGF-×××
µPD784216AGF-×××
µPD784217AGF-×××
×××-3BA, µPD784214AYGF-×××
×××-3BA,
×××-3BA,
×××
×××
×××
µPD784218AGF-×××
µPD784215AYGF-×××
VSS
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
×××-3BA,
×××-3BA,
×××-3BA
×××
×××
×××
µPD784216AYGF-×××
µPD784217AYGF-×××
µPD784218AYGF-×××
P60/A16
P61/A17
P62/A18
P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
VDD
P100/TI5/TO5
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/TI00
P36/TI01
P37/EXANote 5
TESTNote 1
P90
P91
P92
P93
P94
P95
P84/A4
P83/A3
P82/A2
P81/A1
P80/A0
P27/SCK0/SCL0Note 4
P26/SO0
P25/SI0/SDA0Note 4
P24/BUZ
P23/PCL
P22/ASCK1/SCK1
P21/TxD1/SO1
P20/RxD1/SI1
P72/ASCK2/SCK2
P71/TxD2/SO2
P70/RxD2/SI2
AVREF1
P131/ANO1
P130/ANO0
AVSSNote 3
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVREF0
AVDDNote 2
P122/RTP2
P123/RTP3
P124/RTP4
P125/RTP5
P126/RTP6
P127/RTP7
VDD
X2
X1
VSS
XT2
XT1
RESET
P00/INTP0
P01/INTP1
P02/INTP2/NMI
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
P120/RTP0
P121/RTP1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes 1. Connect the TEST pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is
recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
4. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only.
5. The EXA pin is available in µPD784218A, 784218AY Subseries products only.
Data Sheet U14121EJ2V0DS00
11
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
A0 to A19:
Address Bus
P120 to P127:
Port 12
AD0 to AD7:
Address/Data Bus
P130, P131:
Port 13
ANI0 to ANI7:
Analog Input
PCL:
Programmable Clock
ANO0, ANO1:
Analog Output
RD:
Read Strobe
ASCK1, ASCK2:
Asynchronous Serial Clock
RESET:
Reset
ASTB:
Address Strobe
RTP0 to RTP7:
Real-time Output Port
AVDD:
Analog Power Supply
RxD1, RxD2:
Receive Data
AVREF0, AVREF1:
Analog Reference Voltage
SCK0 to SCK2:
Serial Clock
AVSS:
Analog Ground
SCL0Note 1:
Serial Clock
BUZ:
Buzzer Clock
SDA0Note 1:
Serial Data
External Access Status Output
SI0 to SI2:
Serial Input
Note 2
EXA
:
INTP0 to INTP6:
Interrupt from Peripherals
SO0 to SO2:
Serial Output
NMI:
Non-maskable Interrupt
TEST:
Test
P00 to P06:
Port 0
TI00, TI01,
P10 to P17:
Port 1
TI1, TI2, TI5 to TI8:
P20 to P27:
Port 2
TO0 to TO2, TO5 to TO8: Timer Output
P30 to P37:
Port 3
TxD1, TxD2:
Transmit Data
Timer Input
P40 to P47:
Port 4
VDD:
Power Supply
P50 to P57:
Port 5
VSS:
Ground
P60 to P67:
Port 6
WAIT:
Wait
P70 to P72:
Port 7
WR:
Write Strobe
P80 to P87:
Port 8
X1, X2:
Crystal (Main System Clock)
P90 to P95:
Port 9
XT1, XT2:
Crystal (Subsystem Clock)
P100 to P103:
Port 10
Notes 1. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only.
2. The EXA pin is available in µPD784218A, 784218AY Subseries products only.
12
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
4. BLOCK DIAGRAM
INTP2/NMI
INTP0, INTP1,
INTP3 to INTP6
UART/IOE1
Baud-rate
generator
Programmable
interrupt
controller
TI00
TI01
TO0
Timer/event
counter
(16 bits)
TI1
TO1
Timer/event
counter 1
(8 bits)
TI2
TO2
Timer/event
counter 2
(8 bits)
TI5/TO5
Timer/event
counter 5
(8 bits)
UART/IOE2
Baud-rate
generator
Clocked
serial
interfaceNote 1
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0/SDA0
SO0
SCK0/SCL0
AD0 to AD7
A0 to A7
A8 to A15
Bus I/F
A16 to A19
RD
WR
WAIT
ASTB
EXANote 2
TI6/TO6
Timer/event
counter 6
(8 bits)
Timer/event
counter 7
(8 bits)
Port 0
P00 to P06
TI7/TO7
Port 1
P10 to P17
Timer/event
counter 8
(8 bits)
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P72
Port 8
P80 to P87
Port 9
P90 to P95
Port 10
P100 to P103
Port 12
P120 to P127
Port 13
P130, P131
TI8/TO8
Watch timer
78K/IV
CPU Core
ROM
RAM
Watchdog timer
RTP0 to RTP7
NMI/INTP2
ANO0
ANO1
AVREF1
AVSS
P03/INTP3
ANI0 to ANI7
AVREF0
AVDD
AVSS
PCL
Real-time
output port
D/A
converter
A/D
converter
RESET
X1
Clock output
control
System control
X2
XT1
BUZ
Buzzer output
XT2
VDD
VSS
TEST
2
Notes 1. This function supports the I C bus interface and is available in µPD784216AY/784218AY Subseries
products only.
2. The EXA pin is available in µPD784218A, 784218AY Subseries products only.
Remark The internal ROM and RAM capacities differ depending on the product.
Data Sheet U14121EJ2V0DS00
13
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
5. PIN FUNCTIONS
5.1 Port Pins (1/2)
Pin Name
P00
I/O
I/O
Alternate Function
INTP0
P01
INTP1
P02
INTP2/NMI
P03
INTP3
P04
INTP4
P05
INTP5
P06
INTP6
P10 to P17
P20
Input
I/O
Port 1 (P1):
• 8-bit input only port
RxD1/SI1
Port 2 (P2):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip
pull-up resistor can be specified in 1-bit units by means of
software.
TxD1/SO1
P22
ASCK1/SCK1
P23
PCL
P24
BUZ
P25
SI0/SDA0Note 1
P26
SO0
P27
SCK0/SCL0Note 1
I/O
Port 0 (P0):
• 7-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip
pull-up resistor can be specified in 1-bit units by means of
software.
ANI0 to ANI7
P21
P30
Function
TO0
P31
TO1
P32
TO2
P33
TI1
P34
TI2
P35
TI00
P36
TI01
P37
EXANote 2
Port 3 (P3):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip
pull-up resistor can be specified in 1-bit units by means of
software.
P40 to P47
I/O
AD0 to AD7
Port 4 (P4):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• All pins set in input mode can be connected to on-chip pull-up
resistors by means of software.
• LEDs can be driven directly.
P50 to P57
I/O
A8 to A15
Port 5 (P5):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• All pins set in input mode can be connected to on-chip pull-up
resistors by means of software.
• LEDs can be driven directly.
Notes 1. This function is available in µPD784216AY/784218AY Subseries products only.
2. This function is available in µPD784218A, 784218AY Subseries products only.
14
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
5.1 Port Pins (2/2)
Pin Name
P60
I/O
I/O
Alternate Function
A16
P61
A17
P62
A18
P63
A19
P64
RD
P65
WR
P66
WAIT
P67
ASTB
P70
I/O
Port 6 (P6):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• All pins set in input mode can be connected to on-chip pull-up
resistors by means of software.
RxD2/SI2
P71
TxD2/SO2
P72
ASCK2/SCK2
P80 to P87
I/O
P90 to P95
I/O
P100
I/O
A0 to A7
TI5/TO5
TI6/TO6
P102
TI7/TO7
P103
TI8/TO8
Port 7 (P7):
• 3-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip
pull-up resistor can be specified in 1-bit units by means of
software.
Port 8 (P8):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip
pull-up resistor can be specified in 1-bit units by means of
software.
• The interrupt control flag (KRIF) is set to 1 when a falling edge is
detected at a pin of this port.
−
P101
Function
Port 9 (P9):
• N-ch open-drain middle-voltage I/O port
• 6-bit I/O port
• Input/output can be specified in 1-bit units.
• LEDs can be driven directly.
Port 10 (P10):
• 4-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip
pull-up resistor can be specified in 1-bit units by means of
software.
P120 to P127
I/O
RTP0 to RTP7
Port 12 (P12):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip
pull-up resistor can be specified in 1-bit units by means of
software.
P130, P131
I/O
ANO0, ANO1
Port 13 (P13):
• 2-bit I/O port
• Input/output can be specified in 1-bit units.
Data Sheet U14121EJ2V0DS00
15
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
5.2 Non-Port Pins (1/2)
Pin Name
TI00
I/O
Alternate Function
Function
P35
External count clock input to 16-bit timer counter
TI01
P36
Capture trigger signal input to capture/compare register 00
TI1
P33
External count clock input to 8-bit timer counter 1
TI2
P34
External count clock input to 8-bit timer counter 2
TI5
P100/TO5
External count clock input to 8-bit timer counter 5
TI6
P101/TO6
External count clock input to 8-bit timer counter 6
TI7
P102/TO7
External count clock input to 8-bit timer counter 7
TI8
P103/TO8
External count clock input to 8-bit timer counter 8
P30
16-bit timer output (shared by 14-bit PWM output)
TO1
P31
8-bit timer output (shared by 8-bit PWM output)
TO2
P32
TO5
P100/TI5
TO6
P101/TI6
TO7
P102/TI7
TO8
P103/TI8
TO0
RxD1
Input
Output
Input
RxD2
TxD1
Output
TxD2
ASCK1
Input
ASCK2
SI0
Input
P20/SI1
Serial data input (UART1)
P70/SI2
Serial data input (UART2)
P21/SO1
Serial data output (UART1)
P71/SO2
Serial data output (UART2)
P22/SCK1
Baud rate clock input (UART1)
P72/SCK2
Baud rate clock input (UART2)
Note
P25/SDA0
Serial data input (3-wire serial I/O 0)
SI1
P20/RxD1
Serial data input (3-wire serial I/O 1)
SI2
P70/RxD2
Serial data input (3-wire serial I/O 2)
P26
Serial data output (3-wire serial I/O 0)
SO0
Output
SO1
P21/TxD1
Serial data output (3-wire serial I/O 1)
SO2
P71/TxD2
Serial data output (3-wire serial I/O 2)
P25/SI0
Serial data input/output (I C bus)
SCK0
P27/SCL0Note
Serial clock input/output (3-wire serial I/O 0)
SCK1
P22/ASCK1
Serial clock input/output (3-wire serial I/O 1)
SCK2
P72/ASCK2
Serial clock input/output (3-wire serial I/O 2)
SCL0
P27/SCK0
Serial clock input/output (I C bus)
P02/INTP2
Non-maskable interrupt request input
INTP0
P00
External interrupt request input
INTP1
P01
INTP2
P02/NMI
INTP3
P03
INTP4
P04
SDA0
NMI
I/O
Input
INTP5
P05
INTP6
P06
2
2
Note This function is available in µPD784216AY/784218AY Subseries products only.
16
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
5.2 Non-Port Pins (2/2)
Pin Name
I/O
Alternate Function
Function
PCL
Output
P23
Clock output (for trimming main system clock and subsystem clock)
BUZ
Output
P24
Buzzer output
RTP0 to RTP7
Output
P120 to P127
Real-time output port that outputs data in synchronization with
trigger
I/O
P40 to P47
Lower address/data bus for expanding memory externally
Output
P80 to P87
Lower address bus for expanding memory externally
AD0 to AD7
A0 to A7
A8 to A15
P50 to P57
Middle address bus for expanding memory externally
A16 to A19
P60 to P63
Higher address bus for expanding memory externally
P64
Strobe signal output for reading from external memory
P65
Strobe signal output for writing to external memory
RD
Output
WR
WAIT
Input
P66
Wait insertion at external memory access
ASTB
Output
P67
Strobe output that externally latches address information output to
ports 4 through 6 and 8 to access external memory
EXANote
Output
P37
Status signal output at external memory access
RESET
Input
−
System reset input
X1
Input
−
Connecting crystal resonator for main system clock oscillation
X2
−
−
Connecting crystal resonator for subsystem clock oscillation
XT1
Input
XT2
−
ANI0 to ANI7
Input
P10 to P17
ANO0, ANO1
Output
P130, P131
AVREF0
−
A/D converter analog input
D/A converter analog output
−
A/D converter reference voltage input
AVREF1
D/A converter reference voltage input
AVDD
A/D converter positive power supply. Connect to VDD.
AVSS
GND for A/D converter and D/A converter. Connect to VSS.
VDD
Positive power supply
VSS
GND
TEST
Connect this pin to VSS directly or via a pull-down resistor. For the
pull-down connection, it is recommended to use a resistor with a
resistance ranging from 470 Ω to 10 kΩ (this pin is for IC test).
Note This function is available in µPD784218A, 784218AY Subseries products only.
Data Sheet U14121EJ2V0DS00
17
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
5.3 Pin I/O Circuits and Recommended Connections of Unused Pins
The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 5-1.
For each type of input/output circuit, refer to Figure 5-1.
Table 5-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins (1/2)
Pin Name
P00/INTP0
I/O Circuit Type
I/O
8-N
I/O
P01/INTP1
Recommended Connection of Unused Pins
Input: Independently connect to VSS via a resistor
Output: Leave open
P02/INTP2/NMI
P03/INTP3 to P06/INTP6
P10/ANI0 to P17/ANI7
9
P20/RxD1/SI1
10-K
P21/TxD1/SO1
10-L
P22/ASCK1/SCK1
10-K
P23/PCL
10-L
Input
I/O
Connect to VSS or VDD
Input: Independently connect to VSS via a resistor
Output: Leave open
P24/BUZ
P25/SI0/SDA0Note 1
10-K
P26/SO0
10-L
Note 1
P27/SCK0/SCL0
10-K
P30/TO0 to P32/TO2
12-E
P33/TI1, P34/TI2
8-N
P35/TI00, P36/TI01
10-M
P37/EXA
Note 2
P40/AD0 to P47/AD7
12-E
5-A
P50/A8 to P57/A15
P60/A16 to P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P70/RxD2/SI2
8-N
P71/TxD2/SO2
10-M
P72/ASCK2/SCK2
8-N
P80/A0 to P87/A7
12-E
P90 to P95
13-D
P100/TI5/TO5
8-N
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8
P120/RTP0 to P127/RTP7
12-E
P130/ANO0, P131/ANO1
12-F
Notes 1. This function is available in µPD784216AY/784218AY Subseries products only.
2. This function is available in µPD784218A, 784218AY Subseries products only.
18
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 5-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name
I/O Circuit Type
RESET
2-G
XT1
16
AVREF1
Recommended Connection of Unused Pins
−
Input
Connect to VSS
−
XT2
AVREF0
I/O
−
Leave open
Connect to VSS
Connect to VDD
AVDD
AVSS
Connect to VSS
TEST
Connect this pin to VSS directly or via a pull-down resistor.
For the pull-down connection, it is recommended to use a resistor
with a resistance ranging from 470 Ω to 10 kΩ.
Remark Because the circuit type numbers are standardized among the 78K Series products, they are not
sequential in some models (i.e., some circuits are not provided).
Data Sheet U14121EJ2V0DS00
19
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 5-1. Types of Pin I/O Circuits (1/2)
Type 2-G
Type 10-K
VDD
Pullup
enable
P-ch
IN
VDD
Data
P-ch
IN/OUT
Open drain
Output disable
N-ch
Schmitt-triggered input with hysteresis characteristics
Type 5-A
Type 10-L
VDD
Pullup
enable
VDD
Pullup
enable
P-ch
P-ch
VDD
Data
VDD
Data
P-ch
P-ch
IN/OUT
Output
disable
IN/OUT
Open drain
Output disable
N-ch
N-ch
VSS
Input
enable
Type 8-N
Type 10-M
VDD
Pullup
enable
VDD
Pullup
enable
P-ch
P-ch
VDD
VDD
Data
Data
P-ch
P-ch
IN/OUT
Output
disable
N-ch
Output disable
N-ch
VSS
VDD
Type 12-E
Type 9
IN
IN/OUT
P-ch
N-ch
Comparator
+
Pullup
enable
P-ch
VDD
Data
–
P-ch
IN/OUT
Output
disable
(Threshold voltage)
Input
enable
20
Input
enable
Data Sheet U14121EJ2V0DS00
N-ch
P-ch
Analog output
voltage
N-ch
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 5-1. Types of Pin I/O Circuits (2/2)
Type 16
Type 12-F
VDD
Data
Feedback
cut-off
P-ch
P-ch
IN/OUT
Output
disable
Input
enable
N-ch
VSS
Analog output
voltage
P-ch
N-ch
XT1
VSS
XT2
Type 13-D
IN/OUT
Data
Output disable
N-ch
VDD
RD
P-ch
Middle-voltage input buffer
Data Sheet U14121EJ2V0DS00
21
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
6. CPU ARCHITECTURE
6.1 Memory Space
A memory space of 1 MB can be accessed. Mapping of the internal data area (special function registers and
internal RAM) can be specified by the LOCATION instruction. The LOCATION instruction must always be executed
after reset cancellation, and must not be used more than once.
(1) When LOCATION 0H instruction is executed
• Internal memory
The internal data area and internal ROM area are mapped as follows.
Part Number
Internal Data Area
Internal ROM Area
µPD784214A,
µPD784214AY
0F100H to 0FFFFH
00000H to 0F0FFH
10000H to 17FFFH
µPD784215A,
µPD784215AY
0EB00H to 0FFFFH
00000H to 0EAFFH
10000H to 1FFFFH
µPD784216A,
µPD784216AY
0DF00H to 0FFFFH
00000H to 0DEFFH
10000H to 1FFFFH
µPD784217A,
µPD784217AY
0CD00H to 0FFFFH
00000H to 0CCFFH
10000H to 2FFFFH
µPD784218A,
µPD784218AY
00000H to 0CCFFH
10000H to 3FFFFH
Caution The following areas that overlap the internal data area of the internal ROM cannot be used
when the LOCATION 0H instruction is executed.
Part Number
Unusable Area
µPD784214A,
µPD784214AY
0F100H to 0FFFFH (3,840 bytes)
µPD784215A,
µPD784215AY
0EB00H to 0FFFFH (5,376 bytes)
µPD784216A,
µPD784216AY
0DF00H to 0FFFFH (8,448 bytes)
µPD784217A,
µPD784217AY
0CD00H to 0FFFFH (13,056 bytes)
µPD784218A,
µPD784218AY
• External memory
The external memory is accessed in external memory expansion mode.
22
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(2) When LOCATION 0FH instruction is executed
• Internal memory
The internal data area and internal ROM area are mapped as follows.
Part Number
Internal Data Area
Internal ROM Area
µPD784214A,
µPD784214AY
FF100H to FFFFFH
00000H to 17FFFH
µPD784215A,
µPD784215AY
FEB00H to FFFFFH
00000H to 1FFFFH
µPD784216A,
µPD784216AY
FDF00H to FFFFFH
00000H to 1FFFFH
µPD784217A,
µPD784217AY
FCD00H to FFFFFH
00000H to 2FFFFH
µPD784218A,
µPD784218AY
00000H to 3FFFFH
• External memory
The external memory is accessed in external memory expansion mode.
Data Sheet U14121EJ2V0DS00
23
24
Figure 6-1. Memory Map of µPD784214A, 784214AY
On execution of
LOCATION 0H instruction
On execution of
LOCATION 0FH instruction
F F F F FH
External memory
(928 KB)
1 8 0 0 0H
1 7 F F FH
General-purpose
registers (128 bytes)
Note 1
0 FE8 0H
0 FE 7 FH
function registers (SFR)
(256 bytes)
Internal RAM
(3,584 bytes)
FFE8 0H
F FE 7 FH
FF 1 0 0H
F F 0 F FH
Internal ROM
Data Sheet U14121EJ2V0DS00
(32,768 bytes)
1 0 0 0 0H
0 F F F FH
Special function registers
0 F FDFH
Note 1
0 F FD0H
(256 bytes)
0 FF 0 0H
0 FEF FH
0 F E 3 BH
(SFR)
0 FE0 6H
Macro service control word
area (54 bytes)
F F E 3 BH
FFE0 6H
Data area (512 bytes)
0 FD0 0H
0 FCF FH
Internal RAM
(3,584 bytes)
F FD0 0H
F FCF FH
External memory
(980,736 bytes)
Program/data area
(3,072 bytes)
0 F 1 0 0H
0 F 0 F FH
0 F 1 0 0H
FF 1 0 0H
1 7 F F FH
1 0 0 0 0H
1 7 F F FH
Note 1
Note 2
0 F 0 F FH
Program/data area
Note 4
Note 3
0 1 0 0 0H
0 0 F F FH
CALLF entry
area (2 KB)
Internal ROM
(61,696 bytes)
0 0 8 0 0H
0 0 7 F FH
0 0 0 8 0H
0 0 0 7 FH
0 0 0 4 0H
0 0 0 3 FH
0 0 0 0 0H
0 0 0 0 0H
1 8 0 0 0H
1 7 F F FH
CALLT table
area (64 bytes)
Vector table area
(64 bytes)
Internal ROM
(96 KB)
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode.
2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
Note 4
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
F FEF FH
0 FEF FH
F F F F F H Special
F F FDFH
Note 1
F F FD0H
FFF 0 0H
F FEF FH
Figure 6-2. Memory Map of µPD784215A, 784215AY
On execution of
LOCATION 0FH instruction
F F F F FH
External memory
(896 KB)
Note 1
F FEF FH
0 FEF FH
General-purpose
registers (128 bytes)
0 FE8 0H
0 FE 7 FH
2 0 0 0 0H
1 F F F FH
Data Sheet U14121EJ2V0DS00
1 0 0 0 0H
0 F F F FH
Special
0 F FDFH
Note 1
0 F FD0H
0 FF 0 0H
0 FEF FH
F F F F F H Special
F F FDFH
Note 1
F F FD0H
FFF 0 0H
F FEF FH
Internal ROM
(65,536 bytes)
0 F E 3 BH
function registers (SFR)
0 FE0 6H
(256 bytes)
(256 bytes)
Internal RAM
(5,120 bytes)
FFE8 0H
F FE 7 FH
Macro service control word
area (54 bytes)
function registers (SFR)
FEB 0 0H
FEAF FH
F F E 3 BH
FFE0 6H
Data area (512 bytes)
0 FD0 0H
0 FCF FH
Internal RAM
(5,120 bytes)
F FD0 0H
F FCF FH
External memory
(912,128 bytes)
Program/data area
(4,608 bytes)
0 EB 0 0H
0 EAF FH
0 EB 0 0H
FEB 0 0H
1 F F F FH
1 0 0 0 0H
1 F F F FH
Note 1
Note 2
0 EAF FH
Program/data area
Note 4
Note 3
0 1 0 0 0H
0 0 F F FH
CALLF entry
area (2 KB)
Internal ROM
(60,160 bytes)
0 0 8 0 0H
0 0 7 F FH
0 0 0 8 0H
0 0 0 7 FH
0 0 0 4 0H
0 0 0 3 FH
0 0 0 0 0H
0 0 0 0 0H
2 0 0 0 0H
1 F F F FH
CALLT table
area (64 bytes)
Vector table area
(64 bytes)
Internal ROM
(128 KB)
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode.
2. This 5,376-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
3. On execution of LOCATION 0H instruction: 125,696 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes
25
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
Note 4
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
On execution of
LOCATION 0H instruction
26
Figure 6-3. Memory Map of µPD784216A, 784216AY
On execution of
LOCATION 0H instruction
On execution of
LOCATION 0FH instruction
F F F F FH
Note 1
General-purpose
registers (128 bytes)
0 FE8 0H
0 FE 7 FH
2 0 0 0 0H
1 F F F FH
Data Sheet U14121EJ2V0DS00
1 0 0 0 0H
0 F F F FH
Special
0 F FDFH
Note 1
0 F FD0H
0 FF 0 0H
0 FEF FH
Internal ROM
(65,536 bytes)
0 F E 3 BH
function registers (SFR)
0 FE0 6H
(256 bytes)
(256 bytes)
Internal RAM
(8,192 bytes)
FFE8 0H
F FE 7 FH
Macro service control word
area (54 bytes)
function registers (SFR)
FDF 0 0H
FDE F FH
F F E 3 BH
FFE0 6H
Data area (512 bytes)
0 FD0 0H
0 FCF FH
Internal RAM
(8,192 bytes)
F FD0 0H
F FCF FH
External memory
(909,056 bytes)
Program/data area
(7,680 bytes)
0DF 0 0H
0 DE F FH
0DF 0 0H
FDF 0 0H
1 F F F FH
1 0 0 0 0H
1 F F F FH
Note 1
Note 2
0 DE F FH
Program/data area
Note 4
Note 3
0 1 0 0 0H
0 0 F F FH
CALLF entry
area (2 KB)
Internal ROM
(57,088 bytes)
0 0 8 0 0H
0 0 7 F FH
0 0 0 8 0H
0 0 0 7 FH
0 0 0 4 0H
0 0 0 3 FH
0 0 0 0 0H
0 0 0 0 0H
2 0 0 0 0H
1 F F F FH
CALLT table
area (64 bytes)
Vector table area
(64 bytes)
Internal ROM
(128 KB)
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode.
2. This 8,448-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
3. On execution of LOCATION 0H instruction: 122,624 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
Note 4
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
External memory
(896 KB)
F FEF FH
0 FEF FH
F F F F F H Special
F F FDFH
Note 1
F F FD0H
FFF 0 0H
F FEF FH
Figure 6- 4. Memory Map of µPD784217A, 784217AY
On execution of
LOCATION 0FH instruction
F F F F FH
F FEF FH
0 FEF FH
External memory
(928 KB)
1 8 0 0 0H
1 7 F F FH
F F F F F H Special
F F FDFH
Note 1
F F FD0H
FFF 0 0H
F FEF FH
General-purpose
registers (128 bytes)
Note 1
0 FE8 0H
0 FE 7 FH
function registers (SFR)
(256 bytes)
Internal RAM
(12,800 bytes)
FFE8 0H
F FE 7 FH
F CD 0 0 H
F CC F F H
Internal ROM
Data Sheet U14121EJ2V0DS00
(32,768 bytes)
1 0 0 0 0H
0 F F F FH
Special function registers
0 F FDFH
Note 1
0 F FD0H
(256 bytes)
0 FF 0 0H
0 FEF FH
0 F E 3 BH
(SFR)
0 FE0 6H
Macro service control word
area (54 bytes)
F F E 3 BH
FFE0 6H
Data area (512 bytes)
0 FD0 0H
0 FCF FH
Internal RAM
(12,800 bytes)
F FD0 0H
F FCF FH
External memory
(838,912 bytes)
Program/data area
(12,288 bytes)
0 CD 0 0 H
0 CC F F H
0 CD 0 0 H
F CD 0 0 H
2 F F F FH
1 0 0 0 0H
1 7 F F FH
Note 1
Note 2
0 F 0 F FH
Program/data area
Note 4
Note 3
0 1 0 0 0H
0 0 F F FH
CALLF entry
area (2 KB)
Internal ROM
(52,480 bytes)
0 0 8 0 0H
0 0 7 F FH
0 0 0 8 0H
0 0 0 7 FH
0 0 0 4 0H
0 0 0 3 FH
0 0 0 0 0H
0 0 0 0 0H
3 0 0 0 0H
2 F F F FH
CALLT table
area (64 bytes)
Vector table area
(64 bytes)
Internal ROM
(192 KB)
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode.
2. This 13,056-byte area can be used as internal ROM only when the LOCATION 0FH instruction is executed.
3. On execution of LOCATION 0H instruction: 183,552 bytes, on execution of LOCATION 0FH instruction: 196,608 bytes
27
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
Note 4
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
On execution of
LOCATION 0H instruction
28
Figure 6-5. Memory Map of µPD784218A, 784218AY
On execution of
LOCATION 0H instruction
On execution of
LOCATION 0FH instruction
F F F F FH
F FEF FH
0 FEF FH
External memory
(768 KB)
General-purpose
registers (128 bytes)
0 FE8 0H
0 FE 7 FH
4 0 0 0 0H
3 F F F FH
Data Sheet U14121EJ2V0DS00
1 0 0 0 0H
0 F F F FH
Special
0 F FDFH
Note 1
0 F FD0H
0 FF 0 0H
0 FEF FH
Internal ROM
(196,608 bytes)
0 F E 3 BH
function registers (SFR)
0 FE0 6H
(256 bytes)
(256 bytes)
Internal RAM
(12,800 bytes)
FFE8 0H
F FE 7 FH
Macro service control word
area (54 bytes)
function registers (SFR)
F CD 0 0 H
F CC F F H
F F E 3 BH
FFE0 6H
Data area (512 bytes)
0 FD0 0H
0 FCF FH
Internal RAM
(12,800 bytes)
F FD0 0H
F FCF FH
Note 1
External memory
(773,376 bytes)
Program/data area
(12,288 bytes)
0 CD 0 0 H
0 CC F F H
0 CD 0 0 H
F CD 0 0 H
3 F F F FH
1 0 0 0 0H
3 F F F FH
Note 2
0 CC F F H
Note 3
Program/data area
Note 4
0 1 0 0 0H
0 0 F F FH
CALLF entry
area (2 KB)
Internal ROM
(52,480 bytes)
0 0 8 0 0H
0 0 7 F FH
0 0 0 8 0H
0 0 0 7 FH
0 0 0 4 0H
0 0 0 3 FH
0 0 0 0 0H
0 0 0 0 0H
4 0 0 0 0H
3 F F F FH
CALLT table
area (64 bytes)
Vector table area
(64 bytes)
Internal ROM
(256 KB)
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode.
2. This 13,056-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
3. On execution of LOCATION 0H instruction: 249,088 bytes, on execution of LOCATION 0FH instruction: 262,144 bytes
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
Note 4
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Note 1
F F F F F H Special
F F FDFH
Note 1
F F FD0H
FFF 0 0H
F FEF FH
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
6.2 CPU Registers
6.2.1 General-purpose registers
Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can also be used in pairs as a 16-bit
register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24bit address specification registers.
Eight banks of these register sets are available and can be selected by using software or the context switching
function.
The general-purpose registers except the V, U, T, and W registers for address expansion are mapped to the
internal RAM.
Figure 6-6. General-Purpose Register Format
A (R1)
X (R0)
AX (RP0)
B (R3)
C (R2)
BC (RP1)
R5
R4
RP2
R7
R6
RP3
V
R9
R8
VP (RP4)
VVP (RG4)
U
R11
R10
T
UP (RP5)
UUP (RG5)
D (R13)
E (R12)
W
DE (RP6)
TDE (RG6)
H (R15)
L (R14)
8 banks
WHL (RG7)
HL (RP7)
Names in parentheses indicate absolute names.
Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers,
respectively, by setting the RSS bit of the PSW to 1.
However, use this function only for
recycling the program of the 78K/III Series.
Data Sheet U14121EJ2V0DS00
29
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
6.2.2 Control registers
(1) Program counter (PC)
The program counter is a 20-bit register whose contents are automatically updated when the program is
executed.
Figure 6-7. Format of Program Counter (PC)
19
0
PC
(2) Program status word (PSW)
This register holds the statuses of the CPU. Its contents are automatically updated when the program is
executed.
Figure 6-8. Format of Program Status Word (PSW)
PSWH
15
14
13
12
11
10
9
8
UF
RBS2
RBS1
RBS0
–
–
–
–
7
6
5
4
3
2
1
0
AC
IE
P/V
0
CY
PSW
S
PSWL
Z
RSS
Note
Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0,
except when the software for the 78K/III Series is used.
(3) Stack pointer (SP)
This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this
pointer.
Figure 6-9. Format of Stack Pointer (SP)
23
SP
30
0
20
0
0
0
0
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
6.2.3 Special function registers (SFRs)
The special function registers, such as the mode registers and control registers of the internal peripheral
hardware, are registers to which special functions are assigned. These registers are mapped to the 256-byte space
of addresses 0FF00H to 0FFFFHNote.
Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH
instruction.
Caution Do not access an address in this area to which no SFR is assigned. If such an address is
accessed by mistake, the µPD784218A may enter a deadlocked state. This deadlock state can be
cleared only by inputting the RESET signal.
Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows.
• Symbol ................................ Symbol indicating an SFR.
This symbol is reserved for NEC's assembler
(RA78K4). It can be used as an sfr variable by means of the #pragma sfr command
in the C compiler (CC78K4).
• R/W ..................................... Indicates whether the SFR is read-only, write-only, or read/write.
R/W: Read/write
R:
Read-only
W:
Write-only
• Bit units for manipulation ..... Bit units in which the value of the SFR can be manipulated.
SFRs that can be manipulated in 16-bit units can be described as the operand sfrp
of an instruction. To specify the address of this SFR, describe an even address.
SFRs that can be manipulated in 1-bit units can be described as the operand of a
bit manipulation instruction.
• After reset............................ Indicates the status of the register when the RESET signal has been input.
Data Sheet U14121EJ2V0DS00
31
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (1/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
16 Bits
0FF00H
Port 0
P0
R/W
√
√
−
0FF01H
Port 1
P1
R
√
√
−
0FF02H
Port 2
P2
R/W
√
√
−
0FF03H
Port 3
P3
√
√
−
0FF04H
Port 4
P4
√
√
−
0FF05H
Port 5
P5
√
√
−
0FF06H
Port 6
P6
√
√
−
0FF07H
Port 7
P7
√
√
−
0FF08H
Port 8
P8
√
√
−
0FF09H
Port 9
P9
√
√
−
0FF0AH
Port 10
P10
√
√
−
0FF0CH
Port 12
P12
√
√
−
0FF0DH
Port 13
P13
√
√
−
0FF10H
16-bit timer counter
TM0
R
−
−
√
Capture/compare register 00
(16-bit timer/event counter)
CR00
R/W
−
−
√
Capture/compare register 01
(16-bit timer/event counter)
CR01
−
−
√
After Reset
00HNote 2
0000H
0FF11H
0FF12H
0FF13H
0FF14H
0FF15H
0FF16H
Capture/compare control register 0
CRC0
√
√
−
0FF18H
16-bit timer mode control register
TMC0
√
√
−
0FF1AH
16-bit timer output control register
TOC0
√
√
−
0FF1CH
Prescaler mode register 0
PRM0
√
√
−
0FF20H
Port 0 mode register
PM0
√
√
−
√
−
0FF22H
Port 2 mode register
PM2
√
0FF23H
Port 3 mode register
PM3
√
√
−
0FF24H
Port 4 mode register
PM4
√
√
−
0FF25H
Port 5 mode register
PM5
√
√
−
0FF26H
Port 6 mode register
PM6
√
√
−
0FF27H
Port 7 mode register
PM7
√
√
−
0FF28H
Port 8 mode register
PM8
√
√
−
0FF29H
Port 9 mode register
PM9
√
√
−
0FF2AH
Port 10 mode register
PM10
√
√
−
0FF2CH
Port 12 mode register
PM12
√
√
−
0FF2DH
Port 13 mode register
PM13
√
√
−
00H
FFH
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION
0FH instruction is executed.
2. Because each port is initialized to input mode after reset, "00H" is not actually read. The output latch is
initialized to "0".
32
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (2/4)
AddressNote
Special Function Register (SFR) Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
16 Bits
0FF30H
Pull-up resistor option register 0
PU0
√
√
−
0FF32H
Pull-up resistor option register 2
PU2
√
√
−
0FF33H
Pull-up resistor option register 3
PU3
√
√
−
0FF37H
Pull-up resistor option register 7
PU7
√
√
−
0FF38H
Pull-up resistor option register 8
PU8
√
√
−
0FF3AH
Pull-up resistor option register 10
PU10
√
√
−
0FF3CH
Pull-up resistor option register 12
PU12
√
√
−
0FF40H
Clock output control register
CKS
√
√
−
0FF42H
Port function control register
PF2
√
√
−
0FF4EH
Pull-up resistor option register
PUO
√
√
−
0FF50H
8-bit timer counter 1
TM1
−
√
√
0FF51H
8-bit timer counter 2
TM2
−
√
0FF52H
Compare register 10 (8-bit timer/event counter 1) CR10 CR1W
0FF53H
Compare register 20 (8-bit timer/event counter 2) CR20
0FF54H
8-bit timer mode control register 1
TMC1 TMC1W
√
√
0FF55H
8-bit timer mode control register 2
TMC2
√
√
0FF56H
Prescaler mode register 1
PRM1 PRM1W
√
√
0FF57H
Prescaler mode register 2
PRM2
0FF60H
8-bit timer counter 5
TM5
0FF61H
8-bit timer counter 6
TM6
0FF62H
8-bit timer counter 7
TM7
0FF63H
8-bit timer counter 8
TM8
0FF64H
Compare register 50 (8-bit timer/event counter 5) CR50 CR5W
0FF65H
TM1W
R/W
R
R/W
−
√
−
√
√
√
−
√
−
√
−
√
−
√
−
√
Compare register 60 (8-bit timer/event counter 6) CR60
−
√
0FF66H
Compare register 70 (8-bit timer/event counter 7) CR70 CR7W
−
√
0FF67H
Compare register 80 (8-bit timer/event counter 8) CR80
−
√
0FF68H
8-bit timer mode control register 5
TMC5 TMC5W
√
√
0FF69H
8-bit timer mode control register 6
TMC6
√
√
0FF6AH
8-bit timer mode control register 7
TMC7 TMC7W
√
√
0FF6BH
8-bit timer mode control register 8
TMC8
√
√
0FF6CH
Prescaler mode register 5
PRM5 PRM5W
√
√
0FF6DH
Prescaler mode register 6
PRM6
√
√
0FF6EH
Prescaler mode register 7
PRM7 PRM7W
√
√
0FF6FH
Prescaler mode register 8
PRM8
√
√
0FF70H
Asynchronous serial interface mode register 1
ASIM1
√
√
0FF71H
Asynchronous serial interface mode register 2
ASIM2
0FF72H
Asynchronous serial interface status register 1
ASIS1
0FF73H
Asynchronous serial interface status register 2
ASIS2
TM5W
R
TM7W
R/W
R
After Reset
00H
0000H
√
√
√
√
√
√
√
√
√
√
√
−
√
√
−
√
√
−
√
√
−
00H
Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH
instruction is executed.
Data Sheet U14121EJ2V0DS00
33
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (3/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
16 Bits
After Reset
Transmit shift register 1
TXS1
W
−
√
−
Receive buffer register 1
RXB1
R
−
√
−
0FF75H
Transmit shift register 2
TXS2
W
−
√
−
RXB2
R
−
√
−
0FF76H
Baud rate generator control register 1
BRGC1
R/W
√
√
−
0FF77H
Baud rate generator control register 2
BRGC2
√
√
−
0FF7AH
Oscillation mode select register
CC
√
√
−
0FF80H
A/D converter mode register
ADM
√
√
−
0FF81H
A/D converter input select register
ADIS
√
√
−
0FF83H
A/D conversion result register
ADCR
R
−
√
−
Undefined
0FF84H
D/A conversion value setting register 0
DACS0
R/W
√
√
−
00H
0FF85H
D/A conversion value setting register 1
DACS1
√
√
−
0FF86H
D/A converter mode register 0
DAM0
√
√
−
0FF87H
D/A converter mode register 1
DAM1
√
√
−
0FF74H
Receive buffer register 2
0FF8CH
External bus type select register
EBTS
√
√
−
0FF90H
Serial operation mode register 0
CSIM0
√
√
−
0FF91H
Serial operation mode register 1
CSIM1
√
√
−
CSIM2
√
√
−
0FF92H
Serial operation mode register 2
0FF94H
Serial I/O shift register 0
SIO0
−
√
−
0FF95H
Serial I/O shift register 1
SIO1
−
√
−
0FF96H
Serial I/O shift register 2
SIO2
−
√
−
0FF98H
Real-time output buffer register L
RTBL
−
√
−
0FF99H
Real-time output buffer register H
RTBH
−
√
−
0FF9AH
Real-time output port mode register
RTPM
√
√
−
√
−
FFH
00H
0FF9BH
Real-time output port control register
RTPC
√
0FF9CH
Watch timer mode control register
WTM
√
√
−
0FFA0H
External interrupt rising edge enable register
EGP0
√
√
−
0FFA2H
External interrupt falling edge enable register
EGN0
√
√
−
0FFA8H
In-service priority register
ISPR
R
√
√
−
0FFA9H
Interrupt select control register
SNMI
R/W
√
√
−
0FFAAH
Interrupt mode control register
√
√
−
80H
0FFACH
Interrupt mask flag register 0L
MK0L
√
√
√
FFFFH
0FFADH
Interrupt mask flag register 0H
MK0H
√
√
√
√
√
√
IMC
0FFAEH
Interrupt mask flag register 1L
MK1L
0FFAFH
Interrupt mask flag register 1H
MK1H
0FFB0H
I2C bus control registerNote 2
0FFB2H
Prescaler mode register for serial clock
0FFB4H
Slave address register
MK0
MK1
√
IICC0
√
√
−
SPRM0
√
√
−
SVA0
√
√
−
00H
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION
0FH instruction is executed.
2. µPD784216AY/784218AY Subseries only
34
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (4/4)
AddressNote 1
Special Function Register (SFR) Name
0FFB6H
I2C bus status registerNote 2
0FFB8H
Serial shift register
0FFC0H
Standby control register
0FFC2H
Watchdog timer mode register
0FFC4H
Memory expansion mode register
0FFC7H
Programmable wait control register 1
0FFCEH
Clock status register
0FFCFH
Oscillation stabilization time specification register
0FFD0H to
0FFDFH
External SFR area
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
16 Bits
After Reset
IICS0
R
√
√
−
IIC0
R/W
√
√
−
STBC
−
√
−
WDM
−
√
−
00H
MM
√
√
−
20H
PWC1
PCS
R
OSTS
R/W
00H
30H
√
√
−
AAH
√
√
−
32H
00H
√
√
−
−
√
√
−
0FFE0H
Interrupt control register (INTWDTM)
WDTIC
√
√
−
0FFE1H
Interrupt control register (INTP0)
PIC0
√
√
−
0FFE2H
Interrupt control register (INTP1)
PIC1
√
√
−
0FFE3H
Interrupt control register (INTP2)
PIC2
√
√
−
0FFE4H
Interrupt control register (INTP3)
PIC3
√
√
−
0FFE5H
Interrupt control register (INTP4)
PIC4
√
√
−
0FFE6H
Interrupt control register (INTP5)
PIC5
√
√
−
0FFE7H
Interrupt control register (INTP6)
PIC6
√
√
−
0FFE8H
Interrupt control register (INTIIC0/INTCSI0)
CSIIC0
√
√
−
0FFE9H
Interrupt control register (INTSER1)
SERIC1
√
√
−
0FFEAH
Interrupt control register (INTSR1/INTCSI1)
SRIC1
√
√
−
0FFEBH
Interrupt control register (INTST1)
STIC1
√
√
−
0FFECH
Interrupt control register (INTSER2)
SERIC2
√
√
−
0FFEDH
Interrupt control register (INTSR2/INTCSI2)
SRIC2
√
√
−
0FFEEH
Interrupt control register (INTST2)
STIC2
√
√
−
0FFEFH
Interrupt control register (INTTM3)
TMIC3
√
√
−
0FFF0H
Interrupt control register (INTTM00)
TMIC00
√
√
−
0FFF1H
Interrupt control register (INTTM01)
TMIC01
√
√
−
0FFF2H
Interrupt control register (INTTM1)
TMIC1
√
√
−
0FFF3H
Interrupt control register (INTTM2)
TMIC2
√
√
−
0FFF4H
Interrupt control register (INTAD)
ADIC
√
√
−
0FFF5H
Interrupt control register (INTTM5)
TMIC5
√
√
−
0FFF6H
Interrupt control register (INTTM6)
TMIC6
√
√
−
0FFF7H
Interrupt control register (INTTM7)
TMIC7
√
√
−
√
−
0FFF8H
Interrupt control register (INTTM8)
TMIC8
√
0FFF9H
Interrupt control register (INTWT)
WTIC
√
√
−
0FFFAH
Interrupt control register (INTKR)
KRIC
√
√
−
−
43H
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION
0FH instruction is executed.
2. µPD784216AY/784218AY Subseries only
Data Sheet U14121EJ2V0DS00
35
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7. PERIPHERAL HARDWARE FUNCTIONS
7.1 Ports
The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the
function of each port. Ports 0, 2 through 8, 10, and 12 can be connected to on-chip pull-up resistors by means of
software when in input mode.
Figure 7-1. Port Configuration
Port 7



Pprt 8







Port 9







Port 10



Port 12







Port 13



P70
P00
P06
P87
P90
P10 to P17
P20
P95
P100
P103
P120
P127
P130
P27
P30
P37
P40
P131
P47
P50
P57
P60
P67
36



 Port 0



P72
P80
Data Sheet U14121EJ2V0DS00
8
Port 1



 Port 2






 Port 3






 Port 4






 Port 5






 Port 6



µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 7-1. Port Functions
Port Name
Pin Name
Function
Specification of Pull-up Resistor
Connection by Software
Port 0
P00 to P06
• Input/output can be specified in 1-bit units
Port 1
P10 to P17
• Input port
Port 2
P20 to P27
• Input/output can be specified in 1-bit units
Can be specified in 1-bit units
Port 3
P30 to P37
• Input/output can be specified in 1-bit units
Can be specified in 1-bit units
Port 4
P40 to P47
• Input/output can be specified in 1-bit units
• LEDs can be driven directly
Can be specified in 1-port units
Port 5
P50 to P57
• Input/output can be specified in 1-bit units
• LEDs can be driven directly
Can be specified in 1-port units
Port 6
P60 to P67
• Input/output can be specified in 1-bit units
Can be specified in 1-port units
Port 7
P70 to P72
• Input/output can be specified in 1-bit units
Can be specified in 1-bit units
Port 8
P80 to P87
• Input/output can be specified in 1-bit units
Can be specified in 1-bit units
Port 9
P90 to P95
• N-ch open-drain I/O port
• Input/output can be specified in 1-bit units
• LEDs can be driven directly
Port 10
P100 to P103
• Input/output can be specified in 1-bit units
Can be specified in 1-bit units
Port 12
P120 to P127
• Input/output can be specified in 1-bit units
Can be specified in 1-bit units
Port 13
P130, P131
• Input/output can be specified in 1-bit units
Can be specified in 1-bit units
−
−
−
7.2 Clock Generator
An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider. If
high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to
reduce the current consumption.
Figure 7-2. Block Diagram of Clock Generator
XT1
XT2
Subsystem
fXT
clock
oscillator
Watch timer,
clock output function
IDLE
controller
fX
Frequency
divider
fX
2
Clock to
peripheral hardware
Prescaler
fXX
fXX
2
fXX
22
fXX
23
STOP or bit 2 (MCK)
of the standby control
register (STBC) is set
to 1 when the subclock
is selected as the CPU
clock
Selector
X2
Main system
clock
oscillator
Selector
Prescaler
X1
STOP, IDLE
controller
HALT
controller
CPU
clock
(fCPU)
Internal system
clock
(fCLK)
Data Sheet U14121EJ2V0DS00
37
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 7-3. Example of Using Main System Clock Oscillator
(1) Crystal/ceramic oscillation
(2) External clock
X2
X2
X1
VSS
External
clock
µ PD74HCU04
Crystal resonator
or
ceramic resonator
X1
Figure 7-4. Example of Using Subsystem Clock Oscillator
(1) Crystal oscillation
32.768
kHz
(2) External clock
VSS
XT2
XT2
External
clock
XT1
Caution
XT1
µPD74HCU04
When using the main system clock and subsystem clock oscillator, wire as follows in the area
enclosed by the broken lines in Figures 7-3 and 7-4 to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the subsystem clock oscillator has a low amplification factor to reduce the current
consumption.
38
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.3 Real-Time Output Port
The real-time output function is to transfer data set in advance to the real-time output buffer register to the output
latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device.
The pins that output the data to the external device constitute a port called a real-time output port.
Because the real-time output port can output signals without jitter, it is ideal for controlling a stepper motor.
Figure 7-5. Block Diagram of Real-Time Output Port
Internal bus
Real-time output port
control register (RTPC)
RTPOE
BYTE
EXTR
INTP2TRG
INTTM1
Output trigger
Controller
INTTM2
High-order 4 bits of
real-time output
buffer register
(RTBH)
Low-order 4 bits of
real-time output
buffer register
(RTBL)
Real-time output
port mode register
(RTPM)
Port 12 output latch
Real-time output port output latch
P127······································ P120
RTP7······································ RTP0
RTPOE bit
P12n/RTPn pin output (n = 0 to 7)
P127/
P120/
RTP7······································ RTP0
Data Sheet U14121EJ2V0DS00
39
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.4 Timer/Event Counter
One unit of 16-bit timer/event counter and six 8-bit timer/event counters are provided.
Because a total of eight interrupt requests are supported, these timer/event counters can be used as eight
timer/counters.
Table 7-2. Operations of Timers
Name
Item
Count width
Operation mode
8 bits
−
16 bits
√
Interval timer
√
√
√
√
√
√
√
√
1 ch
1 ch
1 ch
1 ch
1 ch
1 ch
√
√
√
√
√
√
√
1 ch
1 ch
1 ch
1 ch
1 ch
1 ch
1 ch
PPG output
√
−
−
−
−
−
−
PWM output
−
√
√
√
√
√
√
Square wave output
√
√
√
√
√
√
√
One-shot pulse output
√
−
−
−
−
−
−
2 inputs
−
−
−
−
−
−
2
1
1
1
1
1
1
Timer output
Pulse width measurement
Number of interrupt requests
40
√
1 ch
External event counter
Function
8-Bit
8-Bit
8-Bit
8-Bit
8-Bit
8-Bit
16-Bit
Timer/
Timer/
Timer/
Timer/
Timer/
Timer/
Timer/
Event
Event
Event
Event
Event
Event
Event
Counter Counter 1 Counter 2 Counter 5 Counter 6 Counter 7 Counter 8
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 7-6. Block Diagram of Timer/Event Counters
16-bit timer/event counter
Clear
Selector
fXX/4
fXX/16
INTTM3
16-bit timer counter (TM0)
16
INTTM00
16-bit capture/compare register 00
(CR00)
16
INTTM01
TI00
16-bit capture/compare register 01
(CR01)
Edge
detector
Output controller
Edge
detector
Selector
TI01
TO0
8-bit timer/event counter 1, 5, 7
fXX/22
Clear
fXX/25
fXX/27
8-bit timer counter n
(TMn)
Output
controller
TOn
8
fXX/29
TIn
OVF
Edge
detector
Selector
fXX/24
Selector
fXX/23
8-bit compare register n0
(CRn0)
INTTMn
INTTMn + 1
Remarks 1. n = 1, 5, 7
2. OVF: Overflow flag
8-bit timer/event counter 2, 6, 8
TMn – 1
fXX/22
Clear
fXX/24
5
fXX/2
Selector
fXX/23
7
fXX/2
8-bit timer counter n
(TMn)
OVF
Output
controller
TOn
8
fXX/29
TIn
Edge detector
8-bit compare register n0
(CRn0)
INTTMn
Remarks 1. n = 2, 6, 8
2. OVF: Overflow flag
Data Sheet U14121EJ2V0DS00
41
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.5 A/D Converter
An A/D converter converts an analog signal input into a digital signal. This microcontroller is provided with an A/D
converter with a resolution of 8 bits and eight channels (ANI0 to ANI7).
This A/D converter is of successive approximation type and the result of conversion is stored in an 8-bit A/D
conversion result register (ADCR).
The A/D converter can be started in the following two ways:
• Hardware start
Conversion is started by trigger input (P03).
• Software start
Conversion is started by setting the A/D converter mode register (ADM).
One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started by
means of hardware start, conversion is stopped after it has been completed. When conversion is started by means
of software start, A/D conversion is repeatedly executed. Each time conversion has been completed, an interrupt
request (INTAD) is generated.
Figure 7-7. Block Diagram of A/D Converter
Series resistor string
AVDD
ANI0
AVREF0
ANI2
ANI4
Voltage comparator
Selector
ANI3
ANI5
Tap selector
Sample & hold circuit
ANI1
ANI6
AVSS
ANI7
INTP3/P03
Successive approximation
register (SAR)
Edge
detector
Edge
detector
Controller
INTAD
A/D conversion result register
(ADCR)
INTP3
Internal bus
42
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.6 D/A Converter
A D/A converter converts a digital signal input into an analog signal. This microcontroller is provided with a
voltage output type D/A converter with a resolution of 8 bits and two channels.
The conversion method is of R-2R resistor ladder type.
D/A conversion is started by setting DACE0 of D/A converter mode register 0 (DAM0) and DACE1 of D/A
converter mode register 1 (DAM1).
The D/A converter operates in the following two modes:
• Normal mode
The converter outputs an analog voltage immediately after it has completed D/A conversion.
• Real-time output mode
The converter outputs an analog voltage in synchronization with an output trigger after it has completed D/A
conversion.
Figure 7-8. Block Diagram of D/A Converter
DACS0
8
2R
ANO0
AVREF1
2R
R
Selector
R
2R
DACS1
2R
8
2R
ANO1
2R
R
Selector
R
2R
AVSS
2R
Data Sheet U14121EJ2V0DS00
43
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.7 Serial Interface
Three independent serial interface channels are provided.
• Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2
• Clocked serial interface (CSI) × 1
• 3-wire serial I/O (IOE)
• I2C bus interface (I2C) (µPD784216AY/784218AY Subseries only)
Therefore, communication with an external system and local communication within the system can be
simultaneously executed (refer to Figure 7-9).
Figure 7-9. Example of Serial Interface
(a) UART + I2C
(b)
µPD784218AY (master)
VDD
VDD
µ PD4711A
[UART]
RS-232-C
driver/receiver
SDA0
RxD1
µPD780078Y (slave)
[I2C]
SDA
SCL
SCL0
TxD1

 Port

µPD780308Y (slave)
µ PD4711A
SDA
[UART]
RS-232-C
driver/receiver
LCD
SCL
RxD2
TxD2

 Port

(b) UART + 3-wire serial I/O
µPD784218AY (master)
µ PD4711A
SO1
[UART]
RxD2
RS-232-C
driver/receiver
TxD2



Port
µ PD753106 (slave)
[3-wire serial I/O]
SI1
SO
SCK1
INTPm
SCK
Note
Port
Note Handshake line
44
SI
Data Sheet U14121EJ2V0DS00
Port
INT
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
Two channels of serial interfaces for which an asynchronous serial interface mode and a 3-wire serial I/O mode
can be selected are provided.
(1) Asynchronous serial interface mode
In this mode, data of 1 byte following the start bit is transmitted or received.
Because an on-chip baud rate generator is provided, a wide range of baud rates can be set.
Moreover, the clock input to the ASCK pin can be divided to define a baud rate.
When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can also be
obtained.
Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode
Internal bus
8
Receive buffer register
1, 2 (RXB1, RXB2)
8
8
RxD1, RxD2
Receive shift register
1, 2 (RX1, RX2)
Transmit shift register
1, 2 (TXS1, TXS2)
TxD1, TxD2
Receive control
parity check
INTSR1,
INTSR2
Transmit control
parity addition
INTST1,
INTST2
Baud rate generator
5-bit counter × 2 transmit/
receive clock generation
Selector
fXX to fXX/25
ASCK1, ASCK2
Data Sheet U14121EJ2V0DS00
45
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(2) 3-wire serial I/O mode
In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in
synchronization with this clock.
This mode is used to communicate with a device having a conventional clocked serial interface. Basically,
communication is established by using three lines: serial clocks (SCK1 and SCK2), serial data inputs (SI1 and
SI2), and serial data outputs (SO1 and SO2).
To connect two or more devices, a handshake line is
necessary.
Figure 7-11. Block Diagram in 3-Wire Serial I/O Mode
Internal bus
8
Serial I/O shift register
1, 2 (SIO1, SIO2)
SI1, SI2
SO1, SO2
SCK1, SCK2
46
Serial clock
counter
Interrupt
generator
INTCSI1,
INTCSI2
Serial clock
controller
Selector
TO2
fXX/8
fXX/16
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.7.2 Clocked serial interface (CSI)
In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in
synchronization with this clock.
(1) 3-wire serial I/O mode
This mode is to communicate with devices having a conventional clocked serial interface.
Basically, communication is established in this mode with three lines: serial clock (SCK0) serial data input
(SI0), and serial data output (SO0) lines.
Generally, a handshake line is necessary to check the reception status.
Figure 7-12. Block Diagram in 3-Wire Serial I/O Mode
Internal bus
8
SI0
Serial I/O shift register 0
(SIO0)
SO0
SCK0
Serial clock
counter
Interrupt
generator
INTCSI0
Serial clock
controller
Selector
TO2
fXX/8
fXX/16
Data Sheet U14121EJ2V0DS00
47
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(2) I2C bus (Inter IC) bus mode (supporting multimaster) (µPD784216AY/784218AY Subseries only)
This mode is for communication with devices conforming to the I2C bus format.
This mode is for transferring 8-bit data between two or more devices by using two lines: serial clock (SCL0)
and serial data bus (SDA0) lines.
During transmission, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus.
During reception, these data are automatically detected by hardware.
Figure 7-13. Block Diagram of I2C Bus Mode
Internal bus
8
8
Direction controller
Slave address register
(SVA0)
Wake-up
controller
8
SDA0
Serial I/O shift
register 0 (SIO0)
Output latch
Acknowledge
generator
Start condition/acknowledge
detector
Stop condition
detector
SCL0
INTIIC0
Selector
TO2/18 to TO2/68
fXX/24 to fXX/178
Serial clock counter
Serial clock
controller
48
Interrupt
generator
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.8 Clock Output Function
Clocks of the following frequencies can be output as clock output.
• 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 MHz
(@12.5 MHz operation with main system clock)
• 32.768 kHz (@32.768 kHz operation with subsystem clock)
Figure 7-14. Block Diagram of Clock Output Function
fXX
fXX/2
fXX/23
fXX/24
fXX/25
Selector
fXX/22
Synchronization
circuit
Output controller
PCL
6
fXX/2
fXX/27
fXT
7.9 Buzzer Output Function
Clocks of the following frequencies can be output as buzzer output.
• 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (@12.5 MHz operation with main system clock)
fXX/210
fXX/211
fXX/212
fXX/213
Selector
Figure 7-15. Block Diagram of Buzzer Output Function
Output controller
Data Sheet U14121EJ2V0DS00
BUZ
49
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.10 Edge Detection Function
The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP6) are used not only to input interrupt requests
but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input
signal, they have a function to detect an edge. Moreover, a noise elimination function is also provided to prevent
erroneous detection due to noise.
Pin Name
Detectable Edge
Noise Elimination
Either or both of rising and falling edges
NMI
By analog delay
−
INTP0 to INTP6
7.11 Watch Timer
The watch timer has the following functions:
• Watch timer
• Interval timer
The watch timer and interval timer functions can be used at the same time.
(1) Watch timer
The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds by
using the 32.768 kHz subsystem clock.
(2) Interval timer
The interval timer generates an interrupt request (INTTM3) at predetermined time intervals.
Prescaler
fW
25
fW
26
fW
27
fW
28
5-bit counter
fW
29
INTWT
fW
25
Selector
fW
24
fW
214
Selector
fXT
fW
Selector
fXX/27
Selector
Figure 7-16. Block Diagram of Watch Timer
INTTM3
To 16-bit timer/counter
50
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.12 Watchdog Timer
A watchdog timer is provided to detect a CPU runaway. This watchdog timer generates a non-maskable or
maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the
watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input
from the NMI pin takes precedence can be specified.
Figure 7-17. Block Diagram of Watchdog Timer
fCLK
Timer
fCLK/221
RUNNote
HALT
IDLE
STOP
fCLK/219
Selector
fCLK/220
INTWDT
fCLK/217
Note Write “+” to bit 7 (RUN) of the watchdog timer (WDM)
Remark fCLK: Internal system clock (fXX to fXX/8)
Data Sheet U14121EJ2V0DS00
51
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
8. INTERRUPT FUNCTIONS
The three types of interrupt request servicing shown in Table 8-1 can be selected by program.
Table 8-1. Servicing of Interrupt Request
Servicing Mode
Entity of Servicing
Vectored interrupt
Servicing
Software
Context switching
Macro service
Firmware
Contents of PC and PSW
Branches and executes servicing routine
(servicing is arbitrary)
Saves to and restores from
stack
Automatically switches register bank,
branches and executes servicing routine
(servicing is arbitrary)
Saves to or restores from
fixed area in register bank
Executes data transfer between memory
and I/O (servicing is fixed)
Retained
8.1 Interrupt Sources
Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 29 types of sources,
execution of the BRK instruction, BRKCS instruction, or an operand error.
The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt
servicing and so that which of the two or more interrupts that simultaneously occur should be serviced first can be
determined. When the macro service function is used, however, nesting always proceeds.
The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having
the same priority, are simultaneously generated (refer to Table 8-2).
Table 8-2. Interrupt Sources (1/2)
Type
Default
Priority
−
Software
−
Non-maskable
Maskable
52
Source
Name
Trigger
BRK instruction
Instruction execution
BRKCS instruction
Instruction execution
Operand error
If result of exclusive OR between operands byte
and byte is not FFH when “MOV STBC, #byte”
instruction, “MOV WDM, #byte” instruction, or
LOCATION instruction is executed
Internal/
External
Macro
Service
−
−
−
NMI
Pin input edge detection
External
INTWDT
Overflow of watchdog timer
Internal
0 (highest)
INTWDTM
Overflow of watchdog timer
Internal
1
INTP0
Pin input edge detection
External
2
INTP1
3
INTP2
4
INTP3
5
INTP4
6
INTP5
7
INTP6
8
INTIIC0
INTCSI0
End of 3-wire transfer by CSI0
9
INTSER1
Occurrence of UART reception error in ASI1
2
End of I C bus transfer by CSI0
Data Sheet U14121EJ2V0DS00
Internal
√
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 8-2. Interrupt Sources (2/2)
Type
Maskable
Default
Priority
10
Source
Name
Trigger
INTSR1
End of UART reception by ASI1
INTCSI1
End of 3-wire transfer by CSI1
11
INTST1
End of UART transmission by ASI1
12
INTSER2
Occurrence of UART reception error in ASI2
13
INTSR2
End of UART reception by ASI2
INTCSI2
End of 3-wire transfer by CSI2
14
INTST2
End of UART transmission by ASI2
15
INTTM3
Reference time interval signal from watch timer
16
INTTM00
Signal indicating match between 16-bit timer
counter and capture/compare register (CR00)
17
INTTM01
Signal indicating match between 16-bit timer
counter and capture/compare register (CR01)
18
INTTM1
Occurrence of match signal of 8-bit timer/event
counter 1
19
INTTM2
Occurrence of match signal of 8-bit timer/event
counter 2
20
INTAD
End of conversion by A/D converter
21
INTTM5
Occurrence of match signal of 8-bit timer/event
counter 5
22
INTTM6
Occurrence of match signal of 8-bit timer/event
counter 6
23
INTTM7
Occurrence of match signal of 8-bit timer/event
counter 7
24
INTTM8
Occurrence of match signal of 8-bit timer/event
counter 8
25
INTWT
Overflow of watch timer
26 (lowest)
INTKR
Detection of falling edge of port 8
Internal/
External
Macro
Service
Internal
√
External
Remarks 1. ASI: Asynchronous Serial Interface
CSI: Clocked Serial Interface
2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and
maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use.
Data Sheet U14121EJ2V0DS00
53
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
8.2 Vectored Interrupt
Execution branches to a servicing routine by using the memory contents of a vector table address corresponding
to the interrupt source as the address of the branch destination.
So that the CPU performs interrupt servicing, the following operations are performed:
• On branching: Saves the status of the CPU (contents of PC and PSW) to stack
• On returning:
Restores the status of the CPU (contents of PC and PSW) from stack
To return to the main routine from an interrupt service routine, the RETI instruction is used.
The branch destination address is in a range of 0 to FFFFH.
Table 8-3. Vector Table Address
Interrupt Source
Vector Table Address
Interrupt Source
Vector Table Address
BRK instruction
003EH
INTST1
001CH
TRAP0 (operand error)
003CH
INTSER2
001EH
NMI
0002H
INSR2
0020H
INTWDT (non-maskable)
0004H
INTCSI2
INTWDTM (maskable)
0006H
INTST2
0022H
INTP0
0008H
INTTM3
0024H
INTP1
000AH
INTTM00
0026H
INTP2
000CH
INTTM01
0028H
INTP3
000EH
INTTM1
002AH
INTP4
0010H
INTTM2
002CH
INTP5
0012H
INTAD
002EH
INTP6
0014H
INTTM5
0030H
INTIIC0
0016H
INTTM6
0032H
INTTM7
0034H
INTCSI0
INTSER1
0018H
INTTM8
0036H
INTSR1
001AH
INTWT
0038H
INTKR
003AH
INTCSI1
54
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
8.3 Context Switching
When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register
bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in
advance in the register bank, while at the same time stacking the current contents of the program counter (PC) and
program status word (PSW) to the register bank.
The branch address is in a range of 0 to FFFFH.
Figure 8-1. Context Switching Operation When Interrupt Request Is Generated
Register bank
(0 to 7)
0000B
<7> Transfer
Register bank n (n = 0 to 7)
PC19-16
PC15-0
<2> Save
(Bits 8 to 11 of
temporary register)
<6> Exchange
<5> Save
Temporary register
<1> Save
A
X
B
C
R5
R4
R7
R6
V
VP
U
UP
T
D
E
W
H
L
<3> Switching of register bank
(RBS0 to RBS2 ← n)
<4> RSS ← 0
IE ← 0
PSW
Data Sheet U14121EJ2V0DS00
55
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
8.4 Macro Service
This function is to transfer data between memory and a special function register (SFR) without intervention by the
CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers
data without loading it.
Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high
speeds.
Figure 8-2. Macro Service
Read
CPU
Memory
Write
Write
Macro service
controller
Internal bus
56
Data Sheet U14121EJ2V0DS00
SFR
Read
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
8.5 Application Example of Macro Service
(1) Serial interface transmission
Transmit data storage buffer (memory)
Data n
Data n – 1
Data 2
Data 1
Internal bus
TxD1, TxD2
Transmit shift register TXS1, TXS2 (SFR)
Transmit control
INTST1, INTST2
Each time macro service requests INTST1 and INTST2 are generated, the next transmit data is transferred
from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the
transmit data storage buffer has become empty), vectored interrupt requests INTST1 and INTST2 are
generated.
(2) Serial interface reception
Receive data storage buffer (memory)
Data n
Data n – 1
Data 2
Data 1
Internal bus
Receive buffer register RXB1, RXB2 (SFR)
RxD1, RxD2
Receive shift register
Receive control
INTSR1, INTSR2
Each time macro service requests INTSR1 and INTSR2 are generated, the receive data is transferred from
RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data
storage buffer has become full), vectored interrupt requests INTSR1 and INTSR2 are generated.
Data Sheet U14121EJ2V0DS00
57
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
9. LOCAL BUS INTERFACE
The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory
space of 1 MB (refer to Figure 9-1).
Figure 9-1. Example of Local Bus Interface
(a) Multiplexed bus mode
VDD
µ PD784218A
SRAM
CS
Data bus
RD
OE
WR
WE
I/O1 to I/O8
Address bus
A8 to A19
A0 to A19
Address latch
ASTB
LE
Q0 to Q7
D0 to D7
OE
AD0 to AD7
(b) Separate bus mode
µ PD784218A
VDD
SRAM
CS
OE
RD
WR
Address bus
A0 to A19
AD0 to AD7
58
Data Sheet U14121EJ2V0DS00
WE
I/O1 to I/O8
A0 to A19
Data bus
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
9.1 Memory Expansion
External program memory and data memory can be connected in two stages: 256 KB and 1 MB.
To connect the external memory, ports 4 through 6 and port 8 are used.
The external memory can be connected in the following two modes:
• Multiplexed bus mode: The external memory is connected by using a time-division address/data bus. The
number of ports used when the external memory is connected can be reduced in this
mode.
• Separate bus mode:
The external memory is connected by using an address bus and data bus independent
of each other. Because an external latch circuit is not necessary, this mode is useful for
reducing the number of components and mounting area on the printed wiring board.
9.2 Programmable Wait
Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active.
In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address
decode time.
Data Sheet U14121EJ2V0DS00
59
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
10. STANDBY FUNCTION
This function is to reduce the power consumption of the chip, and can be used in the following modes:
• HALT mode:
Stops supply of the operating clock to the CPU. This mode is used in
combination with the normal operation mode for intermittent operation to
reduce the average power consumption.
• IDLE mode:
Stops the entire system except for the oscillator, which continues
operating. The power consumption in this mode is close to that in the
STOP mode.
However, the time required to restore the normal program operation
from this mode is almost the same as that from the HALT mode.
• STOP mode:
Stops the main system clock and thereby stops all the internal
operations of the chip.
Consequently, the power consumption is
minimized with only leakage current flowing.
• Low power consumption mode:
The main system clock is stopped and the subsystem clock is used as
the system clock. The CPU can operate on the subsystem clock to
reduce the current consumption.
• Low power consumption HALT mode: This is a standby function in the low power consumption mode and
stops the operation clock of the CPU, to reduce the power consumption
of the entire system.
• Low power consumption IDLE mode:
This is a standby function in the low power consumption mode and
stops the entire system except the oscillator, to reduce the power
consumption of the entire system.
These modes are programmable.
The macro service can be started from the HALT mode or low power consumption HALT mode. After macro
service processing is executed, the system returns to the HALT mode again.
The transition of the standby status is shown in Figure 10-1.
60
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 10-1. Standby Function State Transitions
t
es
qu s
re end
ice sing s
rv
se ces nd
ro pro e e
ac ime rvic
M
se
e-t
On cro
a
M
On
e-t
Ma ime
cro pro
ce
se
ss
r vi
ing
ce
req en
ue ds
st
Macro
service
ET
ES
R
Interrupt
request for
masked interrupt
t
pu
in
Low
con pow
sum er
ptio
Retu
nm
rn to
ode
norm
set
al o
pera
tion
Low power consumption
Low
Low power consumption HALT mode set Low power
IDLE mode set
Low power
power
consumption
consumption
NMI, INTP0 to INTP6 input,
mode
consumption
Note
2
IDLE mode
(Subsystem
HALT mode
INTWT, key return interrupt
Interrupt requestNote 1
clock operation)
(Standby)
(Standby)
Ti
SE
RE
Interrupt
request for
masked interrupt
t
npu
Macro service request
One-time processing ends
Macro service ends
Macro
service
STOP
(Standby)
Interrupt
request for
masked
interrupt
IDLE
(Standby)
Interrupt
request for
masked
interrupt
Interrupt
request for
masked
interrupt
RE
rv
ice
re
oc
es que
sin
st
g
en
ds
se
pr
ro
e
tim
ac
t
T
ET
t
pu
in
2
HALT
(Standby)
pu
SE
NM
RE
SE
INT I, IN
Ti
T
WT P0
np
,k
ut
t
ey o IN
ret TP
urn 6 i
int npu
err t,
up N
t ote
e-
M
On
se
t
es
qu
re
t
pt npu
ru
er ET i t
Int
S
se
RE ALT
H
t
P
O
ST
NM
ke I, I
ID
y r NT
LE
etu P0
se
rn
t
t
int o IN
er TP
ru
6
pt No in
te pu
2
t, I
NT
RESET inpu
W
t
T
,
Normal
operation
(Main system
clock
operation)
in
S
RE
Wait for
stable
oscillation
Notes 1. Only unmasked interrupt requests
2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87)
Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby
(HALT mode/STOP mode/IDLE mode).
Data Sheet U14121EJ2V0DS00
61
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
11. RESET FUNCTION
When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized
(reset). During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the
current consumption of the entire system can be reduced.
When the RESET signal goes high, the reset status is cleared. And after the oscillation stabilization time (84.0 ms
at 12.5 MHz operation) elapses, the contents of the reset vector table are set to the program counter (PC), execution
branches to an address set to the PC, and program execution is started from that branch address. Therefore, the
program can be reset and started from any address.
Figure 11-1. Oscillation of Main System Clock During Reset Period
Main system clock
oscillator
Oscillation is unconditionally
stopped during reset period
fCLK
RESET input
Oscillation stabilization time
The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise.
Figure 11-2. Acknowledgement of Reset Signal
Time until clock
starts oscillating
Analog delay
Analog delay
RESET input
Internal reset signal
Internal clock
62
Data Sheet U14121EJ2V0DS00
Analog
delay
Oscillation
stabilization
time
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
12. INSTRUCTION SET
(1) 8-bit instructions (instructions in parentheses are combinations realized by describing A as r)
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC,
CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC
Table 12-1. Instruction List by 8-Bit Addressing
Second Operand
#byte
A
r
saddr
r'
saddr'
sfr
!addr16
!!addr24
First Operand
A
(MOV)
ADD
Note 1
(MOV)
(XCH)
MOV
ADD
Note 1
Note 6
(XCH)
XCH
Note 1
r
Note 6
(MOV)
MOV
Note 1
Notes 1, 6
MOV
XCH
Note 1
Note 1
ADD
(MOV)
MOV
MOV
MOV
MOV
(XCH)
XCH
XCH
XCH
XCH
ADD
Note 1
[WHL−]
(XCH)
(ADD)
Note 1
PSWL
PSWH
(MOV)
(ADD)
ADD
[saddrp]
[%saddrg]
(XCH)
(ADD)
Note 1
[WHL+]
MOV
(ADD)
(ADD)
r3
mem
ADD
ADD
MOV
Note 2
None
n
(MOV)
(XCH)
Note 1
Note 1
(ADD)
ROR
Note 3
MULU
DIVUW
Note 1
INC
DEC
saddr
Note 6
(MOV)
MOV
ADD
Note 1
Note 1
(ADD)
MOV
ADD
Note 1
MOV
INC
XCH
DEC
ADD
sfr
MOV
ADD
!addr16
MOV
Note 1
MOV
Note 1
DBNZ
MOV
Note 1
PUSH
Note 1
(ADD)
ADD
(MOV)
MOV
POP
Note 1
!!addr24
ADD
mem
MOV
[saddrp]
ADD
Note 1
[%saddrg]
mem3
ROR4
ROL4
MOV
r3
MOV
PSWL
PSWH
B, C
DBNZ
STBC, WDM
[TDE+]
[TDE−]
MOV
Note 6
(MOV)
MOVBK
Note 5
Note 1
(ADD)
Note 4
MOVM
Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD.
2. Either the second operand is not used, or the second operand is not an operand address.
3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR.
4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of
MOVM.
5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of
MOVBK.
6. The code length of some instructions having saddr2 as saddr in this combination is short.
Data Sheet U14121EJ2V0DS00
63
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(2) 16-bit instructions (instructions in parentheses are combinations realized by describing AX as rp)
MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,
POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
Table 12-2. Instruction List by 16-Bit Addressing
Second Operand
#word
AX
rp
saddrp
rp'
saddrp'
sfrp
!addr16
ADDW
Note 1
MOVW
ADDW
Note 1
(MOVW)
(MOVW)
(XCHW)
(XCHW)
(XCHW)
Note 1
Notes 1, 3
MOVW
ADDW
!addr16
Note 1
MOVW
(MOVW) MOVW
(MOVW)
(XCHW)
XCHW
Note 2
None
(XCHW)
(ADDW)
(MOVW)
MOVW
MOVW
MOVW
(XCHW)
XCHW
XCHW
XCHW
Note 3
(MOVW)
Note 1
(ADDW)
ADDW
Note 1
MOVW
ADDW
Note 1
ADDW
MOVW
Note 1
XCHW
Note 1
(ADDW)
ADDW
MOVW
SHRW
MULU
SHLW
INCW
Note 1
DECW
INCW
XCHW
DECW
Note 1
MOVW
Note 1
PUSH
Note 1
(ADDW)
ADDW
(MOVW)
MOVW
Note 4
MOVW
ADDW
sfrp
MOVW
(ADDW)
Note 1
MOVW
Note 1
Note 3
(ADD)
(ADDW)
ADDW
Note 3
(MOVW)
Note 1
saddrp
n
[%saddrg]
(MOVW)
rp
byte
!!addr24 [saddrp]
First Operand
AX
[WHL+]
mem
POP
MOVTBLW
!!addr24
MOVW
mem
[saddrp]
[%saddrg]
PSW
PUSH
POP
SP
ADDWG
SUBWG
post
PUSH
POP
PUSHU
POPU
[TDE+]
(MOVW)
SACW
byte
MACW
MACSW
Notes 1. The operands of SUBW and CMPW are the same as that of ADDW.
2. Either the second operand is not used, or the second operand is not an operand address.
3. The code length of some instructions having saddrp2 as saddrp in this combination is short.
4. The operands of MULUW and DIVUX are the same as that of MULW.
64
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(3) 24-bit instructions (instructions in parentheses are combinations realized by describing WHL
as rg)
MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
Table 12-3. Instruction List by 24-Bit Addressing
Second Operand
#imm24
WHL
rg
saddrg
!!addr24
mem1
[%saddrg]
SP
Note
None
rg'
First Operand
WHL
rg
(MOVG)
(MOVG)
(MOVG)
(MOVG)
(ADDG)
(ADDG)
(ADDG)
ADDG
(SUBG)
(SUBG)
(SUBG)
SUBG
MOVG
(MOVG)
MOVG
MOVG
MOVG
MOVG
INCG
MOVG
(MOVG)
MOVG
ADDG
(ADDG)
ADDG
DECG
SUBG
(SUBG)
SUBG
PUSH
POP
saddrg
(MOVG)
MOVG
!!addr24
(MOVG)
MOVG
mem1
MOVG
[%saddrg]
MOVG
SP
MOVG
MOVG
INCG
DECG
Note Either the second operand is not used, or the second operand is not an operand address.
Data Sheet U14121EJ2V0DS00
65
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(4) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
Table 12-4. Instruction List by Bit Manipulation Instruction Addressing
Second Operand
CY
First Operand
CY
Note
None
saddr.bit sfr.bit
/saddr.bit /sfr. bit
A.bit X.bit
/A.bit /X.bit
PSWL.bit PSWH.bit
/PSWL.bit /PSWH.bit
mem2.bit
/mem2.bit
!addr16.bit !!addr24.bit
/!addr16.bit /!!addr24.bit
MOV1
AND1
NOT1
AND1
OR1
SET1
OR1
CLR1
XOR1
saddr.bit
MOV1
NOT1
sfr.bit
SET1
A.bit
CLR1
X.bit
BF
PSWL.bit
BT
PSWH.bit
BTCLR
mem2.bit
BFSET
!addr16.bit
!!addr24.bit
Note Either the second operand is not used, or the second operand is not an operand address.
66
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(5) Call and return/branch instructions
CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC,
BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Table 12-5. Instruction List by Call and Return/Branch Instruction Addressing
Operand of Instruction
$addr20 $!addr20 !addr16
!!addr20
rp
rg
[rp]
[rg]
!addr11
[addr5]
RBn
None
Address
BC
Basic instruction
Note
BR
Compound instruction
CALL
CALL
CALL
CALL
CALL
CALL
CALL
BR
BR
BR
BR
BR
BR
BR
CALLF
CALLF
BRKCS
BRK
RET
RETCS
RETI
RETCSB
RETB
BF
BT
BTCLR
BFSET
DBNZ
Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE,
BGT, BNH, and BH are the same as that of BC.
(6) Other instructions
ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
Data Sheet U14121EJ2V0DS00
67
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
13. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Supply voltage
Symbol
Conditions
Ratings
Unit
VDD
−0.3 to +6.5
V
AVDD
−0.3 to VDD + 0.3
V
AVSS
−0.3 to VSS + 0.3
V
AVREF0
A/D converter reference voltage input
−0.3 to VDD + 0.3
V
AVREF1
D/A converter reference voltage input
−0.3 to VDD + 0.3
V
VI1
Other than P90 to P95
−0.3 to VDD + 0.3
V
VI2
P90 to P95
−0.3 to +12
V
Analog input voltage
VAN
Analog input pin
AVSS − 0.3 to AVREF0 + 0.3
V
Output voltage
VO
−0.3 to VDD + 0.3
V
Output current, low
IOL
Per pin
15
mA
Total of P2, P4 to P8
75
mA
Total of P0, P3, P9, P10, P12, P13
75
mA
Total of all pins
100
mA
Per pin
−10
mA
Total of all pins
−50
mA
Input voltage
Output current, high
IOH
N-ch open drain
Operating ambient
temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−65 to +150
°C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
68
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Operating Conditions
• Operating ambient temperature (TA): −40 to +85°C
• Power supply voltage and clock cycle time: See Figure 13-1
• Power supply voltage with subsystem clock operation: VDD = 1.8 to 5.5 V
Figure 13-1. Power Supply Voltage and Clock Cycle Time (CPU Clock Frequency: fCPU)
10,000
8,000
Clock cycle time tCYK [ns]
500
400
Guaranteed
operating range
320
300
200
160
100
80
0
0
1
1.8 2
2.7 3
4
4.5
5
5.5
6
Supply voltage [V]
Capacitance (TA = 25°°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CI
CO
CIO
Conditions
f = 1 MHz
Unmeasured pins
returned to 0 V.
MAX.
Unit
Other than Port 9
15
pF
Port 9
20
pF
Other than Port 9
15
pF
Port 9
20
pF
Other than Port 9
15
pF
Port 9
20
pF
Data Sheet U14121EJ2V0DS00
MIN.
TYP.
69
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Main System Clock Oscillator Characteristics (TA = −40 to +85°°C)
Resonator
Ceramic
resonator
or crystal
resonator
Recommended Circuit
X2
X1 VSS
External
clock
Parameter
Oscillation frequency
(fX)
X1 input frequency (fX)
X2
µ PD74HCU04
X1
Conditions
TYP.
MAX.
Unit
MHz
4.5 V ≤ VDD ≤ 5.5 V
2
12.5
2.7 V ≤ VDD < 4.5 V
2
6.25
2.0 V ≤ VDD < 2.7 V
2
3.125
1.8 V ≤ VDD < 2.0 V
2
2
4.5 V ≤ VDD ≤ 5.5 V
2
12.5
2.7 V ≤ VDD < 4.5 V
2
6.25
2.0 V ≤ VDD < 2.7 V
2
3.125
1.8 V ≤ VDD < 2.0 V
2
2
15
250
ns
4.5 V ≤ VDD ≤ 5.5 V
0
5
ns
2.7 V ≤ VDD < 4.5 V
0
10
2.0 V ≤ VDD < 2.7 V
0
20
1.8 V ≤ VDD < 2.0 V
0
30
X1 input high-/lowlevel width (tWXH, tWXL)
X1 input rising/falling
time (tXR, tXF)
MIN.
MHz
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched back to the main system clock after the oscillation
stabilization time is secured by the program.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
70
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Subsystem Clock Oscillator Characteristics (TA = −40 to +85°°C)
Resonator
Crystal
resonator
Recommended Circuit
VSS XT2
XT1
Parameter
Oscillation frequency
(fXT)
Oscillation
stabilization timeNote
External
clock
XT2
XT1
µ PD74HCU04
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
4.5 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.5 V
10
XT1 input frequency
(fXT)
32
35
kHz
XT1 input high-/lowlevel width (tXTH, tXTL)
14.3
15.6
µs
Note Time required to stabilize oscillation after applying supply voltage (VDD).
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14121EJ2V0DS00
71
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
DC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (1/3)
Parameter
Input voltage, low
Symbol
VIL1
VIL2
V
2.2 V ≤ VDD ≤ 5.5 V
0
0.3VDD
1.8 V ≤ VDD < 2.2 V
0
0.2VDD
P00 to P06, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V
P34, P70, P72,
1.8 V ≤ VDD < 2.2 V
P100 to P103, RESET
0
0.2VDD
0
0.15VDD
Note 1
0.3VDD
1.8 V ≤ VDD < 2.2 V
0
0.2VDD
VIL4
P10 to P17, P130, P131
2.2 V ≤ VDD ≤ 5.5 V
0
0.3VDD
1.8 V ≤ VDD < 2.2 V
0
0.2VDD
VIH1
X1, X2, XT1, XT2
2.2 V ≤ VDD ≤ 5.5 V
0
0.2VDD
1.8 V ≤ VDD < 2.2 V
0
0.1VDD
2.2 V ≤ VDD ≤ 5.5 V
0
0.3VDD
1.8 V ≤ VDD < 2.2 V
0
0.2VDD
2.2 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
1.8 V ≤ VDD < 2.2 V
0.8VDD
VDD
P00 to P06, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V
P34, P70, P72,
1.8 V ≤ VDD < 2.2 V
P100 to P103, RESET
0.8VDD
VDD
0.85VDD
VDD
0.7VDD
12
P25, P27
Note 1
VIH3
P90 to P95
(N-ch open drain)
2.2 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.2 V
0.8VDD
VDD
VIH4
P10 to P17, P130, P131
2.2 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
1.8 V ≤ VDD < 2.2 V
0.8VDD
VDD
2.2 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
1.8 V ≤ VDD < 2.2 V
0.85VDD
VDD
2.2 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
1.8 V ≤ VDD < 2.2 V
0.8VDD
VDD
VIH6
VOL1
X1, X2, XT1, XT2
P25, P27
V
V
V
V
V
V
V
V
V
0.4
V
P40 to P47, P50 to P57
Note 2
IOL = 8 mA
4.5 V ≤ VDD ≤ 5.5 V
1.0
V
VOL2
IOL = 400 µA
VOH1
IOH = −1 mA
VIN = 0 V
ILIL2
VIN = VDD
4.5 V ≤ VDD ≤ 5.5 V
0.8
Note 2
Note 2
IOL = −100 µA
ILIH1
V
4.5 V ≤ VDD ≤ 5.5 V
Note 2
ILIL1
V
For pins other than
P40 to P47, P50 to P57,
Note 1
P90 to P95 IOL = 1.6 mA
P90 to P95 IOL = 15 mA
Input leakage current, high
Unit
0
VIH5
Input leakage current, low
MAX.
2.2 V ≤ VDD ≤ 5.5 V
VIH2
Output voltage, high
TYP.
P90 to P95
(N-ch open drain)
VIL6
Output voltage, low
MIN.
VIL3
VIL5
Input voltage, high
Conditions
2.0
V
0.5
V
4.5 V ≤ VDD ≤ 5.5 V VDD − 1.0
V
VDD − 0.5
V
Note 2
Except X1, X2, XT1,
XT2
−3
µA
X1, X2, XT1, XT2
−20
µA
3
µA
Except X1, X2, XT1,
XT2
20
µA
ILIH3
VIN = 12 V (N-ch open drain) P90 to P95
20
µA
Output leakage current, low
ILOL1
VOUT = 0 V
−3
µA
Output leakage current, high
ILOH1
VOUT = VDD
3
µA
ILIH2
X1, X2, XT1, XT2
Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,
P120 to P127
2. Per pin
72
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
DC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (2/3)
(1) µPD784214A, 784215A, 784216A, 784214AY, 784215AY, 784216AY
Parameter
Supply current
Symbol
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Conditions
Operation
mode
HALT mode
IDLE mode
Operation
modeNote
HALT
modeNote
IDLE
modeNote
TYP.
MAX.
Unit
fXX = 12.5 MHz, VDD = 5.0 V ±10%
MIN.
11
40
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
3
17
mA
fXX = 2 MHz, VDD = 2.0 V ±10%
1
8
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
5
20
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
2
8
mA
fXX = 2 MHz, VDD = 2.0 V ±10%
0.3
3.5
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
1
2.5
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
0.4
1.3
mA
fXX = 2 MHz, VDD = 2.0 V ±10%
0.2
0.9
mA
fXX = 32 kHz, VDD = 5.0 V ±10%
80
200
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
60
110
µA
fXX = 32 kHz, VDD = 2.0 V ±10%
30
100
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
60
160
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
20
80
µA
fXX = 32 kHz, VDD = 2.0 V ±10%
10
70
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
50
150
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
15
70
µA
fXX = 32 kHz, VDD = 2.0 V ±10%
5
60
µA
Data retention voltage
VDDDR
HALT, IDLE modes
Data retention current
IDDDR
STOP mode
1.8
VDD = 2.0 V ±10%
2
VDD = 5.0 V ±10%
Pull-up resistor
RL
VIN = 0 V
10
5.5
V
10
µA
10
50
µA
30
100
kΩ
Note When main system clock is stopped and subsystem clock is operating.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U14121EJ2V0DS00
73
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
DC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (3/3)
(2) µPD784217A, 784218A, 784217AY, 784218AY
Parameter
Supply current
Symbol
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Conditions
Operation
mode
HALT mode
IDLE mode
Operation
modeNote
HALT
modeNote
IDLE
modeNote
TYP.
MAX.
Unit
fXX = 12.5 MHz, VDD = 5.0 V ±10%
MIN.
11
40
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
4
17
mA
fXX = 2 MHz, VDD = 2.0 V ±10%
1
8
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
6
20
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
2
8
mA
fXX = 2 MHz, VDD = 2.0 V ±10%
0.4
3.5
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
1
2.5
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
0.4
1.3
mA
fXX = 2 MHz, VDD = 2.0 V ±10%
0.2
0.9
mA
fXX = 32 kHz, VDD = 5.0 V ±10%
80
200
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
60
110
µA
fXX = 32 kHz, VDD = 2.0 V ±10%
30
100
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
60
160
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
20
80
µA
fXX = 32 kHz, VDD = 2.0 V ±10%
10
70
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
50
150
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
15
70
µA
fXX = 32 kHz, VDD = 2.0 V ±10%
5
60
µA
Data retention voltage
VDDDR
HALT, IDLE modes
Data retention current
IDDDR
STOP mode
1.8
VDD = 2.0 V ±10%
2
VDD = 5.0 V ±10%
Pull-up resistor
RL
VIN = 0 V
10
5.5
V
10
µA
10
50
µA
30
100
kΩ
Note When main system clock is stopped and subsystem clock is operating.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
74
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
AC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Cycle time
Symbol
tCYK
Address setup time (to ASTB↓)
tSAST
Address hold time (from ASTB↓) tHSTLA
ASTB high-level width
Address hold time (from RD↑)
tWSTH
tHRA
Delay time from address to RD↓ tDAR
Address float time (from RD↓)
Data input time from address
Data input time from ASTB↓
Data input time from RD↓
tFAR
tDAID
tDSTID
tDRID
Conditions
Data hold time (from RD↑)
tDSTR
tHRID
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
80
ns
2.7 V ≤ VDD < 4.5 V
160
ns
2.0 V ≤ VDD < 2.7 V
320
ns
1.8 V ≤ VDD < 2.0 V
500
ns
VDD = 5.0 V ±10%
(0.5 + a)T − 20
ns
VDD = 3.0 V ±10%
(0.5 + a)T − 40
ns
VDD = 2.0 V ±10%
(0.5 + a)T − 80
ns
VDD = 5.0 V ±10%
0.5T − 19
ns
VDD = 3.0 V ±10%
0.5T − 24
ns
VDD = 2.0 V ±10%
0.5T − 34
ns
VDD = 5.0 V ±10%
(0.5 + a)T − 17
ns
VDD = 3.0 V ±10%
(0.5 + a)T − 40
ns
VDD = 2.0 V ±10%
(0.5 + a)T − 110
ns
VDD = 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±10%
0.5T − 14
ns
VDD = 5.0 V ±10%
(1 + a)T − 24
ns
VDD = 3.0 V ±10%
(1 + a)T − 35
ns
VDD = 2.0 V ±10%
(1 + a)T − 80
ns
VDD = 5.0 V ±10%
0
ns
VDD = 3.0 V ±10%
0
ns
VDD = 2.0 V ±10%
0
ns
VDD = 5.0 V ±10%
(2.5 + a + n)T − 37
ns
VDD = 3.0 V ±10%
(2.5 + a + n)T − 52
ns
VDD = 2.0 V ±10%
(2.5 + a + n)T − 120
ns
VDD = 5.0 V ±10%
(2 + n)T − 35
ns
VDD = 3.0 V ±10%
(2 + n)T − 50
ns
VDD = 2.0 V ±10%
(2 + n)T − 80
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 40
ns
= 3.0 V ±10%
(1.5 + n)T − 50
ns
VDD = 2.0 V ±10%
(1.5 + n)T − 90
ns
VDD
Delay time from ASTB↓ to RD↓
MIN.
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±10%
0.5T − 20
ns
VDD = 5.0 V ±10%
0
ns
VDD = 3.0 V ±10%
0
ns
VDD = 2.0 V ±10%
0
ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of waits (n ≥ 0)
Data Sheet U14121EJ2V0DS00
75
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
AC Characteristics
(1) Read/write operation (2/2)
Parameter
Address active time from RD↑
Delay time from RD↑ to ASTB↑
RD low-level width
Symbol
tDRA
tDRST
tWRL
Delay time from address to WR↓ tDAW
Address hold time (from WR↑)
tHRD
Conditions
MIN.
TYP.
MAX.
Unit
VDD = 5.0 V ±10%
0.5T − 2
ns
VDD = 3.0 V ±10%
0.5T − 12
ns
VDD = 2.0 V ±10%
0.5T − 35
ns
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±10%
0.5T − 40
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 30
ns
VDD = 2.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 5.0 V ±10%
(1 + a)T − 24
ns
VDD = 3.0 V ±10%
(1 + a)T − 34
ns
VDD = 2.0 V ±10%
(1 + a)T − 70
ns
VDD = 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±10%
0.5T − 14
ns
Delay time from ASTB↓ to data tDSTOD
VDD = 5.0 V ±10%
0.5T + 15
ns
output
VDD = 3.0 V ±10%
0.5T + 30
ns
VDD = 2.0 V ±10%
0.5T + 240
ns
Delay time from WR↓ to data tDWOD
VDD = 5.0 V ±10%
0.5T − 30
ns
output
VDD = 3.0 V ±10%
0.5T − 30
ns
VDD = 2.0 V ±10%
0.5T − 30
ns
Delay time from ASTB↓ to WR↓ tDSTW
Data setup time (to WR↑)
Data hold time (from WR↑)
tSODWR
tHWOD
Delay time from WR↑ to ASTB↑ tDWST
WR low-level width
tWWL
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±10%
0.5T − 20
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 20
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 2.0 V ±10%
(1.5 + n)T − 70
ns
VDD = 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±10%
0.5T − 50
ns
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±10%
0.5T − 30
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 30
ns
VDD = 2.0 V ±10%
(1.5 + n)T − 30
ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
76
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
AC Characteristics
(2) External wait timing
Parameter
Input time from address to
Symbol
tDAWT
WAIT↓
Input time from ASTB↓ to
tDSTWT
WAIT↓
Conditions
MIN.
VDD = 5.0 V ±10%
Hold time from ASTB↓ to WAIT
Delay time from ASTB↓ to
tDSTWTH
WAIT↑
Input time from RD↓ to WAIT↓
Hold time from RD↓ to WAIT↓
Delay time from RD↓ to WAIT↑
Data input time from WAIT↑
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
Input time from WR↓ to WAIT↓
tDRWTL
tHRWT
tDRWTH
tDWTID
tDWTR
tDWTW
tDWWTL
Hold time from WR↓ to WAIT
Delay time from WR↓ to WAIT↑
tDWWTH
Unit
ns
(2 + a)T − 60
ns
VDD = 2.0 V ±10%
(2 + a)T − 300
ns
VDD = 5.0 V ±10%
1.5T − 40
ns
VDD = 3.0 V ±10%
1.5T − 60
ns
1.5T − 260
ns
VDD = 5.0 V ±10%
(0.5 + n)T + 5
ns
VDD = 3.0 V ±10%
(0.5 + n)T + 10
ns
VDD = 2.0 V ±10%
(0.5 + n)T + 30
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 40
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 60
ns
VDD = 2.0 V ±10%
(1.5 + n)T − 90
ns
VDD = 5.0 V ±10%
T − 40
ns
VDD = 3.0 V ±10%
T − 60
ns
VDD = 2.0 V ±10%
T − 70
ns
VDD = 5.0 V ±10%
nT + 5
ns
VDD = 3.0 V ±10%
nT + 10
ns
VDD = 2.0 V ±10%
nT + 30
ns
VDD = 5.0 V ±10%
(1 + n)T − 40
ns
VDD = 3.0 V ±10%
(1 + n)T − 60
ns
VDD = 2.0 V ±10%
(1 + n)T − 90
ns
VDD = 5.0 V ±10%
0.5T − 5
ns
VDD = 3.0 V ±10%
0.5T − 10
ns
VDD = 2.0 V ±10%
0.5T − 30
ns
VDD = 5.0 V ±10%
0.5T
ns
VDD = 3.0 V ±10%
0.5T
ns
VDD = 2.0 V ±10%
0.5T + 5
ns
VDD = 5.0 V ±10%
0.5T
ns
VDD = 3.0 V ±10%
0.5T
ns
VDD = 2.0 V ±10%
0.5T + 5
ns
VDD = 5.0 V ±10%
T − 40
ns
VDD = 3.0 V ±10%
T − 60
ns
VDD = 2.0 V ±10%
tHWWT
MAX.
(2 + a)T − 40
VDD = 3.0 V ±10%
VDD = 2.0 V ±10%
tHSTWT
TYP.
T − 90
ns
VDD = 5.0 V ±10%
nT + 5
ns
VDD = 3.0 V ±10%
nT + 10
ns
VDD = 2.0 V ±10%
nT + 30
ns
VDD = 5.0 V ±10%
(1 + n)T − 40
ns
VDD = 3.0 V ±10%
(1 + n)T − 60
ns
VDD = 2.0 V ±10%
(1 + n)T − 90
ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
Data Sheet U14121EJ2V0DS00
77
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Serial Operation (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
(a) 3-wire serial I/O mode (SCK: Internal clock output)
Parameter
Symbol
Conditions
SCK cycle time
tKCY1
2.7 V ≤ VDD ≤ 5.5 V
SCK high-/low-level width
tKH1,
tKL1
2.7 V ≤ VDD ≤ 5.5 V
tSIK1
2.7 V ≤ VDD ≤ 5.5 V
SI setup time (to SCK↑)
SI hold time (from SCK↑)
tKSI1
SO output delay time
(from SCK↓)
tKSO1
MIN.
TYP.
MAX.
Unit
800
ns
3,200
ns
350
ns
1,500
ns
10
ns
30
ns
40
ns
30
ns
MAX.
Unit
(b) 3-wire serial I/O mode (SCK: External clock input)
Parameter
Symbol
Conditions
SCK cycle time
tKCY2
2.7 V ≤ VDD ≤ 5.5 V
SCK high-/low-level width
tKH2
tKL2
2.7 V ≤ VDD ≤ 5.5 V
tSIK2
2.7 V ≤ VDD ≤ 5.5 V
SI setup time (to SCK↑)
SI hold time (from SCK↑)
tKSI2
SO output delay time
(from SCK↓)
tKSO2
MIN.
TYP.
800
ns
3,200
ns
400
ns
1,600
ns
10
ns
30
ns
40
ns
30
ns
MAX.
Unit
(c) UART mode
Parameter
ASCK cycle time
Symbol
tKCY3
Conditions
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
ASCK high-/low-level width
78
tKH3
tKL3
MIN.
TYP.
417
ns
833
ns
1,667
ns
4.5 V ≤ VDD ≤ 5.5 V
208
ns
2.7 V ≤ VDD < 4.5 V
416
ns
833
ns
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(d) I2C bus mode
Parameter
Symbol
Standard Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
fCLK
0
100
0
400
kHz
Bus free time (between stop
and start conditions)
tBUF
4.7
−
1.3
−
µs
tHD : STA
4.0
−
0.6
−
µs
Low-level width of SCL0 clock
tLOW
4.7
−
1.3
−
µs
High-level width of SCL0 clock
tHIGH
4.0
−
0.6
−
µs
Setup time of start/restart
conditions
tSU : STA
4.7
−
0.6
−
µs
Data hold When using CBUStime
compatible master
tHD : DAT
5.0
−
−
−
µs
0Note 2
−
0Note 2
0.9Note 3
µs
Hold timeNote1
2
When using I C bus
Data setup time
tSU : DAT
250
−
Note 4
−
ns
Note 5
20 + 0.1Cb
300
ns
100
Rise time of SDA0 and SCL0
signals
tR
−
1,000
Fall time of SDA0 and SCL0
signals
tF
−
300
20 + 0.1CbNote 5
300
ns
Setup time of stop condition
tSU : STO
4.0
−
0.6
−
µs
Pulse width of spike restricted
by input filter
tSP
−
−
0
50
ns
Load capacitance of each bus
line
Cb
−
400
−
400
pF
Notes 1. For the start condition, the first clock pulse is generated after the hold time.
2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal
SDA0 signal (on VIHmin.) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low-level hold time (tLOW), only the maximum data hold
time
tHD : DAT needs to be satisfied.
4. The high-speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low-level hold time
tSU : DAT ≥ 250 ns
• If the device extends the SCL0 signal low-level hold time
Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU :
DAT
= 1,000 + 250 = 1,250 ns by standard mode I2C bus specification)
5. Cb: Total capacitance per bus line (unit: pF)
Data Sheet U14121EJ2V0DS00
79
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Other Operations (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
NMI high-/low-level width
tWNIL
tWNIH
INTP input high-/low-level width
tWITL
tWITH
RESET high-/low-level width
tWRSL
tWRSH
Conditions
INTP0 to INTP6
MIN.
TYP.
MAX.
Unit
10
µs
100
ns
10
µs
Clock Output Operation (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
PCL cycle time
tCYCL
4.5 V ≤ VDD ≤ 5.5 V, nT
80
31,250
ns
PCL high-/low-level width
tCLL
tCLH
4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10
30
15,615
ns
PCL rise/fall time
tCLR
tCLF
4.5 V ≤ VDD ≤ 5.5 V
5
ns
2.7 V ≤ VDD < 4.5 V
10
ns
1.8 V ≤ VDD < 2.7 V
20
ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)
n: Divided frequency ratio set by software in the CPU
• When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128
• When using the subsystem clock: n = 1
80
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
A/D Converter Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bits
2.7 V ≤ VDD ≤ 5.5 V
2.2 V ≤ AVREF0 ≤ VDD
±1.2
%FSR
1.8 V ≤ VDD < 2.7 V
1.8 V ≤ AVREF0 ≤ VDD
±1.6
%FSR
144
µs
Resolution
Notes 1, 2
Overall error
Conversion time
tCONV
14
Sampling time
tSAMP
24/fXX
Analog input voltage
VIAN
AVSS
AVREF0
V
Reference voltage
AVREF0
1.8
AVDD
V
Resistance between AVREF0 and AVSS
RAVREF0
When not A/D converting
µs
40
kΩ
Notes 1. Quantization error (±1/2 LSB) is not included.
2. Overall error is indicated as a ratio to the full-scale value.
Remark fXX : Main system clock frequency
D/A Converter Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
Bits
R = 10 MΩ, 2.0 V ≤ AVREF1 ≤ VDD,
2.0 V ≤ VDD ≤ 5.5 V
±0.6
%FSR
R = 10 MΩ, 1.8 V ≤ AVREF1 ≤ VDD,
1.8 V ≤ VDD ≤ 2.0 V
±1.2
%FSR
4.5 V ≤ AVREF1 ≤ 5.5 V
10
µs
2.7 V ≤ AVREF1 < 4.5 V
15
µs
1.8 V ≤ AVREF1 < 2.7 V
20
µs
Resolution
Notes 1, 2
Overall error
Settling time
Load conditions:
C = 30 pF
Output resistance
RO
Reference voltage
AVREF1
AVREF1 current
AIREF1
DACS0, 1 = 55H
8
1.8
For only 1 channel
kΩ
VDD
V
2.5
mA
Notes 1. Quantization error (±1/2 LSB) is not included.
2. Overall error is indicated as a ratio to the full-scale value.
Data Sheet U14121EJ2V0DS00
81
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Data Retention Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
1.8
MAX.
Unit
5.5
V
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
VDDDR = 5.0 V ±10%
10
50
µA
VDDDR = 2.0 V ±10%
2
10
µA
VDD rise time
tRVD
200
µs
VDD fall time
tFVD
200
µs
VDD hold time
(from STOP mode setting)
tHVD
0
ms
STOP release signal input time
tDREL
0
ms
Oscillation stabilization wait time
tWAIT
Crystal resonator
30
ms
Ceramic resonator
5
ms
RESET, P00/INTP0 to P06/INTP6
0
0.1VDDDR
V
0.9VDDDR
VDDDR
V
Low-level input voltage
VIL
High-level input voltage
VIH
AC Timing Test Points
VDD − 1 V
0.8VDD or 1.8 V
0.8VDD or 1.8 V
Test points
0.45 V
82
0.8 V
0.8 V
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Timing Waveforms
(1) Read operations
(CLK)
tCYK
A0 to A7
(Output)
Lower address
Lower address
A8 to A19
(Output)
Higher address
Higher address
tDAID
tHRA
tDRA
tDSTID
AD0 to AD7
(Input/output)
Hi-Z
Hi-Z
Lower address
(Output)
tSAST
Data (Input)
Hi-Z
Lower address
(Output)
tHRID
tHSTLA
tFAR
ASTB
(Output)
tWSTH
tDSTR
tDAR
tDRST
tDRID
RD
(Output)
tWRL
tDRWTL
tDAWT
tDRWTH
tHRWT
tDWTR
tDWTID
WAIT
(Input)
tDSTWT
tDSTWTH
tHSTWT
Remark The signal is output from pins A0 to A7 when P80 to P87 are unused.
Data Sheet U14121EJ2V0DS00
83
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(2) Write operation
(CLK)
tCYK
A0 to A7
(Output)
Lower address
Lower address
A8 to A19
(Output)
Higher address
Higher address
tDAID
tHWA
tDAW
tDSTOD
AD0 to AD7
(Output)
Hi-Z
Lower address
(Output)
tSAST
Hi-Z
tHWOD
tHSTLA
tSODWR
tFAR
ASTB
(Output)
Hi-Z
Data (Output)
tWSTH
tDSTW
tDWST
tDAW
tDWOD
WR
(Output)
tWWL
tDWWTL
tDAWT
tDWWTH
tHWWT
tDWTW
tDWTID
WAIT
(Input)
tDSTWT
tDSTWTH
tHSTWT
Remark The signal is output from pins A0 to A7 when P80 to P87 are unused.
84
Data Sheet U14121EJ2V0DS00
Lower address
(Output)
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Serial Operation
(1) 3-wire serial I/O mode
tKCY1, 2
tKH1, 2
tKL1, 2
SCK
tKSO1, 2
tKSI1, 2
tSIK1, 2
SI/SO
(2) UART mode
tKCY3
tKH3
tKL3
ASCK
(3) I2C bus mode (µPD784216AY/784218AY Subseries only)
tR
SCL0
tHD : DAT
tHD : STA
tHIGH
tSU : DAT
tF
tSU : STA
tHD : STA
tSP
tSU : STO
SDA0
tBUF
Stop
condition
Restart
condition
Start
condition
Data Sheet U14121EJ2V0DS00
Stop
condition
85
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Clock Output Timing
tCLH
tCLL
CLKOUT
tCLR
tCLF
tCYCL
Interrupt Input Timing
tWNIH
tWNIL
tWITH
tWITL
tWRSH
tWRSL
NMI
INTP0 to INTP6
Reset Input Timing
RESET
86
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Clock Timing
tWXH
tWXL
X1
tXR
tXF
1/fX
tXTH
tXTL
XT1
1/fXT
Data Retention Characteristics
STOP mode setting
VDD
VDDDR
tHVD
tFVD
tRVD
tDREL
tWAIT
RESET
NMI
(Cleared by falling edge)
NMI
(Cleared by rising edge)
Data Sheet U14121EJ2V0DS00
87
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
14. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
Q
R
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
+7°
3° −3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
Remark The external dimensions and material of the ES version are the same as those of the mass-produced
version.
88
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
100-PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
Q
R
31
30
100
1
F
G
J
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
23.6±0.4
B
20.0±0.2
C
14.0±0.2
D
17.6±0.4
F
0.8
G
H
0.6
0.30±0.10
I
0.15
J
K
L
0.65 (T.P.)
1.8±0.2
0.8±0.2
M
0.15+0.10
−0.05
N
0.10
P
2.7±0.1
Q
R
0.1±0.1
5°±5°
S
3.0 MAX.
P100GF-65-3BA1-4
Remark The external dimensions and material of the ES version are the same as those of the mass-produced
version.
Data Sheet U14121EJ2V0DS00
89
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
15. RECOMMENDED SOLDERING CONDITIONS
The µPD784218A should be soldered and mounted under the following recommended conditions. For the details
of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology
Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 15-1. Surface Mounting Type Soldering Conditions (1/2)
×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm)
(1) µPD784214AGC-×××
×××
×××-8EU:100-pin
plastic LQFP(fine pitch) (14 × 14 mm)
×××
µPD784215AGC-×××
×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm)
×××
µPD784216AGC-×××
×××-8EU:
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
×××
µPD784217AGC-×××
×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
×××
µPD784218AGC-×××
×××-8EU:100-pin
plastic LQFP(fine pitch) (14 × 14 mm)
×××
µPD784214AYGC-×××
×××-8EU:100-pin
plastic LQFP(fine pitch) (14 × 14 mm)
×××
µPD784215AYGC-×××
×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm)
×××
µPD784216AYGC-×××
×××-8EU:
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
×××
µPD784217AYGC-×××
×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
×××
µPD784218AYGC-×××
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Note
Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125°C
Recommended
Condition Symbol
IR35-107-2
for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Note
Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125°C
VP15-107-2
for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
−
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
90
Do not use different soldering methods together (except for partial heating).
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 15-1. Surface Mounting Type Soldering Conditions (2/2)
×××-3BA:100-pin
(2) µPD784214AGF-×××
plastic QFP(14 × 20 mm)
×××
×××-3BA:100-pin
plastic QFP(14 × 20 mm)
×××
µPD784215AGF-×××
×××-3BA:100-pin plastic QFP(14 × 20 mm)
×××
µPD784216AGF-×××
×××-3BA:
100-pin plastic QFP (14 × 20 mm)
×××
µPD784217AGF-×××
×××-3BA: 100-pin plastic QFP (14 × 20 mm)
×××
µPD784218AGF-×××
×××-3BA:100-pin
plastic QFP(14 × 20 mm)
×××
µPD784214AYGF-×××
×××-3BA:100-pin plastic QFP(14 × 20 mm)
×××
µPD784215AYGF-×××
×××-3BA:100-pin
plastic QFP(14 × 20 mm)
×××
µPD784216AYGF-×××
×××-3BA: 100-pin plastic QFP (14 × 20 mm)
×××
µPD784217AYGF-×××
×××-3BA:
100-pin plastic QFP (14 × 20 mm)
×××
µPD784218AYGF-×××
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
IR35-00-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
VP15-00-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution
−
Do not use different soldering methods together (except for partial heating).
Data Sheet U14121EJ2V0DS00
91
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD784218A. Also refer to (5)
Cautions on using development tools.
(1) Language processing software
RA78K4
Assembler package common to 78K/IV Series
CC78K4
C compiler package common to 78K/IV Series
DF784218
Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries
CC78K4-L
C compiler library source file common to 78K/IV Series
(2) Flash memory writing tools
Dedicated flash programmer for microcontroller incorporating flash memory
Flashpro II
(Model number: FL-PR2),
Flashpro III
(Model number: FL-PR3, PG-FP3)
FA-100GF
Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be
performed in accordance with the target product.
FA-100GC
Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be
performed in accordance with the target product.
Flashpro II controller,
Flashpro III controller
Control program that runs on a personal computer and is attached to Flashpro II, Flashpro III.
TM
Operates on Windows 95, etc.
(3) Debugging tools
• When IE-78K4-NS in-circuit emulator is used
IE-78K4-NS
In-circuit emulator common to 78K/IV Series
IE-70000-MC-PS-B
Power supply unit for IE-78K4-NS
IE-70000-98-IF-C
Interface adapter required when PC-9800 series PC (except notebook type) is used as host
machine (C bus supported)
IE-70000-CD-IF-A
PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter required when using IBM PC/AT
supported)
IE-70000-PCI-IF
Interface adapter required when using PC that incorporates PCI bus as host machine
TM
compatibles as host machine (ISA bus
IE-784225-NS-EM1
Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries
NP-100GF
Emulation probe for 100-pin plastic QFP (GF-3BA type)
NP-100GC
Emulation probe for 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW
Conversion adapter to connect the NP-100GC and a target system board on which a 100-pin
plastic LQFP (GC-8EU type) can be mounted
ID78K4-NS
Integrated debugger for IE-78K4-NS
SM78K4
System simulator common to 78K/IV Series
DF784218
Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries
92
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
• When IE-784000-R in-circuit emulator is used
IE-784000-R
In-circuit emulator common to 78K/IV Series
IE-70000-98-IF-C
Interface adapter required when PC-9800 series PC (except notebook type) is used as host
machine (C bus supported)
IE-70000-PC-IF-C
Interface adapter required when using IBM PC/AT and compatibles as host machine (ISA bus
supported)
IE-70000-PCI-IF
Interface adapter required when using PC that incorporates PCI bus as host machine
IE-78000-R-SV3
Interface adapter and cable required when EWS is used as host machine
IE-784225-NS-EM1
Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries
IE-784000-R-EM
Emulation board common to 78K/IV Series
IE-78K4-R-EX3
Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R.
EP-784218GF-R
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EP-78064GC-R
Emulation probe for 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW
Conversion adapter to connect the EP-78064GC-R and a target system board on which a
100-pin plastic LQFP (GC-8EU type) can be mounted
ID78K4
Integrated debugger for IE-784000-R
SM78K4
System simulator common to 78K/IV Series
DF784218
Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries
(4) Real-time OS
RX78K/IV
Real-time OS for 78K/IV Series
MX78K4
OS for 78K/IV Series
Data Sheet U14121EJ2V0DS00
93
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(5) Cautions on using development tools
• The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218.
• The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.
• The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito
Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).
• The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.
For further information, contact Daimaru Kogyo, Ltd.
Tokyo Electronic Division (TEL: +81-3-3820-7112)
Osaka Electronic Division (TEL: +81-6-6244-6672)
• For third party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machine and OS suitable for each software are as follows:
Host Machine
PC
EWS
Software
PC-9800 series [Windows]
IBM PC/AT and compatibles
[Japanese/English Windows]
HP9000 Series 700 [HP-UX ]
TM
TM
TM
SPARCstation [SunOS , Solaris ]
TM
TM
NEWS (RISC) [NEWS-OS ]
RA78K4
√Note
√
Note
√
[OS]
CC78K4
√
TM
ID78K4-NS
√
−
ID78K4
√
√
√
−
SM78K4
RX78K/IV
Note
√
√
MX78K4
√Note
√
Note DOS-based software
94
Data Sheet U14121EJ2V0DS00
TM
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
APPENDIX B. RELATED DOCUMENTS
Documents related to devices
Document Name
Document No.
English
Japanese
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY,
784217AY, 784218AY Data Sheet
This document
U14121J
µPD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet
To be prepared
To be prepared
µPD784216A, 784216AY Subseries User’s Manual Hardware
U13570E
U13570J
µPD784218A, 784218AY Subseries User’s Manual Hardware
U12970E
U12970J
78K/IV Series User’s Manual Instructions
U10905E
U10905J
78K/IV Series Instruction Table
−
U10594J
78K/IV Series Instruction Set
−
U10595J
78K/IV Series Application Note Software Basics
−
U10095J
Documents related to development tools (user’s manuals)
Document Name
Document No.
English
RA78K4 Assembler Package
Japanese
Language
U11162E
U11162J
Operation
U11334E
U11334J
U11743E
U11743J
Language
U11571E
U11571J
Operation
U11572E
U11572J
IE-78K4-NS
U13356E
U13356J
IE-784000-R
U12903E
U12903J
IE-784218-R-EM1
U12155E
U12155J
IE-784225-NS-EM1
U13742E
U13742J
EP-78064
EEU-1469
EEU-934
RA78K Structured Assembler Preprocessor
CC78K4 C Compiler
SM78K4 System Simulator Windows Based
Reference
U10093E
U10093J
SM78K Series System Simulator
External Part User Open
Interface Specifications
U10092E
U10092J
ID78K4-NS Integrated Debugger PC Based
Reference
U12796E
U12796J
ID78K4 Integrated Debugger Windows Based
Reference
U10440E
U10440J
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS based
Reference
U11960E
U11960J
Caution
The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Data Sheet U14121EJ2V0DS00
95
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Documents related to embedded software (user’s manuals)
Document Name
Document No.
English
78K/IV Series Real-Time OS
78K/IV Series OS MX78K4
Japanese
Fundamental
U10603E
U10603J
Installation
U10604E
U10604J
Debugger
−
U10364J
Fundamental
−
U11779J
Other documents
Document Name
Document No.
English
Japanese
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
C11892J
Guide to Microcomputer-Related Products by Third Party
Caution
U11416J
The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
96
−
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet U14121EJ2V0DS00
97
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
98
Data Sheet U14121EJ2V0DS00
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
IEBus is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
Data Sheet U14121EJ2V0DS00
99
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
2
2
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components
2
2
in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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