DATA SHEET MOS INTEGRATED CIRCUIT µPD753104, 753106, 753108 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD753108 is one of the 75XL Series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. The existing 75X Series containing an LCD controller/driver supplies an 80-pin package. The µPD753108 supplies a 64-pin package (12 × 12), which is suitable for small-scale systems. It features expanded CPU functions and can provide high-speed operation at a low supply voltage of 1.8 V compared with the existing µPD75308B. Detailed function descriptions are provided in the following user’s manual. Be sure to read it before designing. µ PD753108 User’s Manual: U10890E FEATURES • Low voltage operation: VDD = 1.8 to 5.5 V • Can be driven by two 1.5 V batteries • Internal memory • Program memory (ROM): 4096 × 8 bits (µPD753104) 6144 × 8 bits (µPD753106) 8192 × 8 bits (µPD753108) • Data memory (RAM): 512 × 4 bits • Capable of high-speed operation and variable instruction execution time for power saving • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock) • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock) • 122 µs (@ 32.768 kHz with subsystem clock) • Internal programmable LCD controller/driver • Small package: 64-pin plastic LQFP (12 × 12), 64-pin plastic TQFP (12 × 12) • One-time PROM version: µPD75P3116 APPLICATION Remote controllers, cameras, hemadynamometers, electronic scale, gas meters, etc. Unless otherwise indicated, references in this data sheet to the µPD753108 mean the µ PD753104 and µPD753106. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U10086EJ4V0DS00 (4th edition) Date Published September 2000 N CP(K) Printed in Japan The mark shows major revised points. 1995, 2000 µPD753104, 753106, 753108 ORDERING INFORMATION Part number µPD753104GC-×××-AB8 64-pin plastic QFP (14 × 14) µPD753104GK-×××-8A8 64-pin plastic LQFP (12 × 12) µPD753104GK-×××-9ET 64-pin plastic TQFP (12 × 12) µPD753106GC-×××-AB8 64-pin plastic QFP (14 × 14) µPD753106GK-×××-8A8 64-pin plastic LQFP (12 × 12) µPD753106GK-×××-9ET 64-pin plastic TQFP (12 × 12) µPD753108GC-×××-AB8 64-pin plastic QFP (14 × 14) µPD753108GK-×××-8A8 64-pin plastic LQFP (12 × 12) µPD753108GK-×××-9ET 64-pin plastic TQFP (12 × 12) Remark 2 Package ××× indicates ROM code suffix. Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 OVERVIEW OF FUNCTIONS Parameter Function • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock) • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock) • 122 µs (@ 32.768 kHz with subsystem clock) Instruction execution time Internal memory ROM 4096 × 8 bits ( µPD753104), 6144 × 8 bits ( µPD753106), 8192 × 8 bits ( µPD753108) RAM 512 × 4 bits General-purpose register • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks I/O port CMOS input 8 On-chip pull-up resistors which can be specified by means of software: 7 CMOS I/O 20 On-chip pull-up resistors which can be specified by means of software: 12 Also used for segment pins: 8 N-ch open-drain I/O pins 4 On-chip pull-up resistors which can be specified by mask option, 13 V withstand voltage Total 32 LCD controller/driver • Segment selection: 16/20/24 segments (can be changed to CMOS I/O port in 4 time-unit; max. 8) • Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) • On-chip split resistor for LCD drive can be specified by mask option Timer 5 channels • 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator, timer with gate) • Basic interval timer/watchdog timer: 1 channel • Watch timer: 1 channel Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit • 2-wire serial I/O mode • SBI mode Bit sequential buffer (BSB) 16 bits Clock output (PCL) • Φ, 524, 262, 65.5 kHz (@ 4.19 MHz with main system clock) • Φ, 750, 375, 93.8 kHz (@ 6.0 MHz with main system clock) Buzzer output (BUZ) • 2, 4, 32 kHz Vectored interrupt External: 3, Internal: 5 Test input External: 1, Internal: 1 System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation • Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode Supply voltage VDD = 1.8 to 5.5 V Package • 64-pin plastic QFP (14 × 14) • 64-pin plastic LQFP (12 × 12) • 64-pin plastic TQFP (12 × 12) (@ 4.19 MHz with main system clock or @ 32.768 kHz with subsystem clock) • 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock) Data Sheet U10086EJ4V0DS00 3 µPD753104, 753106, 753108 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) .................................................................................................... 6 2. BLOCK DIAGRAM ................................................................................................................................ 8 3. PIN FUNCTIONS ................................................................................................................................... 9 3.1 Port Pins ...................................................................................................................................... 9 3.2 Non-Port Pins ............................................................................................................................ 11 3.3 Pin I/O Circuits .......................................................................................................................... 13 3.4 Recommended Connections of Unused Pins ........................................................................ 15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 16 4.1 Difference Between Mk I Mode and Mk II Mode ..................................................................... 16 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 17 5. MEMORY CONFIGURATION ............................................................................................................. 18 6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 23 6.1 Digital I/O Port ........................................................................................................................... 23 6.2 Clock Generator ........................................................................................................................23 6.3 Subsystem Clock Oscillator Control Functions .................................................................... 25 6.4 Clock Output Circuit .................................................................................................................26 6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 27 6.6 Watch Timer ..............................................................................................................................28 6.7 Timer/Event Counter .................................................................................................................29 6.8 Serial Interface .......................................................................................................................... 33 6.9 LCD Controller/Driver ............................................................................................................... 35 6.10 Bit Sequential Buffer ................................................................................................................ 37 7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 38 8. STANDBY FUNCTION ........................................................................................................................40 9. RESET FUNCTION .............................................................................................................................41 10. MASK OPTION ...................................................................................................................................44 11. INSTRUCTION SET ............................................................................................................................ 45 12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 59 13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ............................................................... 75 14. PACKAGE DRAWINGS ..................................................................................................................... 78 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 81 4 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 APPENDIX A. µPD75308B, 753108 AND 75P3116 FUNCTIONAL LIST .............................................. 83 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 85 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 89 Data Sheet U10086EJ4V0DS00 5 µPD753104, 753106, 753108 1. PIN CONFIGURATION (TOP VIEW) • 64-pin plastic QFP (14 × 14) µPD753104GC-×××-AB8, 753106GC-×××-AB8, 753108GC-×××-AB8 • 64-pin plastic LQFP (12 × 12) µPD753104GK-×××-8A8, 753106GK-×××-8A8, 753108GK-×××-8A8 • 64-pin plastic TQFP (12 × 12) COM3 COM2 COM1 COM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 µPD753104GK-×××-9ET, 753106GK-×××-9ET, 753108GK-×××-9ET BIAS 1 48 S12 VLC0 2 47 S13 VLC1 3 46 S14 VLC2 4 45 S15 P30/LCDCL 5 44 S16/P93 P31/SYNC 6 43 S17/P92 P32 7 42 S18/P91 P33 8 41 S19/P90 VSS 9 40 S20/P83 P50 10 39 S21/P82 P51 11 38 S22/P81 P52 12 37 S23/P80 6 24 25 26 27 28 29 30 31 32 VDD P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/INT2/TI1/TI2 P13/TI0 23 P00/INT4 22 X2 P63/KR3 Note X1 P20/PTO0 21 P21/PTO1 33 XT2 34 16 ICNote 15 P62/KR2 20 P61/KR1 19 P22/PCL/PTO2 XT1 P23/BUZ 35 18 36 14 17 13 RESET P53 P60/KR0 Connect the IC (Internally Connected) pin directly to VDD. Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Pin Identification P00 to P03: P10 to P13: P20 to P23: P30 to P33: P50 to P53: P60 to P63: P80 to P83: P90 to P93: KR0 to KR3: SCK: SI: SO: SB0, SB1: RESET: S0 to S23: COM0 to COM3: Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 8 Port 9 Key Return 0 to 3 Serial Clock Serial Input Serial Output Serial Data Bus 0, 1 Reset Segment Output 0 to 23 Common Output 0 to 3 VLC0 to VLC2: BIAS: LCDCL: SYNC: TI0 to TI2: PTO0 to PTO2: BUZ: PCL: INT0, INT1, INT4: INT2: X1, X2: XT1, XT2: VDD: VSS: IC: Data Sheet U10086EJ4V0DS00 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 to 2 Programmable Timer Output 0 to 2 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Positive Power Supply Ground Internally Connected 7 4 P00 to P03 INTW fLCD BASIC INTERVAL TIMER/ WATCHDOG TIMER CY PROGRAM COUNTER PORT1 4 P10 to P13 SBS PORT2 4 P20 to P23 BANK PORT3 4 P30 to P33 PORT5 4 P50 to P53 PORT6 4 P60 to P63 PORT8 4 P80 to P83 PORT9 4 P90 to P93 SP(8) ALU INTBT PTO0/P20 Data Sheet U10086EJ4V0DS00 INTT0 INTT1 TI1/TI2/P12/INT2 PTO1/P21 PTO2/PCL/P22 TOUT0 GENERAL REG. 8-BIT TIMER/EVENT COUNTER #0 TI0/P13 TOUT0 PROGRAM MEMORYNote (ROM) DECODE AND CONTROL 8-BIT TIMER/EVENT CASCADED COUNTER #1 16-BIT TIMER/ 8-BIT EVENT TIMER/EVENT COUNTER COUNTER #2 DATA MEMORY (RAM) 512 × 4 BITS LCD CONTROLLER/ 16 DRIVER INTT2 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INT1 INT0/P10 INT1/P11 INT4/P00 INT2/P12/TI1/TI2 KR0/P60 to KR3/P63 4 INTERRUPT CONTROL N fx/2 CPU CLOCK Φ PCL/PTO2/P22 X1 X2 XT1XT2 fLCD IC BIT SEQ. BUFFER (16) Note 4 S16/P93 to S19/P90 4 S20/P83 to S23/P80 4 CLOCK CLOCK SYSTEM CLOCK STAND BY OUTPUT DIVIDER GENERATOR CONTROL CONTROL MAIN SUB The ROM capacity depends on the product. VDD VSS RESET S0 to S15 COM0 to COM3 BIAS VLC0 VLC1 VLC2 SYNC/P31 LCDCL/P30 µPD753104, 753106, 753108 INTCSI TOUT0 2. BLOCK DIAGRAM 8 PORT0 WATCH TIMER BUZ/P23 µPD753104, 753106, 753108 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name P00 I/O Alternate Function Input INT4 Function 4-bit input port (PORT0). An on-chip pull-up resistor can be specified by means of software in 3-bit units. 8-bit I/O After Reset I/O Circuit TYPE Note 1 No Input (B) P01 SCK P02 SO/SB0 (F)-B P03 SI/SB1 (M)-C P10 Input INT0 P11 INT1 P12 TI1/TI2/INT2 P13 TI0 P20 I/O PTO0 P21 PTO1 P22 PCL/PTO2 P23 BUZ P30 I/O LCDCL P31 SYNC P32 – P33 – P50 to P53Note 2 Notes 1. 2. I/O – (F)-A 4-bit input port (PORT1). An on-chip pull-up resistor can be specified by means of software in 4-bit units. P10/INT0 can select noise elimination circuit. No Input (B)-C 4-bit I/O port (PORT2). An on-chip pull-up resistor can be specified by means of software in 4-bit units. No Input E-B Programmable 4-bit I/O port (PORT3). Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software in 4-bit units. No Input E-B N-ch open-drain 4-bit I/O port (PORT5). An on-chip pull-up resistor can be specified in 1-bit units (mask option). Withstand voltage is 13 V in open-drain mode. No High level (when pullup resistors are provided) or highimpedance M-D Characters in parentheses indicate the Schmitt-triggered input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low-level input leakage current increases when input or bit manipulation instruction is executed. Data Sheet U10086EJ4V0DS00 9 µPD753104, 753106, 753108 3.1 Port Pins (2/2) Pin Name P60 I/O Alternate Function I/O KR0 P61 KR1 P62 KR2 P63 KR3 P80 I/O S23 P81 S22 P82 S21 P83 S20 P90 I/O S19 P91 S18 P92 S17 P93 S16 Notes 1. 2. 8-bit I/O After Reset I/O Circuit TYPENote 1 Programmable 4-bit I/O port (PORT6). Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software in 4-bit units. No Input (F)-A 4-bit I/O port (PORT8). An on-chip pull-up resistor can be specified by means of software in 4-bit unitsNote 2. Yes Input H Input H Function 4-bit I/O port (PORT9). An on-chip pull-up resistor can be specified by means of software in 4-bit unitsNote 2. Characters in parentheses indicate the Schmitt-triggered input. When these pins are used as segment signal output pins, do not connect the on-chip pull-up resistor by means of software. 10 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 3.2 Non-Port Pins (1/2) Pin Name TI0 I/O Alternate Function Input P13 TI1 P12/INT2/TI2 TI2 P12/INT2/TI1 PTO0 Output P20 PTO1 P21 PTO2 P22/PCL After Reset I/O Circuit TYPE Note 1 External event pulse input to the timer/event counter. Input (B)-C Timer/event counter output Input E-B Input (F)-A Function PCL P22/PTO2 BUZ P23 Optional frequency output (for buzzer output or system clock trimming) P01 Serial clock I/O SO/SB0 P02 Serial data output Serial data bus I/O (F)-B SI/SB1 P03 Serial data input Serial data bus I/O (M)-C SCK I/O Clock output INT4 Input P00 Edge detection vectored interrupt input (both rising edge and falling edge detection) Input (B) INT0 Input P10 Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 can select noise elimination circuit. Rising edge detection testable input Input (B)-C Input (F)-A INT1 P11 INT2 P12/TI1/TI2 KR0 to KR3 Noise elimination circuit/ asynchronous selection Asynchronous Asynchronous Input P60 to P63 S0 to S15 Output – Segment signal output Note 2 G-A S16 to S19 Output P93 to P90 Segment signal output Input H S20 to S23 Output P83 to P80 Segment signal output Input H COM0 to COM3 Output – Common signal output Note 2 G-B – – LCD drive power On-chip split resistor is enabled (mask option). – – BIAS Output – Output for external split resistor disconnect Note 3 – LCDCL Note 4 Output P30 Clock output for externally expanded driver Input E-B SYNC Note 4 Output P31 Clock output for externally expanded driver synchronization Input E-B V LC0 to V LC2 Notes 1. 2. 3. 4. Falling edge detection testable input Characters in parentheses indicate the Schmitt-triggered input. Each display output selects the following VLCX as input source. S0 to S15: V LC1, COM0 to COM2: VLC2, COM3: VLC0 When a split resistor is contained ........ Low level When no split resistor is contained ...... High impedance These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. Data Sheet U10086EJ4V0DS00 11 µPD753104, 753106, 753108 3.2 Non-Port Pins (2/2) I/O Alternate Function Function After Reset I/O Circuit TYPENote X1 Input – Crystal/ceramic connection pin for the main system clock oscillation. When the external clock is used, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. – – X2 – XT1 Input – Crystal connection pin for the subsystem clock oscillation. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. – – XT2 – Input – System reset input (low-level active) – (B) IC – – Internally connected. Connect directly to VDD. – – V DD – – Positive power supply – – V SS – – Ground potential – – Pin Name RESET Note 12 Characters in parentheses indicate the Schmitt-triggered input. Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 3.3 Pin I/O Circuits The µPD753108 pin input/output circuits are shown schematically. (1/2) TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN output disable N-ch N-ch Push-pull output that can be placed in output high-impedance (both P-ch and N-ch off). CMOS standard input buffer TYPE E-B TYPE B VDD P.U.R. P.U.R. enable P-ch IN data Type D IN/OUT output disable Type A Schmitt-triggered input with hysteresis characteristics P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-C VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch data output disable IN/OUT Type D IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor Data Sheet U10086EJ4V0DS00 13 µPD753104, 753106, 753108 (2/2) TYPE F-B TYPE H VDD P.U.R. P.U.R enable P-ch output disable (P) SEG data VDD IN/OUT TYPE G-A P-ch IN/OUT data output disable data N-ch output disable output disable (N) TYPE E-B P.U.R. : Pull-Up Resistor TYPE G-A TYPE M-C VDD P-ch N-ch VLC0 VLC1 P.U.R. P-ch N-ch P.U.R. enable P-ch P-ch N-ch IN/OUT data OUT N-ch output disable SEG data N-ch P-ch N-ch VLC2 N-ch P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-D P.U.R. (Mask Option) IN/OUT P-ch N-ch VLC0 VLC1 data P-ch N-ch P-ch output disable N-ch OUT input instruction COM data N-ch (+13 V withstand voltage) VDD P-ch Note P.U.R. N-ch P-ch P-ch N-ch VLC2 Voltage limitation circuit (+13 V withstand voltage) N-ch Note 14 VDD The pull-up resistor operates only when an input instruction is executed (current flows from VDD to the pin when the pin is low). Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 3.4 Recommended Connections of Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin Name Recommended Connection P00/INT4 Connect to VSS or VDD. P01/SCK At input: Independently connect to VSS or VDD via a resistor. P02/SO/SB0 At output: Leave open. P03/SI/SB1 Connect to VSS. P10/INT0, P11/INT1 Connect to VSS or V DD. P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 At input: Independently connect to VSS or VDD via a resistor. P21/PTO1 At output: Leave open. P22/PCL/PTO2 P23/BUZ P30/LCDCL P31/SYNC P32 P33 P50 to P53 At input: Connect to VSS. At output: Connect to VSS (do not connect a pull-up resistor of mask option). P60/KR0 to P63/KR3 At input: Independently connect to VSS or VDD via a resistor. At output: Leave open. S0 to S15 Leave open. COM0 to COM3 S16/P93 to S19/P90 At input: Independently connect to VSS or VDD via a resistor. S20/P83 to S23/P80 At output: Leave open. VLC0 to V LC2 Connect to VSS. BIAS Only if all of VLC0 to VLC2 are unused, connect to VSS. In other cases, leave open. XT1 Note Connect to VSS. XT2 Note Leave open. IC Connect directly to VDD. Note When the subsystem clock is not used, specify SOS.0 = 1 (so as not to use the on-chip feedback resistor). Data Sheet U10086EJ4V0DS00 15 µPD753104, 753106, 753108 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference Between Mk I Mode and Mk II Mode The CPU of the µ PD753108 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the stack bank select register (SBS). • Mk I mode: Upward compatible with the µPD75308B. Can be used in the 75XL CPU with a ROM capacity of up to 16 KB. • Mk II mode: Incompatible with the µPD75308B. Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than 16 KB. Table 4-1. Differences Between Mk I Mode and Mk II Mode Mk I Mode Number of stack bytes Mk II Mode 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles for subroutine instructions Caution The Mk II mode supports a program area exceeding 16 KB for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 KB. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility. 16 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 100×BNote at the beginning of a program. When using the Mk II mode, it must be initialized to 000×BNote. Note Set the desired value in the × position. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 Other than above setting prohibited 0 0 must be set in the bit 2 position. Mode switching specification 0 Mk II mode 1 Mk I mode Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode. Data Sheet U10086EJ4V0DS00 17 µPD753104, 753106, 753108 5. MEMORY CONFIGURATION Program Memory (ROM) .... 4096 × 8 bits (µPD753104) .... 6144 × 8 bits (µPD753106) .... 8192 × 8 bits (µPD753108) • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. • Addresses 0002H to 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt processing can start from any address. • Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. Data Memory (RAM) • Data area ... 512 words × 4 bits (000H to 1FFH) • Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH) 18 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Figure 5-1. Program Memory Map (1/3) (a) µPD753104 Address 7 6 0 0 0 H MBE RBE 0 0 2 H MBE RBE 0 0 4 H MBE RBE 0 0 6 H MBE RBE 0 0 8 H MBE RBE 0 0 A H MBE RBE 0 0 C H MBE RBE 5 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Internal reset start address (high-order 4 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 4 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 4 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 4 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 4 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 4 bits) INTT0 start address (low-order 8 bits) INTT1/INTT2 start address (high-order 4 bits) INTT1/INTT2 start address (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address –15 to –1, +2 to +16 BRCB !caddr instruction branch address 020H GETI instruction reference table 07FH 080H Branch destination address and subroutine entry address when GETI instruction is executed 7FFH 800H FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. Data Sheet U10086EJ4V0DS00 19 µPD753104, 753106, 753108 Figure 5-1. Program Memory Map (2/3) (b) µPD753106 Address 7 6 0 0 0 0 H MBE RBE 0 0 0 2 H MBE RBE 0 0 0 4 H MBE RBE 0 0 0 6 H MBE RBE 0 0 0 8 H MBE RBE 0 0 0 A H MBE RBE 0 0 0 C H MBE RBE 5 0 0 0 0 0 0 0 0 Internal reset start address (high-order 5 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 5 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 5 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 5 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 5 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 5 bits) INTT0 start address (low-order 8 bits) INTT1/INTT2 start address (high-order 5 bits) INTT1/INTT2 start address (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address –15 to –1, +2 to +16 BRCB !caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 17FFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 20 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Figure 5-1. Program Memory Map (3/3) (c) µPD753108 Address 7 6 0 0 0 0 H MBE RBE 0 0 0 2 H MBE RBE 0 0 0 4 H MBE RBE 0 0 0 6 H MBE RBE 0 0 0 8 H MBE RBE 0 0 0 A H MBE RBE 0 0 0 C H MBE RBE 5 0 0 0 0 0 0 0 0 Internal reset start address (high-order 5 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 5 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 5 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 5 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 5 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 5 bits) INTT0 start address (low-order 8 bits) INTT1/INTT2 start address (high-order 5 bits) INTT1/INTT2 start address (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address –15 to –1, +2 to +16 BRCB !caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. Data Sheet U10086EJ4V0DS00 21 µPD753104, 753106, 753108 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area Memory bank (32 × 4) 01FH 0 256 × 4 (224 × 4) Stack areaNote Data area static RAM (512 × 4) 0FFH 100H 256 × 4 (224 × 4) 1 Display data memory 1DFH 1E0H 1F7H 1F8H 1FFH (24 × 4) (8 × 4) Not incorporated F80H 128 × 4 Peripheral hardware area FFFH Note 22 Either memory bank 0 or 1 can be selected for the stack area. Data Sheet U10086EJ4V0DS00 15 µPD753104, 753106, 753108 6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port There are three kinds of I/O port. • CMOS input ports (PORT 0, 1): 8 • CMOS I/O ports (PORT 2, 3, 6, 8, 9): 20 • N-ch open-drain I/O ports (PORT 5): Total 4 32 Table 6-1. Types and Features of Digital Ports Port Name PORT0 Function 4-bit input PORT1 PORT2 4-bit I/O PORT3 Operation and Features Remarks When the serial interface function is used, the alternate function pins function as output ports depending on the operation mode. Also used for the INT4, SCK, SO/SB0, SI/SB1 pins. 4-bit input only port. Also used for the INT0 to INT2/TI1/TI2, TI0 pins. Input/output can be specified in 4-bit units. Also used for the PTO0 to PTO2/PCL, BUZ pins. Input/output can be specified in 1-bit units. Also used for the LCDCL, SYNC pins. PORT5 4-bit I/O (N-ch opendrain, 13 V withstand voltage) Input/output can be specified in 4-bit units. On-chip pull-up resistor can be specified in 1-bit units by mask option. PORT6 4-bit I/O Input/output can be specified in 1-bit units. Also used for the KR0 to KR3 pins. Input/output can be specified in 4-bit units. Also used for the S20 to S23 pins. PORT8 PORT9 Ports 8 and 9 are paired and data can be input/ output in 8-bit units. — Also used for the S16 to S19 pins. 6.2 Clock Generator The clock generator is a device that generates the clock which is supplied to peripheral hardware on the CPU and is configured as shown in Figure 6-1. The clock generator operates according to how the processor clock control register (PCC) and system clock control register (SCC) are set. There are two kinds of clocks, main system clock and subsystem clock. The instruction execution time can also be changed. • 0.95, 1.91, 3.81, 15.3 µ s (main system clock: @ 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µ s (main system clock: @ 6.0 MHz operation) • 122 µs (subsystem clock: @ 32.768 kHz operation) Data Sheet U10086EJ4V0DS00 23 µPD753104, 753106, 753108 Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · LCD controller/driver · INT0 noise elimination circuit · Clock output circuit XT1 VDD XT2 Subsystem clock oscillator fXT Main system clock oscillator fX LCD controller/driver Watch timer X1 VDD X2 1/1 to 1/4096 Divider 1/2 1/4 1/16 Selector WM.3 SCC Oscillation stop Divider SCC3 Selector 1/4 Internal bus SCC0 PCC Φ · CPU · INT0 noise elimination circuit · Clock output circuit PCC0 PCC1 4 HALT F/F PCC2 S HALTNote PCC3 STOPNote R PCC2, PCC3 Clear STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. 24 fX = Main system clock frequency 2. fXT = Subsystem clock frequency 3. Φ = CPU clock 4. PCC: Processor Clock Control register 5. SCC: System Clock Control register 6. One clock cycle (t CY) of the CPU clock is equal to one machine cycle of the instruction. Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 6.3 Subsystem Clock Oscillator Control Functions The µ PD753108 subsystem clock oscillator has the following two control functions. • Selects by means of software whether an on-chip feedback resistor is to be used or not Note. • Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (V DD ≥ 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the on-chip feedback resistor) by software, connect XT1 to V SS , and leave XT2 open. This makes it possible to reduce the current consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (See Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator SOS.0 Feedback resistor Inverter SOS.1 XT1 XT2 VDD Data Sheet U10086EJ4V0DS00 25 µPD753104, 753106, 753108 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL pin to the remote control wave outputs and peripheral LSI’s. Clock output (PCL): Φ, 524, 262, 65.5 kHz (main system clock: @ 4.19 MHz operation) Φ, 750, 375, 93.8 kHz (main system clock: @ 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram From clock generator Φ Selector From timer/event counter (channel 2) fX/23 Selector Output buffer fX/24 PCL/PTO2/P22 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 P22 output latch CLOM Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 26 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. Interval timer operation to generate a reference time interrupt Watchdog timer operation to detect a runaway of program and reset the CPU Selects and counts the wait time when the standby mode is released Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear fX/25 fX/27 MPX Clear Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 8 1 Internal bus Note Instruction execution Data Sheet U10086EJ4V0DS00 27 µPD753104, 753106, 753108 6.6 Watch Timer The µPD753108 has one watch timer channel which has the following functions. Sets the test flag (IRQW) at 0.5-second intervals. The standby mode can be released by the IRQW. 0.5-second interval can be created by both the main system clock (4.19 MHz) and subsystem clock (32.768 kHz). Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of system clock oscillation frequencies. Clears the frequency divider to make the watch start with zero seconds. Figure 6-5. Watch Timer Block Diagram fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) Selector fW (32.768 kHz) fXT (32.768 kHz) Divider fW 214 fLCD INTW IRQW set signal Selector 2 Hz 0.5 sec 4 kHz 2 kHz fW fW 23 24 Clear Selector Output buffer P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch Bit 2 of PMGB Port 2 I/O mode Bit test instruction Internal bus Remark The values enclosed in parentheses are applied when fX = 4.19 MHz and fXT = 32.768 kHz. 28 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 6.7 Timer/Event Counter The µPD753108 has three channels of timer/event counters. Its configuration is shown in Figures 6-6 to 6-8. The timer/event counter has the following functions. Programmable interval timer operation Square wave output of any frequency to the PTOn pin (n = 0 to 2) Event counter operation Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). Supplies the serial shift clock to the serial interface circuit. Reads the count value. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 Channel 2 Yes Yes Yes NoNote No Yes PWM pulse generator mode No No Yes 16-bit timer/event counter mode No Yes NoNote Yes No Yes Mode 8-bit timer/event counter mode Gate control function Gate control function Carrier generator mode Note Used for gate control signal generation Data Sheet U10086EJ4V0DS00 29 30 Figure 6-6. Timer/Event Counter (Channel 0) Block Diagram Internal bus 8 SET1Note 8 8 – TM06 TM05 TM04 TM03 TM02 0 TOE0 TMOD0 TM0 T0 enable flag Modulo register (8) – PORT2.0 P20 output latch Bit 2 of PMGB Port 2 I/O mode To serial interface 8 PORT1.3 TOUT0 Data Sheet U10086EJ4V0DS00 Match Comparator (8) TOUT F/F Output buffer 8 Input buffer PTO0/P20 Reset T0 TI0/P13 fX/24 INTT0 IRQT0 set signal Count register (8) MPX CP From fX/26 clock fX/28 generator fX/210 Clear Timer operation start To timer/event counter (channel 2) Note Instruction execution Caution When setting data to TM0, be sure to set bit 1 to 0. µPD753104, 753106, 753108 RESET IRQT0 clear signal Figure 6-7. Timer/Event Counter (Channel 1) Block Diagram Internal bus 8 Note SET1 TOE1 TM1 – 8 TM16 TM15 TM14 TM13 TM12 TM11 TM10 T1 enable flag TMOD1 Decoder PORT1.2 PORT2.1 P21 output latch Bit 2 of PMGB Port 2 I/O mode Modulo register (8) 8 TI1/TI2/P12/INT2 5 fX/2 fX/26 From clock 8 f X/2 generator fX/210 fX/212 MPX CP P21/PTO1 Output buffer Reset 8 Timer/event counter (channel 2) output TOUT F/F T1 Count register (8) Clear RESET Timer operation start 16-bit timer/event counter mode IRQT1 clear signal Selector Timer/event counter (channel 2) match signal (When 16-bit timer/event counter mode) Timer/event counter (channel 2) reload signal Timer/event counter (channel 2) comparator (When 16-bit timer/event counter mode) Note Instruction execution INTT1 IRQT1 set signal 31 µPD753104, 753106, 753108 Data Sheet U10086EJ4V0DS00 Match Comparator (8) Input buffer 32 Figure 6-8. Timer/Event Counter (Channel 2) Block Diagram Internal bus TMOD2H TM2 8 PORT1.2 Decoder 8 MPX (8) 8 Data Sheet U10086EJ4V0DS00 TI1/TI2/P12/INT2 fX fX/2 f From clock X/24 fX/26 generator fX/28 fX/210 Match TOUT F/F Reset 8 MPX CP PORT2.2 Bit 2 of PMGB P22 Port 2 output latch I/O TC2 TOE2 REMC NRZB NRZ Reload Comparator (8) Input buffer 8 TMOD2 Modulo register (8) TGCE High-level period setting modulo register (8) TM26 TM25 TM24 TM23 TM22 TM21 TM20 8 T2 Count register (8) Overflow P22/PCL/PTO2 Output buffer Selector 8 Selector SET1Note Selector 8 Timer/event counter (channel 1) clock input Carrier generator mode Clear INTT2 IRQT2 set signal 16-bit timer/event counter mode IRQT2 clear signal Timer operation start RESET Timer/event counter (channel 1) clear signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) match signal (When 16-bit timer/event counter mode) Note Instruction execution From clock output circuit Timer/event counter (channel 1) match signal (When carrier generator mode) µPD753104, 753106, 753108 Timer event counter (channel 0) TOUT F/F µPD753104, 753106, 753108 6.8 Serial Interface The µPD753108 incorporates a clock-synchronous 8-bit serial interface. The serial interface can be used in the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • SBI mode Data Sheet U10086EJ4V0DS00 33 34 Figure 6-9. Serial Interface Block Diagram Internal bus 8/4 Bit test 8 8 CSIM 8 Bit manipulation Bit test Slave address register (SVA) (8) SBIC RELT Address comparator Match CMDT (8) P03/SI/SB1 SO latch SET CLR Selector Shift register (SIO) D Q BSYE P02/SO/SB0 ACKE Data Sheet U10086EJ4V0DS00 ACKT (8) Busy/ acknowledge output circuit Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD Serial clock counter P01 output Iatch Serial clock control circuit INTCSI control circuit IRQCSI set signal Serial clock selector fX/23 fX/24 fX/26 TOUT0 (from timer/event counter (channel 0)) External SCK µPD753104, 753106, 753108 INTCSI P01/SCK µPD753104, 753106, 753108 6.9 LCD Controller/Driver The µPD753108 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The µPD753108 LCD controller/driver has the following functions: Display data memory is read automatically by DMA operation and segment and common signals are generated. Display mode can be selected from among the following five: <1> Static <2> 1/2 duty (time-divided by 2), 1/2 bias <3> 1/3 duty (time-divided by 3), 1/2 bias <4> 1/3 duty (time-divided by 3), 1/3 bias <5> 1/4 duty (time-divided by 4), 1/3 bias A frame frequency can be selected from among four in each display mode. A maximum of 24 segment signal output pins (S0 to S23) and four common signal output pins (COM0 to COM3). The segment signal output pins (S0 to S23) can be changed to the I/O ports (PORT8 and PORT9). Split resistor can be incorporated to supply LCD drive power (mask option). • Various bias methods and LCD drive voltages are applicable. • When display is off, current flowing through the split resistor is cut. Display data memory not used for display can be used for normal data memory. It can also operate by using the subsystem clock. Data Sheet U10086EJ4V0DS00 35 36 Figure 6-10. LCD Controller/Driver Block Diagram Internal bus 4 4 8 4 Port 8 output latch 4 4 Port 9 output latch Port mode 3 2 1 0 3 2 1 0 LCD/port selection register register group C 0 1 4 1F7H 3 2 1 0 1F0H 1EFH 3 2 1 0 3 2 1 0 1E0H 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8 4 Display mode register Display control register 4 4 Port 3 Port mode output latch register group A 1 0 1 0 Decoder Data Sheet U10086EJ4V0DS00 1 2 Port 9 I/O buffer 3 0 1 2 Segment driver Segment driver Common driver 3 S23/P80 S16/P93 S15 S0 LCD drive voltage control COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 LCD drive mode switching P31/SYNC P30/LCDCL µPD753104, 753106, 753108 Port 8 I/O buffer 0 Timing fLCD controller µPD753104, 753106, 753108 6.10 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-11. Bit Sequential Buffer Format FC3H Address 3 Bit Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H 2 1 0 BSB0 L = 4H L = 3H L = 0H DECS L INCS L Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register. 2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. Data Sheet U10086EJ4V0DS00 37 µPD753104, 753106, 753108 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD753108 has eight types of interrupt sources and two types of test sources. Of these test sources, INT2 has two types of edge detection testable inputs. The interrupt control circuit of the µPD753108 has the following functions. (1) Interrupt function • Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IE×××) and interrupt master enable flag (IME). • Can set any interrupt start address. • Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). • Test function of interrupt request flag (IRQ×××). An interrupt generation can be checked by software. • Release the standby mode. An interrupt to be released can be selected by the interrupt enable flag. (2) Test function • Test request flag (IRQ×××) generation can be checked by software. • Release the standby mode. The test source to be released can be selected by the test enable flag. 38 Data Sheet U10086EJ4V0DS00 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IME IPS IM2 IM1 IST1 IST0 Interrupt enable flag (IExxx) IM0 Decoder INT4/P00 INT0/P10 Note INT2/P12 KR0/P60 KR3/P63 IRQBT IRQ4 Edge detector IRQ0 Edge detector Rising edge detector VRQn IRQ1 INTCSI IRQCSI INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 INTW IRQW Selector IRQ2 Falling edge detector IM2 Note Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.) Priority control circuit Vector table address generator Standby release signal 39 µPD753104, 753106, 753108 Data Sheet U10086EJ4V0DS00 INT1/P11 Selector INTBT Both edge detector µPD753104, 753106, 753108 8. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD753108. Table 8-1. Operation Status in Standby Mode Mode Item STOP Mode HALT Mode Set instruction STOP instruction HALT instruction System clock when set Settable only when the main system clock is used. Settable both by the main system clock and subsystem clock. Operation status Clock generator Main system clock stops oscillation. Only the CPU clock Φ halts (oscillation continues). Basic interval timer/ watchdog timer Operation stops. Operable only when the main system clock is oscillated. BT mode : IRQBT is set in the reference time interval WT mode : Reset signal is generated by BT overflow Serial interface Operable only when an external SCK input is selected as the serial clock. Operable only when an external SCK input is selected as the serial clock or when the main system clock is oscillated. Timer/event counter Operable only when a signal input to the TI0 to TI2 pins is specified as the count clock. Operable only when a signal input to the TI0 to TI2 pins is specified as the count clock or when the main system clock is oscillated. Watch timer Operable when fXT is selected as the count clock. Operable. LCD controller/driver Operable only when fXT is selected as the Operable. LCDCL. External interrupt The INT1, 2, and 4 are operable. Only the INT0 is not operatedNote. CPU The operation stops. Release signal Note • Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag • Test request signal sent from the test source enabled by the test enable flag • RESET pin Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 40 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 9. RESET FUNCTION There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the configuration of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms: @ 6.00 MHz operation, 31.3 ms: @ 4.19 MHz operation) 2 15/fX (5.46 ms: @ 6.00 MHz operation, 7.81 ms: @ 4.19 MHz operation) Data Sheet U10086EJ4V0DS00 41 µPD753104, 753106, 753108 Table 9-1. Status of Each Hardware After Reset (1/2) RESET Signal Generation in the Standby Mode RESET Signal Generation in Operation Sets the low-order 4 bits of program memory’s address 0000H to the PC11 to PC8 and the contents of address 0001H to the PC7 to PC0. Sets the low-order 4 bits of program memory’s address 0000H to the PC11 to PC8 and the contents of address 0001H to the PC7 to PC0. µPD753106, Sets the low-order 5 bits of µPD753108 program memory’s address 0000H to the PC12 to PC8 and the contents of address 0001H to the PC7 to PC0. Sets the low-order 5 bits of program memory’s address 0000H to the PC12 to PC8 and the contents of address 0001H to the PC7 to PC0. Hardware Program counter (PC) PSW µPD753104 Carry flag (CY) Held Undefined Skip flag (SK0 to SK2) 0 0 Interrupt status flag (IST0, IST1) 0 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Basic interval Counter (BT) timer/watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer/event Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer/event Counter (T1) counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event Counter (T2) counter (T2) Modulo register (TMOD2) FFH FFH High-level period setting modulo register (TMOD2H) FFH FFH 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 TGCE 0 0 Mode register (WM) 0 0 Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB Watch timer 42 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Table 9-1. Status of Each Hardware After Reset (2/2) Serial interface Hardware RESET Signal Generation in the Standby Mode RESET Signal Generation in Operation Shift register (SIO) Held Undefined Operation mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Held Undefined Slave address register (SVA) Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 Sub-oscillator control register (SOS) 0 0 LCD controller/ Display mode register (LCDM) 0 0 driver Display control register (LCDC) 0 0 LCD/port selection register (LPS) 0 0 Reset (0) Reset (0) Interrupt Interrupt request flag (IRQxxx) function Interrupt enable flag (IExxx) 0 0 Interrupt priority selection register (IPS) 0 0 INT0, 1, 2 mode registers (IM0, IM1, IM2) 0, 0, 0 0, 0, 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, B, C) 0 0 Pull-up resistor setting register (POGA, B) 0 0 Held Undefined Digital port Bit sequential buffer (BSB0 to BSB3) Data Sheet U10086EJ4V0DS00 43 µPD753104, 753106, 753108 10. MASK OPTION The µPD753108 has the following mask options. Mask options of P50 to P53 Selects whether or not to internally connect a pull-up resistor. <1> Connect pull-up resistor internally in 1-bit units. <2> Do not connect pull-up resistor internally. VLC0 to VLC2 pins, BIAS pin mask option Selects whether or not to internally connect LCD-driving split resistors. <1> Do not connect split resistor internally. <2> Connect four 10 kΩ (TYP.) split resistors simultaneously internally. <3> Connect four 100 kΩ (TYP.) split resistors simultaneously internally. Standby function mask option Selects the wait time with the RESET signal. <1> 217/fx (21.8 ms: @ fx = 6.0 MHz operation, 31.3 ms: @ fx = 4.19 MHz operation) <2> 215/fx (5.46 ms: @ fx = 6.0 MHz operation, 7.81 ms: @ fx = 4.19 MHz operation) 44 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to “RA75X ASSEMBLER PACKAGE USERS’ MANUAL——LANGUAGE (U12385E)”. If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see User’s Manual. Expression Format Description Method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 rp2 rp' rp'1 BC, BC, XA, BC, rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or labelNote 2-bit immediate data or label fmem pmem FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr caddr faddr 0000H to 0FFFH 0000H to 17FFH 0000H to 1FFFH 0000H to 0FFFH 0000H to 17FFH 0000H to 1FFFH 12-bit immediate 11-bit immediate taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IExxx RBn MBn PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9 IEBT, IET0 to IET2, IE0 to IE2, IE4, IECSI, IEW RB0 to RB3 MB0, MB1, MB15 addr1 (Mk II mode only) DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' immediate data immediate data immediate data immediate data immediate data immediate data data or label data or label or or or or or or label label label label label label (µ PD753104) (µ PD753106) (µ PD753108) (µ PD753104) (µ PD753106) (µ PD753108) Note mem can be only used for even address in 8-bit data processing. Data Sheet U10086EJ4V0DS00 45 µPD753104, 753106, 753108 (2) Legend in explanation of operation 46 A: A register, 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: XA register pair; 8-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair XA’: XA’ expanded register pair BC’: BC’ expanded register pair DE’: DE’ expanded register pair HL’: HL’ expanded register pair PC: Program counter SP: Stack pointer CY: Carry flag, bit accumulator PSW: Program status word MBE: Memory bank enable flag RBE: Register bank enable flag PORTn: Port n (n = 0 to 3, 5, 6, 8, 9) IME: Interrupt master enable flag IPS: Interrupt priority selection register IE×××: Interrupt enable flag RBS: Register bank selection register MBS: Memory bank selection register PCC: Processor clock control register .: Separation between address and bit (××): The contents addressed by ×× ××H: Hexadecimal data Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 (3) Explanation of symbols under addressing area column *1 MB = MBE·MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 µ PD753104 addr = 000H to FFFH µ PD753106 addr = 0000H to 17FFH µ PD753108 addr = 0000H to 1FFFH *7 addr Data memory addressing = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 µ PD753104 caddr = 000H to FFFH µ PD753106 caddr = 0000H to 0FFFH (PC12 = 0) or 1000H to 17FFH (PC12 = 1) µ PD753108 caddr = 0000H to 0FFFH (PC12 = 0) or 1000H to 1FFFH (PC 12 = 1) *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH *11 µ PD753104 addr1 = 000H to FFFH µ PD753106 addr1 = 0000H to 17FFH µ PD753108 addr1 = 0000H to 1FFFH Remarks 1. Program memory addressing MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. Data Sheet U10086EJ4V0DS00 47 µPD753104, 753106, 753108 (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock Φ (= tCY); time can be selected from among four types by setting PCC. 48 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Instruction Group Transfer Mnemonic MOV XCH Number of Bytes Number of Machine Cycles A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ←→ (HL) *1 A, @HL+ 1 2+S A ←→ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ←→ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ←→ (rpa1) *2 XA, @HL 2 2 XA ←→ (HL) *1 A, mem 2 2 A ←→ (mem) *3 XA, mem 2 2 XA ←→ (mem) *3 A, reg1 1 1 A ←→ reg1 XA, rp' 2 2 XA ←→ rp' Operand Operation Data Sheet U10086EJ4V0DS00 Addressing Area Skip Condition String effect A 49 µPD753104, 753106, 753108 Instruction Group Table reference Mnemonic MOVT Operand Number of Bytes Number of Machine Cycles 1 3 XA, @PCDE Operation Addressing Area Skip Condition µPD753104 XA ← (PC11–8+DE)ROM µPD753106, 753108 XA ← (PC12–8+DE)ROM XA, @PCXA 1 3 µPD753104 XA ← (PC11–8+XA)ROM µPD753106, 753108 XA ← (PC12–8+XA)ROM Bit transfer Operation MOV1 ADDS ADDC SUBS SUBC Note XA, @BCDE 1 3 XA ← (BCDE)ROMNote *6 XA, @BCXA 1 3 XA ← (BCXA)ROMNote *6 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← (H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit) ← CY *1 A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry A, @HL 1 1+S A ← A+(HL) XA, rp' 2 2+S XA ← XA+rp' carry rp'1, XA 2 2+S rp'1 ← rp'1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp' 2 2 XA, CY ← XA+rp'+CY rp'1, XA 2 2 rp'1, CY ← rp'1+XA+CY A, @HL 1 1+S A ← A–(HL) XA, rp' 2 2+S XA ← XA–rp' borrow rp'1, XA 2 2+S rp'1 ← rp'1–XA borrow A, @HL 1 1 A, CY ← A–(HL)–CY XA, rp' 2 2 XA, CY ← XA–rp'–CY rp'1, XA 2 2 rp'1, CY ← rp'1–XA–CY carry *1 *1 borrow *1 Set “0” in B register if the µPD753104 is used. Only low-order one bit of B register will be valid if the µPD753106 or 753108 is used. 50 *1 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Instruction Group Operation Number of Bytes Number of Machine Cycles A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) XA, rp' 2 2 XA ← XA ∧ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∧ XA A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp' 2 2 XA ← XA ∨ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∨ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp' 2 2 XA ← XA v rp' rp'1, XA 2 2 rp'1 ← rp'1 v XA RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A INCS reg 1 1+S reg ← reg+1 reg = 0 rp1 1 1+S rp1 ← rp1+1 rp1 = 00H @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 reg 1 1+S reg ← reg–1 reg = FH rp' 2 2+S rp' ← rp'–1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic AND OR XOR Accumulator manipulation Increment and decrement DECS Comparison Carry flag manipulation SKE Operand Operation Skip if CY = 1 Addressing Area Skip Condition *1 *1 *1 CY = 1 CY ← CY Data Sheet U10086EJ4V0DS00 51 µPD753104, 753106, 753108 Instruction Group Memory bit manipulation Mnemonic SET1 CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 52 Number of Bytes Number of Machine Cycles mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 1 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 0 *1 (@H+mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 and clear *1 (@H+mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∧ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY v (H+mem3–0.bit) *1 Operand Operation Data Sheet U10086EJ4V0DS00 Addressing Area Skip Condition µPD753104, 753106, 753108 Instruction Group Branch Mnemonic BRNote Operand addr Number of Bytes Number of Machine Cycles – – Operation µPD753104 PC11–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. Addressing Area Skip Condition *6 µPD753106, 753108 PC12–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. addr1 – – µPD753104 PC11-0 ← addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 µPD753106, 753108 PC12–0 ← addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. !addr 3 3 µPD753104 PC11–0 ← addr *6 µPD753106, 753108 PC12–0 ← addr $addr 1 2 µPD753104 PC11–0 ← addr *7 µPD753106, 753108 PC12–0 ← addr $addr1 1 2 µPD753104 PC11–0 ← addr1 µPD753106, 753108 PC12–0 ← addr1 Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10086EJ4V0DS00 53 µPD753104, 753106, 753108 Instruction Group Branch Mnemonic BR Operand Number of Bytes Number of Machine Cycles 2 3 PCDE Operation Addressing Area Skip Condition µPD753104 PC11–0 ← PC11-8+DE µPD753106, 753108 PC12–0 ← PC12-8+DE PCXA 2 3 µPD753104 PC11–0 ← PC11-8+XA µPD753106, 753108 PC12–0 ← PC12-8+XA BCDE 2 3 µPD753104 PC11–0 ← BCDENote 1 *6 µPD753106, 753108 PC12–0 ← BCDENote 2 BCXA 2 3 µPD753104 PC11–0 ← BCXANote 1 *6 µPD753106, 753108 PC12–0 ← BCXANote 2 BRANote 3 !addr1 3 3 µPD753104 PC11–0 ← addr1 *11 µPD753106, 753108 PC12–0 ← addr1 BRCB !caddr 2 2 µPD753104 PC11–0 ← caddr11–0 *8 µPD753106, 753108 PC12–0 ← PC12+caddr11–0 Subroutine stack control Note 3 CALLA !addr1 3 3 µPD753104 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr1, SP ← SP–6 *11 µPD753106, 753108 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 PC12–0 ← addr1, SP ← SP–6 Notes 1. “0” must be set to B register. 2. Only low-order one bit is valid in B register. 3. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 54 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Instruction Group Subroutine stack control Mnemonic CALLNote Operand !addr Number of Bytes Number of Machine Cycles 3 3 Operation µPD753104 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← addr, SP ← SP–4 Addressing Area Skip Condition *6 µPD753106, 753108 (SP–3) ← MBE, RBE, 0, PC12 (SP–4) (SP–1) (SP–2) ← PC11–0 PC12–0 ← addr, SP ← SP–4 4 µPD753104 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr, SP ← SP–6 µPD753106, 753108 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 PC12–0 ← addr, SP ← SP–6 CALLFNote !faddr 2 2 µPD753104 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← 0+faddr, SP ← SP–4 *9 µPD753106, 753108 (SP–3) ← MBE, RBE, 0, PC12 (SP–4) (SP–1) (SP–2) ← PC11–0 PC12–0 ← 00+faddr, SP ← SP–4 3 µPD753104 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← 0+faddr, SP ← SP–6 µPD753106, 753108 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 PC12–0 ← 00+faddr, SP ← SP–6 Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10086EJ4V0DS00 55 µPD753104, 753106, 753108 Instruction Group Subroutine stack control Mnemonic RETNote Operand Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition µPD753104 PC11–0 ← (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4 µPD753106, 753108 PC11–0 ← (SP) (SP+3) (SP+2) MBE, RBE, 0, PC12 ← (SP+1), SP ← SP+4 µPD753104 ×, ×, MBE, RBE ← (SP+4) 0, 0, 0, 0, ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6 µPD753106, 753108 ×, ×, MBE, RBE ← (SP+4) MBE, 0, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6 RETSNote 1 3+S µPD753104 MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) SP ← SP+4 then skip unconditionally Unconditional µPD753106, 753108 MBE, RBE, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) SP ← SP+4 then skip unconditionally µPD753104 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) ×, ×, MBE, RBE ← (SP+4) SP ← SP+6 then skip unconditionally µPD753106, 753108 0, 0, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) ×, ×, MBE, RBE ← (SP+4) SP ← SP+4 then skip unconditionally Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 56 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Instruction Group Subroutine stack control Mnemonic Operand RETINote 1 Number of Bytes Number of Machine Cycles 1 3 Addressing Area Operation Skip Condition µPD753104 MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 µPD753106, 753108 MBE, RBE, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 µPD753104 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 µPD753106, 753108 0, 0, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 rp 1 1 (SP–1) (SP–2) ← rp, SP ← SP–2 BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP+1) (SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 2 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.3) ← 0 IE××× 2 2 IE××× ← 0 A, PORTn 2 2 A ← PORTn XA, PORTn 2 2 XA ← PORTn+1, PORTn PORTn, A 2 2 PORTn ← A PORTn, XA 2 2 PORTn+1, PORTn ← XA HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0 to 3) MBn 2 2 MBS ← n (n = 0, 1, 15) PUSH POP Interrupt control EI IE××× DI Input/output IN Note 2 OUTNote 2 CPU control Special SEL Notes 1. (n = 0 to 3, 5, 6, 8, 9) (n = 8) (n = 3, 5, 6, 8, 9) (n = 8) The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and MBS must be set to 15. Data Sheet U10086EJ4V0DS00 57 µPD753104, 753106, 753108 Instruction Group Mnemonic GETINote 1, 2 Special Operand taddr Number of Bytes Number of Machine Cycles 1 3 Operation µPD753104 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) Addressing Area Skip Condition *10 –––––––––––––––––––––––––––––––––– ––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← PC11–0 (SP–3) ← MBE, RBE, 0, 0 PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction µPD753106, 753108 • When TBR instruction PC12–0 ← (taddr) 4–0 + (taddr+1) –––––––––––––––––––––––––––––––––– ––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← PC11–0 (SP–3) ← MBE, RBE, 0, PC12 PC12–0 ← (taddr) 4–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 µPD753104 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) ––––––––––––––––––––––––––––––––––––– –––– 4 3 • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 µPD753106, 753108 • When TBR instruction PC12–0 ← (taddr) 4–0 + (taddr+1) ––––––––––––––––––––––––––––––––––––– –––– Notes 1. ––––––––––––– ––––––––––––– Depending on the reference instruction ––––––––––––– • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 (SP–2) ← ×, ×, MBE, RBE PC12–0 ← (taddr) 4–0 + (taddr+1) SP ← SP–6 ––––––––––––––––––––––––––––––––––––– –––– 3 *10 • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 (SP–2) ← ×, ×, MBE, RBE PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–6 ––––––––––––––––––––––––––––––––––––– –––– 4 Depending on the reference instruction • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. ––––––––––––– Depending on the reference instruction The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 2. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 58 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 12. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25˚C) Parameter Symbol Test Conditions Rating Unit –0.3 to +7.0 V Supply voltage V DD Input voltage V I1 Except port 5 –0.3 to VDD + 0.3 V V I2 Port 5 On-chip pull-up resistor –0.3 to VDD + 0.3 V When N-ch open-drain –0.3 to +14 V –0.3 to VDD + 0.3 V Per pin –10 mA Total of all pins –30 mA Per pin 30 mA Total of all pins 220 Output voltage VO Output current, high IOH Output current, low I OL –40 to +85 Operating ambient temperature TA Storage temperature T stg Note mA Note ˚C –65 to +150 ˚C When LCD is driven in normal mode: TA = –10 to +85˚C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. CAPACITANCE (TA = 25˚C, VDD = 0 V) Parameter Symbol Input capacitance CIN Output capacitance COUT I/O capacitance CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V. Data Sheet U10086EJ4V0DS00 MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 59 µPD753104, 753106, 753108 MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Resonator Recommended Constant Ceramic resonator frequency (fx) C1 C2 VDD Crystal resonator C2 VDD stabilization timeNote 3 lation voltage range MIN. 1.0 X2 Oscillation frequency (fx) VDD = 4.5 to 5.5 V Unit 6.0 Note 2 MHz 4 ms 6.0 Note 2 MHz 10 ms 30 1.0 6.0 Note 2 MHz 83.3 500 ns Note 1 X1 input high/low-level width (t XH, tXL) Notes 1. MAX. Note 1 X1 input X1 clock After V DD reaches oscil- stabilization timeNote 3 External TYP. Note 1 Oscillation frequency (fx) C1 MIN. 1.0 Oscillation X2 X1 Test Conditions Oscillation X2 X1 Parameter The oscillation frequency and X1 input frequency indicate only oscillator characteristics. Refer to the AC Characteristics for instruction execution time. 2. When the oscillation frequency is 4.19 MHz < fx ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle time being less than the required 0.95 µs. Therefore, set PCC to a value other than 0011. 3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 60 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Resonator Recommended Constant Crystal XT1 C3 R frequency (fXT) C4 Oscillation MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s Note 1 V DD = 4.5 to 5.5 V stabilization timeNote 2 VDD External XT1 input frequency XT1 10 32 100 kHz 5 15 µs XT2 (f XT) clock Test Conditions Oscillation XT2 resonator Parameter Note 1 X1 input high/low-level width (t XTH, tXTL) Notes 1. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD. Caution When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. The subsystem clock oscillator is designed as a low-amplification circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Data Sheet U10086EJ4V0DS00 61 µPD753104, 753106, 753108 RECOMMENDED OSCILLATOR CONSTANT Ceramic Resonator (TA = –20 to +85˚C) Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 C2 Oscillation Voltage Range (VDD) MIN. Kyocera KBR-1000F/Y 1.0 100 100 1.8 Corporation KBR-2.0MS 2.0 82 82 2.2 KBR-4.19MSA 4.19 33 33 1.8 KBR-4.19MKS — PBRC 4.19A 33 PBRC 4.19B KBR-6.0MSA On-chip capacitor product — On-chip capacitor product 33 33 PBRC 6.00B — — — — PBRC 6.00A 5.5 33 33 KBR-6.0MKS MAX. — — 6.0 Remarks — On-chip capacitor product 33 — — — On-chip capacitor product Ceramic Resonator (T A = –40 to +85˚C) Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 TDK CCR1000K2 1.0 CCR2.0MC33 2.0 FCR4.19MC5 4.19 150 — C2 150 Oscillation Voltage Range (VDD) MIN. 2.3 — Remarks MAX. 5.5 2.0 — On-chip capacitor product CCR4.19MC3 FCR6.0MC5 6.0 2.2 CCR6.0MC3 Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 62 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Ceramic Resonator (TA = –20 to +80˚C) Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 Oscillation Voltage Range (VDD) C2 MIN. Murata Mfg. CSB1000J 1.0 100 100 2.4 Co., Ltd. CSA2.00MG 2.0 30 30 1.8 CST2.00MGW CSA3.00MG — 3.0 30 CST3.00MGW CSA4.19MG 4.19 CSA5.00MG On-chip capacitor product — — On-chip capacitor product 30 2.2 CSA5.00MGU — — 2.2 CST5.00MGWU On-chip capacitor product 1.8 6.0 30 30 2.5 CSA6.00MGU — 1.8 CST6.00MGW — — 2.5 CST6.00MGWU Note — 1.8 CST5.00MGW CSA6.00MG — — 30 30 Rd = 5.6 kΩNote On-chip capacitor product — — 5.0 5.5 30 30 CST4.19MGW MAX. — — Remarks On-chip capacitor product 1.8 If using the CSB1000J (1.0 MHz) ceramic resonator manufactured by Murata Mfg. Co., Ltd., a limiting resistor (Rd = 5.6 kΩ) is required (see figure below). A limiting resistor is not required if using the other recommended resonators. Recommended Main System Clock Circuit Example (using Murata Mfg. Co., Ltd. CSB1000J) X1 X2 CSB1000J C1 Rd C2 VDD Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. Data Sheet U10086EJ4V0DS00 63 µPD753104, 753106, 753108 Crystal Resonator Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 Kinseki HC-49/U 2.0 15 C2 15 Oscillation Voltage Range (VDD) MIN. Remarks MAX. 1.8 5.5 6.0 2.5 5.5 4.19 1.8 5.5 6.0 2.5 5.5 TA = –20 to +70°C 4.19 HC-49/U-S TA = –10 to +70°C Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 64 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 DC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Output current, low Symbol I OL Test Conditions MIN. TYP. Per pin Total of all pins Input voltage, high VIH1 VIH2 VIH3 Input voltage, low X1, XT1 VIL1 Ports 2, 3, 5, 8, 9 VIL2 15 mA 150 mA 0.7VDD VDD V 1.8 ≤ V DD < 2.7 V 0.9VDD VDD V 2.7 ≤ V DD ≤ 5.5 V 0.8VDD VDD V 1.8 ≤ V DD < 2.7 V 0.9VDD VDD V On-chip pull-up 2.7 ≤ V DD ≤ 5.5 V 0.7VDD VDD V resistor 1.8 ≤ V DD < 2.7 V 0.9VDD VDD V When N-ch 2.7 ≤ V DD ≤ 5.5 V 0.7VDD 13 V open-drain 1.8 ≤ V DD < 2.7 V 0.9VDD 13 V V DD–0.1 VDD V 2.7 ≤ V DD ≤ 5.5 V 0 0.3V DD V 1.8 ≤ V DD < 2.7 V 0 0.1V DD V 2.7 ≤ V DD ≤ 5.5 V 0 0.2V DD V 1.8 ≤ V DD < 2.7 V 0 0.1V DD V 0 0.1 V Ports 0, 1, 6, RESET VIH4 Unit 2.7 ≤ V DD ≤ 5.5 V Ports 2, 3, 8, 9 Port 5 MAX. Ports 0, 1, 6, RESET VIL3 X1, XT1 Output voltage, high VOH SCK, SO, ports 2, 3, 6, 8, 9 IOH = –1.0 mA Output voltage, low VOL1 SCK, SO, ports 2, 3, 5, 6, 8, 9 V DD–0.5 I OL = 15 mA, V 0.2 2.0 V 0.4 V 0.2VDD V VDD = 4.5 to 5.5 V I OL = 1.6 mA VOL2 SB0, SB1 N-ch open-drain pull-up resistor ≥ 1 kΩ Input leakage I LIH1 V IN = VDD Pins other than X1, XT1 3 µA current, high I LIH2 X1, XT1 20 µA I LIH3 V IN = 13 V Port 5 (When N-ch open-drain) 20 µA Input leakage I LIL1 V IN = 0 V Pins other than X1, XT1, port 5 –3 µA current, low I LIL2 X1, XT1 –20 µA I LIL3 Port 5 (When N-ch open-drain) When input instruction is not executed –3 µA –30 –27 –8 µA µA µA Port 5 (When N-ch open-drain) When input VDD = 5.0 V instruction is executed VDD = 3.0 V –10 –3 I LOH1 V OUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9, port 5 (When N-ch open-drain) 3 µA I LOH2 V OUT = 13 V Port 5 (When N-ch open-drain) 20 µA Output leakage current, low I LOL V OUT = 0 V –3 µA On-chip pull-up resistor RL1 V IN = 0 V Output leakage current, high RL2 Ports 0 to 3, 6, 8, 9 (Excluding P00 pin) 50 100 200 kΩ Port 5 (When mask option is selected) 15 30 60 kΩ Data Sheet U10086EJ4V0DS00 65 µPD753104, 753106, 753108 DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter Symbol LCD drive voltage VLCD VAC0 = 0 Test Conditions MIN. TA = –40 to +85°C TA = –10 to +85°C VAC0 = 1 VAC current Note 1 LCD split resistor IVAC Note 2 LCD output voltage deviationNote 3 (common) LCD output voltage deviationNote 3 (segment) Supply current Note 4 Unit 2.7 V DD V 2.2 V DD V 1.8 V DD V 1 4 µA RLCD1 50 100 200 kΩ RLCD2 5 10 20 kΩ VODC VODS IDD1 IDD2 IDD1 IDD2 IDD3 I O = ±1.0 µA VLCD0 = V LCD VLCD1 = V LCD × 2/3 VLCD2 = V LCD × 1/3 1.8 V ≤ V LCD ≤ V DD 0 ±0.2 V I O = ±5.0 µA VLCD0 = V LCD VLCD1 = V LCD × 2/3 VLCD2 = V LCD × 1/3 2.2 V ≤ V LCD ≤ V DD 0 ±0.2 V I O = ±0.5 µA VLCD0 = V LCD VLCD1 = V LCD × 2/3 VLCD2 = V LCD × 1/3 1.8 V ≤ V LCD ≤ V DD 0 ±0.2 V I O = ±1.0 µA VLCD0 = V LCD VLCD1 = V LCD × 2/3 VLCD2 = V LCD × 1/3 2.2 V ≤ V LCD ≤ V DD 0 ±0.2 V 6.0 MHz Note 5 VDD = 5.0 V ±10%Note 6 1.9 6.0 mA Crystal oscillation VDD = 3.0 V ±10%Note 7 0.4 1.3 mA HALT mode V DD = 5.0 V ±10% 0.72 2.1 mA V DD = 3.0 V ±10% 0.27 0.8 mA VDD = 5.0 V ±10%Note 6 1.5 4.0 mA Crystal oscillation VDD = 3.0 V ±10%Note 7 0.25 0.75 mA HALT mode V DD = 5.0 V ±10% 0.7 2.0 mA V DD = 3.0 V ±10% 0.23 0.7 mA Low-voltage V DD = 3.0 V ±10% 12 35.0 µA V DD = 2.0 V ±10% 4.5 12.0 µA V DD = 3.0 V, TA = 25˚C 12 24.0 µA Low current consump- V DD = 3.0 V ±10% 6.0 18.0 µA tion modeNote 10 6.0 12.0 µA VDD = 3.0 V ±10% 8.5 25 µA VDD = 2.0 V ±10% 3.0 9.0 µA modeNote 9 VDD = 3.0 V, TA = 25˚C 8.5 17 µA Low current VDD = 3.0 V ±10% consumption modeNote 10 VDD = 3.0 V, TA = 25˚C 3.5 12 µA 3.5 7.0 µA C1 = C2 = 22 pF 4.19 MHzNote 5 C1 = C2 = 22 pF 32.768 kHz Note 8 Crystal oscillation modeNote 9 IDD4 V DD = 3.0 V, TA = 25˚C HALT mode Lowvoltage IDD5 XT1 = 0 V Note 11 VDD = 5.0 V ±10% 0.05 10 µA STOP mode VDD = 3.0 V 0.02 5.0 µA 0.02 3.0 µA ±10% 66 MAX. VAC0 = 1, V DD = 2.0 V ±10% TYP. T A = 25˚C Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Notes 1. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 µ A. 2. 3. Either R LCD1 or R LCD2 can be selected by the mask option. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). 4. Not including currents flowing in on-chip pull-up resistors or LCD split resistors. 5. Including oscillation of the subsystem clock. 6. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. 7. When PCC is set to 0000 and the device is operated in the low-speed mode. 8. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 9. When the sub-oscillator control register (SOS) is set to 0000. 10. When the SOS is set to 0010. 11. When the SOS is set to 00×1, and the sub-oscillator feedback resistor is not used (× : don’t care). Data Sheet U10086EJ4V0DS00 67 µPD753104, 753106, 753108 AC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol CPU clock cycle time t CY Test Conditions MAX. Unit 0.67 64 µs main system clock 0.95 64 µs Operating on subsystem clock 114 125 µs 0 1.0 MHz 0 275 kHz Operating on Note 1 (minimum instruction execution MIN. VDD = 2.7 to 5.5 V TYP. 122 time = 1 machine cycle) TI0, TI1, TI2 input f TI VDD = 2.7 to 5.5 V frequency TI0, TI1, TI2 input t TIH, tTIL 0.48 µs 1.8 µs IM02 = 0 Note 2 µs IM02 = 1 10 µs INT1, 2, 4 10 µs KR0-KR3 10 µs 10 µs VDD = 2.7 to 5.5 V high/low-level width Interrupt input high/ t INTH, tINTL INT0 low-level width RESET low-level width Notes 1. t RSL tCY vs VDD (At main system clock operation) The cycle time (minimum instruction execution time) of the CPU clock 64 60 (Φ) is determined by the oscillation frequency of the connected 6 system clock control register (SCC) 5 and the processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage V DD characteristic with the main system Cycle Time tCY [µs] resonator (and external clock), the Operation guaranteed range 4 3 2 clock operating. 2. 2tCY or 128/fx is set by setting the interrupt mode register (IM0). 1 0.5 0 1 2 3 4 5 Supply Voltage VDD [V] 68 Data Sheet U10086EJ4V0DS00 6 µPD753104, 753106, 753108 SERIAL TRANSFER OPERATION 2-Wire and 3-Wire Serial I/O Modes (SCK...Internal Clock Output): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high/low-level Symbol tKCY1 tKL1, tKH1 Test Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V width SI Note 1 setup time tSIK1 V DD = 2.7 to 5.5 V (to SCK↑) SI Note 1 hold time tKSI1 V DD = 2.7 to 5.5 V (from SCK↑) Delay time from SCK↓ tKSO1 to SONote 1 output Notes 1. 2. RL = 1 kΩ, Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY1/2–50 ns t KCY1/2–150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and C L are the load resistance and load capacitance of the SO output line. 2-Wire and 3-Wire Serial I/O Modes (SCK...External Clock Input): (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high/low-level Symbol tKCY2 tKL2, tKH2 Test Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V width SI Note 1 setup time tSIK2 V DD = 2.7 to 5.5 V (to SCK↑) SI Note 1 hold time tKSI2 V DD = 2.7 to 5.5 V (from SCK↑) Delay time from SCK↓ to SONote 1 output Notes 1. 2. tKSO2 RL = 1 kΩ, Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and C L are the load resistance and load capacitance of the SO output line. Data Sheet U10086EJ4V0DS00 69 µPD753104, 753106, 753108 SBI Mode (SCK...Internal Clock Output (Master)): (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high/low-level Symbol tKCY3 tKL3, tKH3 Test Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V width SB0, 1 setup time tSIK3 V DD = 2.7 to 5.5 V (to SCK↑) SB0, 1 hold time (from SCK↑) tKSI3 Delay time from SCK↓ tKSO3 to SB0, 1 output RL = 1 kΩ, Note VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY3/2–50 ns tKCY3/2–150 ns 150 ns 500 ns tKCY3/2 ns 0 250 ns 0 1000 ns SB0, 1↓ from SCK↑ tKSB tKCY3 ns SCK↓ from SB0, 1↓ tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns Note RL and C L are the load resistance and load capacitance of the SB0, SB1 output line. SBI Mode (SCK...External Clock Input (Slave)): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high/low-level Symbol tKCY4 tKL4, tKH4 Test Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V width SB0, 1 setup time tSIK4 V DD = 2.7 to 5.5 V (to SCK↑) SB0, 1 hold time (from SCK↑) tKSI4 Delay time from SCK↓ tKSO4 RL = 1 kΩ, Note VDD = 2.7 to 5.5 V CL = 100 pF to SB0, 1 output MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns tKCY4/2 ns 0 300 ns 0 1000 ns SB0, 1↓ from SCK↑ tKSB tKCY4 ns SCK↓ from SB0, 1↓ tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns Note 70 RL and C L are the load resistance and load capacitance of the SB0, SB1 output line. Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 AC Timing Test Point (Excluding X1, XT1 inputs) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock Timing 1/fX tXL tXH VDD–0.1 V 0.1 V X1 input 1/fXT tXTL tXTH VDD–0.1 V 0.1 V XT1 input TI0, TI1, TI2 Timing 1/fTI tTIL tTIH TI0, TI1, TI2 Data Sheet U10086EJ4V0DS00 71 µPD753104, 753106, 753108 Serial Transfer Timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 SI tKSI1, 2 Input data tKSO1, 2 SO Output data 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 72 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Serial Transfer Timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSIK3, 4 tSBK tKSI3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSIK3, 4 tSBK tKSI3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0 to 3 RESET input timing tRSL RESET Data Sheet U10086EJ4V0DS00 73 µPD753104, 753106, 753108 DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85˚C) Parameter Symbol Test Conditions MIN. Data retention supply voltage VDDDR 1.8 Release signal set time tSREL 0 Oscillation stabilization t WAIT wait time Notes 1. Note 1 TYP. MAX. Unit 5.5 V µs Release by RESET Note 2 ms Release by interrupt request Note 3 ms The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 2. Either 2 17/fX or 215/fX can be selected by the mask option. 3. Depends on the basic interval timer mode register (BTM) settings (see the table below). BTM3 BTM2 — — — — 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Wait time 220/fx 217/fx 215/fx 213/fx fx = at 4.19 MHz (approx. 250 ms) (approx. 31.3 ms) (approx. 7.81 ms) (approx. 1.95 ms) 220/fx 217/fx 215/fx 213/fx fx = at 6.0 MHz (approx. 175 ms) (approx. 21.8 ms) (approx. 5.46 ms) (approx. 1.37 ms) Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (Interrupt request) tWAIT 74 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) I DD vs VDD (Main System Clock: 6.0 MHz Crystal Resonator) (TA = 25°C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 Supply Current IDD (mA) 0.5 Main system clock HALT mode + 32 kHz oscillation 0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) and subsystem clock HALT mode (SOS.1 = 1) 0.01 0.005 X1 X2 XT1 Crystal resonator 22 pF 0.001 0 1 2 3 4 5 XT2 Crystal resonator 6.0 MHz 32.768 kHz 330 kΩ 22 pF 22 pF 22 pF VDD VDD 6 7 8 Supply Voltage VDD (V) Data Sheet U10086EJ4V0DS00 75 µPD753104, 753106, 753108 I DD vs VDD (Main System Clock: 4.19 MHz Crystal Resonator) (TA = 25°C) 10 5.0 PCC = 0011 1.0 PCC = 0010 PCC = 0001 PCC = 0000 Supply Current IDD (mA) 0.5 Main system clock HALT mode + 32 kHz oscillation 0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode (SOS.1 = 1) 0.01 0.005 X1 X2 XT1 Crystal resonator 22 pF 0.001 0 1 2 3 4 5 Supply Voltage VDD (V) 76 Data Sheet U10086EJ4V0DS00 XT2 Crystal resonator 4.19 MHz 32.768 kHz 330 kΩ 22 pF 22 pF 22 pF VDD VDD 6 7 8 µPD753104, 753106, 753108 I OH vs VDD—VOH (Ports 2, 3, 6, 8 and 9) (TA = 25°C) 15 10 VDD = 5 V VDD = 4 V IOH [mA] VDD = 5.5 V VDD = 2.2 V VDD = 3 V 5 0 VDD = 1.8 V 0 0.5 1.0 1.5 2.0 2.5 3.0 VDD—VOH [V] I OL vs VOL (Ports 2, 3, 6, 8 and 9) (TA = 25°C) 40 VDD = 5 V VDD = 4 V 30 VDD = 5.5 V VDD = 3 V IOL [mA] VDD = 2.2 V 20 VDD = 1.8 V 10 0 0 0.5 1.0 1.5 2.0 VOL [V] Data Sheet U10086EJ4V0DS00 77 µPD753104, 753106, 753108 14. PACKAGE DRAWINGS 64-PIN PLASTIC QFP (14 × 14) A B 33 32 48 49 detail of lead end S C D Q 64 1 R 17 16 F J G H I M P K S N S L M NOTE ITEM Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.6–0.4 B 14.0–0.2 C 14.0–0.2 D 17.6–0.4 F 1.0 G 1.0 H 0.37 +0.08 -0.07 I J 0.15 0.8 (T.P.) K 1.8–0.2 L 0.8–0.2 M 0.17 +0.08 -0.07 N 0.10 P 2.55–0.1 Q 0.1–0.1 R 5 –5 S 2.85 MAX. P64GC-80-AB8-5 78 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 64-PIN PLASTIC LQFP (12 × 12) A B 48 49 33 32 detail of lead end S C D Q 64 R 17 16 1 F G J H I M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 14.8–0.4 B 12.0–0.2 C 12.0–0.2 D 14.8–0.4 F 1.125 G 1.125 H I 0.32–0.08 0.13 J 0.65 (T.P.) K L 1.4–0.2 0.6–0.2 M 0.17 +0.08 -0.07 N 0.10 P 1.4–0.1 Q 0.125–0.075 R 5 –5 S 1.7 MAX. P64GK-65-8A8-3 Data Sheet U10086EJ4V0DS00 79 µPD753104, 753106, 753108 64-PIN PLASTIC TQFP (12 × 12) A B 48 detail of lead end 33 32 49 S P T C D R L U 64 Q 17 16 1 F G J H I M ITEM K S M N S NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A B 14.0–0.2 12.0–0.2 C 12.0–0.2 D F 14.0–0.2 1.125 G 1.125 H 0.32 +0.06 -0.10 I 0.13 J 0.65 (T.P.) K 1.0–0.2 L 0.5 M 0.17 +0.03 -0.07 N 0.10 P 1.0 Q 0.1–0.05 R 3 +4 -3 S 1.1–0.1 T 0.25 U 0.6–0.15 P64GK-65-9ET-2 80 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 15. RECOMMENDED SOLDERING CONDITIONS The µ PD753108 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions (1/2) (1) µPD753104GC-×××-AB8 : 64-pin plastic QFP (14 × 14) µPD753106GC-×××-AB8 : 64-pin plastic QFP (14 × 14) µPD753108GC-×××-AB8 : 64-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (at 210˚C min.), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215˚C, Time: 40 seconds max. (at 200˚C min.), Count: Three times or less VP15-00-3 Wave soldering Solder temperature: 260˚C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120˚C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin row) Caution — Do not use different soldering methods together (except for partial heating). (2) µPD753104GK-×××-8A8 : 64-pin plastic LQFP (12 × 12) µPD753106GK-×××-8A8 : 64-pin plastic LQFP (12 × 12) µPD753108GK-×××-8A8 : 64-pin plastic LQFP (12 × 12) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (at 210˚C min.), Count: Two times or less IR35-00-2 VPS Package peak temperature: 215˚C, Time: 40 seconds max. (at 200˚C min.), Count: Two times or less VP15-00-2 Wave soldering Solder temperature: 260˚C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120˚C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin row) Caution — Do not use different soldering methods together (except for partial heating). Data Sheet U10086EJ4V0DS00 81 µPD753104, 753106, 753108 Table 15-1. Surface Mounting Type Soldering Conditions (2/2) (3) µPD753104GK-×××-9ET : 64-pin plastic TQFP (12 × 12) µPD753106GK-×××-9ET : 64-pin plastic TQFP (12 × 12) µPD753108GK-×××-9ET : 64-pin plastic TQFP (12 × 12) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (at 210˚C min.), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125˚C for 10 hours) IR35-107-2 VPS Package peak temperature: 215˚C, Time: 40 seconds max. (at 200˚C min.), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125˚C for 10 hours) VP15-107-2 Wave soldering Solder bath temperature: 260˚C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120˚C max. (package surface temperature), Exposure limit: 7 daysNote (after that, prebake at 125˚C for 10 hours) WS60-107-1 Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period. Caution 82 — Do not use different soldering methods together (except for partial heating). Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 APPENDIX A. µPD75308B, 753108 AND 75P3116 FUNCTIONAL LIST Parameter Program memory µ PD75308B µ PD753108 µ PD75P3116 Mask ROM 0000H to 1F7FH (8064 × 8 bits) Mask ROM 0000H to 1FFFH (8192 × 8 bits) One-time PROM 0000H to 3FFFH (16384 × 8 bits) Data memory 000H to 1FFH (512 × 4 bits) CPU 75X Standard 75XL CPU When main system clock is selected 0.95, 1.91, 15.3 µs (during 4.19 MHz operation) • 0.95, 1.91, 3.81, 15.3 µs (during 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (during 6.0 MHz operation) When subsystem clock is selected 122 µs (32.768 kHz operation) SBS register None SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection Stack area 000H to 0FFH 000H to 1FFH Subroutine call instruction stack operation 2-byte stack When Mk I mode: 2-byte stack When Mk II mode: 3-byte stack BRA !addr1 CALLA !addr1 Unavailable When Mk I mode: unavailable When Mk II mode: available Instruction execution time Stack Instruction MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA I/O port Available CALL !addr 3 machine cycles Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles CMOS input 8 8 CMOS input/output 16 20 Bit port output 8 0 N-ch open-drain input/output 8 4 Total 40 32 Segment selection: 24/28/32 segments (can be changed to CMOS input/output port in 4 timeunit; max. 8) Segment selection: 16/20/24 segments (can be changed to CMOS input/output port in 4 time-unit; max. 8) LCD controller/driver Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD driver can be specified by using mask option. Timer 3 channels • Basic interval timer: 1 channel • 8-bit timer/event counter: 1 channel • Watch timer: 1 channel No on-chip split resistor for LCD driver 5 channels • Basic interval timer/watchdog timer: 1 channel • 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter) • Watch timer: 1 channel Data Sheet U10086EJ4V0DS00 83 µPD753104, 753106, 753108 µPD75308B Parameter µ PD753108 µPD75P3116 Clock output (PCL) • Φ, 524, 262, 65.5 kHz (Main system clock: during 4.19 MHz operation) • Φ, 524, 262, 65.5 kHz (Main system clock: during 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz (Main system clock: during 6.0 MHz operation) BUZ output (BUZ) • 2 kHz (Main system clock: during 4.19 MHz operation) • 2, 4, 32 kHz (Main system clock: during 4.19 MHz operation or subsystem clock: during 32.768 kHz operation) • 2.93, 5.86, 46.9 kHz (Main system clock: 6.0 MHz operation) Serial interface 3 • • • SOS register Feedback resistor cut flag (SOS.0) None Contained Sub-oscillator current cut flag (SOS.1) None Contained Register bank selection register (RBS) None Yes Standby release by INT0 Unavailable Available Vectored interrupt External: 3, internal: 3 External: 3, internal: 5 Supply voltage VDD = 2.0 to 6.0 V V DD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85˚C Package • 80-pin plastic QFP (14 × 20) • 80-pin plastic QFP (14 × 14) • 80-pin plastic TQFP (Fine pitch) (12 × 12) 84 modes are available 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit 2-wire serial I/O mode SBI mode • 64-pin plastic QFP (14 × 14) • 64-pin plastic LQFP (12 × 12) • 64-pin plastic TQFP (12 × 12) Data Sheet U10086EJ4V0DS00 • 64-pin plastic QFP (14 × 14) • 64-pin plastic LQFP (12 × 12) µPD753104, 753106, 753108 APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µ PD753108. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Host Machine OS PC-9800 Series MS-DOS™ Supply Media Part Number (Product Name) 3.5-inch 2HD µS5A13RA75X 3.5-inch 2HC µS7B13RA75X Ver. 3.30 to Ver. 6.2 Note IBM PC/AT™ and compatible machines Device file Refer to “OS for IBM PC ” Host Machine OS PC-9800 Series MS-DOS Supply Media Part Number (Product Name) 3.5-inch 2HD µS5A13DF753108 3.5-inch 2HC µS7B13DF753108 Ver. 3.30 to Ver. 6.2 Note IBM PC/AT and compatible machines Note Refer to “OS for IBM PC ” Ver. 5.00 and later have the task swap function, but it cannot be used for this software. Remark Operation of the assembler and the device file is guaranteed only on the above host machines and OSs. Data Sheet U10086EJ4V0DS00 85 µPD753104, 753106, 753108 PROM write tools Hardware Software PG-1500 PG-1500 is a PROM programmer which enables you to program single-chip microcontrollers including PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. PA-75P3116GC PROM programmer adapter for the µPD75P3116GC. Connect the programmer adapter to PG-1500 for use. PA-75P3116GK PROM programmer adapter for the µ PD75P3116GK. Connect the programmer adapter to PG-1500 for use. PG-1500 controller PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 Series MS-DOS Supply media Part number (product name) 3.5-inch 2HD µ S5A13PG1500 3.5-inch 2HD µ S7B13PG1500 Ver. 3.30 to Ver. 6.2Note IBM PC/AT and compatible machines Note Refer to “ OS for IBM PC” Ver. 5.00 and later have the task swap function, but it cannot be used for this software. Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. 86 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µ PD753108. The system configurations are described as follows. Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a µ PD753108 Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R or EP-753108GK-R) that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board (IE-75000-R-EM) which is connected. IE-75001-R In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a µ PD753108 Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R or EP-753108GK-R) that are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use a µ PD753108 Subseries. It must be used with the IE-75000-R or IE-75001-R. EP-753108GC-R Emulation probe for the µPD753108GC. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 64-pin conversion socket EV-9200GC-64 which facilitates connection to a target system. EV-9200GC-64 EP-753108GK-R TGK-064SBW Note 2 Software IE control program Emulation probe for the µPD753108GK. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 64-pin conversion adapter TGK-064SBW which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronics interface and controls the IE-75000-R or IE-75001-R on a host machine. Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Supply media Part No. (product name) 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 3.5-inch 2HC µS7B13IE75X 5-inch 2HC µS7B10IE75X Ver. 6.2Note 3 IBM PC/AT and compatible machines Notes 1. 2. Refer to “OS for IBM PC ” Maintenance product. This is a product of TOKYO ELETECH CORPORATION. Contact: Daimaru Kogyo, Ltd. Tokyo Electronic Department (TEL: +81-3-3820-7112) Osaka Electronic Department (TEL: +81-6-6244-6672) 3. Ver. 5.00 and later have the task swap function, but it cannot be used for this software. Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs. 2. The µ PD753104, 753106, 753108 and 75P3116 are commonly referred to as the µ PD753108 Subseries. Data Sheet U10086EJ4V0DS00 87 µPD753104, 753106, 753108 OS for IBM PC The following IBM PC OS’s are supported. OS Version PC DOS™ Ver. 3.1 to Ver. 6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/VNote IBM DOS™ J5.02/VNote Note Only the English mode is supported. Caution 88 Ver. 5.0 and later have the task swap function, but it cannot be used for this software. Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents Document No. Document Name English Japanese µPD753104, 753106, 753108 Data Sheet U10086E (This document) U10086J µPD75P3116 Data Sheet U11369E U11369J µPD753108 User’s Manual U10890E U10890J 75XL Series Selection Guide U10453E U10453J Development Tool Related Documents Document No. Document Name English Hardware Software Japanese IE-75000-R/IE-75001-R User’s Manual EEU-1416 EEU-846 IE-75300-R-EM User’s Manual U11354E U11354J EP-753108GC/GK-R User’s Manual EEU-1495 EEU-968 PG-1500 User’s Manual U11940E U11940J RA75X Assembler Package Operation U12622E U12622J User’s Manual Language U12385E U12385J PG-1500 Controller User’s Manual PC-9800 series (MS-DOS) base EEU-1291 EEU-704 IBM PC series (PC DOS) base U10540E EEU-5008 Other Related Documents Document No. Document Name English Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J — U11416J Guide to Microcomputer-Related Products by Third Party Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U10086EJ4V0DS00 89 µPD753104, 753106, 753108 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 90 Data Sheet U10086EJ4V0DS00 µPD753104, 753106, 753108 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Hong Kong Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 Data Sheet U10086EJ4V0DS00 91 µPD753104, 753106, 753108 MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of September, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4