SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 features DW OR N PACKAGE Four 8-Bit D/A Converters Microprocessor Compatible TTL/CMOS Compatible Single Supply Operation Possible CMOS Technology (TOP VIEW) OUTB OUTA VSS REF AGND DGND DB7 DB6 DB5 DB4 applications D Process Control D Automatic Test Equipment D Automatic Calibration of Large System Parameters, e.g. Gain/Offset description 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 OUTC OUTD VDD A0 A1 WR DB0 DB1 DB2 DB3 OUTA OUTB OUTC OUTD V SS FK PACKAGE (TOP VIEW) 3 2 1 20 19 REF 4 18 VDD AGND 5 17 A0 DGND 6 16 A1 DB7 7 15 WR DB6 8 14 DB0 DB1 10 11 12 13 DB2 Each DAC includes an output buffer amplifier capable of sourcing up to 5 mA of output current. 9 DB4 Separate on-chip latches are provided for each of the four DACs. Data is transferred into one of these data latches through a common 8-bit TTL /CMOS-compatible 5-V input port. Control inputs A0 and A1 determine which DAC is loaded when WR goes low. The control logic is speed compatible with most 8-bit microprocessors. 20 2 DB5 The TLC7226C, TLC7226I, and TLC7226M consist of four 8-bit voltage-output digital-toanalog converters (DACs) with output buffer amplifiers and interface logic on a single monolithic chip. 1 DB3 D D D D D The TLC7226 performance is specified for input reference voltages from 2 V to VDD − 4 V with dual supplies. The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply rail at a reference of 10 V. The TLC7226 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common 8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to microprocessors. All latch-enable signals are level triggered. Combining four DACs, four operational amplifiers, and interface logic into either a 0.3-inch wide, 20-terminal dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOIC) allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. The Leadless Ceramic Chip Carrier (LCCC) package provides for operation at military temperature range. The pinout is aimed at optimizing board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at the other. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 description (continued) The TLC7226C is characterized for operation from 0°C to 70°C. The TLC7226I is characterized for operation from −25°C to 85°C. The TLC7226M is characterized for operation from − 55°C to 125°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (DW) PLASTIC DIP (N) LCCC (FK) 0°C to 70°C TLC7226CDW TLC7226CN — −25°C to 85°C TLC7226IDW TLC7226IN — −55°C to 125°C — — TLC7226MFKB functional block diagram REF 4 _ 8 Latch A 8 Latch B 8 Latch C 8 Latch D 8 _ 8 DB0 −DB7 7 −14 8 DAC B 15 WR 17 A0 16 A1 + DAC D Control Logic schematic of outputs EQUIVALENT ANALOG OUTPUT VDD Output 450 µA VSS 2 POST OFFICE BOX 655303 OUTA 20 OUTB OUTC + DAC C _ 8 1 + _ 8 2 + DAC A • DALLAS, TEXAS 75265 19 OUTD SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 Terminal Functions TERMINAL NAME NO.† AGND 5 A0, A1 17, 16 DGND 6 DB0 −DB7 I/O DESCRIPTION Analog ground. AGND is the reference and return terminal for the analog signals and supply. I DAC select inputs. The combination of high or low levels select either DACA, DACB, DACC, or DACD. Digital ground. DGND is the reference and return terminal for the digital signals and supply. 14−7 I Digital DAC data inputs. DB0 −DB7 are the input digital data used for conversion. OUTA 2 O DACA output. OUTA is the analog output of DACA. OUTB 1 O DACB output. OUTB is the analog output of DACB. OUTC 20 O DACC output. OUTC is the analog output of DACC. OUTD 19 O DACD output. OUTD is the analog output of DACD. REF 4 I Voltage reference input. The voltage level on REF determines the full scale analog output. VDD VSS 18 Positive supply voltage input terminal 3 Negative supply voltage input terminal WR 15 I Write input. WR selects DAC transparency or latch mode. The selected input latch is transparent when WR is low. † Terminal numbers shown are for the DW, N, and FK packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD: AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 17 V VSS‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 24 V Supply voltage range, VSS: AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7 V to 0.3 V Voltage range between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −17 V to 17 V Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V Reference voltage range: Vref (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD Vref (to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 20 V Output voltage range, VO (to AGND) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Continuous total power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 500 mW Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C E suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N packages . . . . . . . . . . . . . . 260°C Case temperature for 10 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ The VSS terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device. NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 60 mA. 2. For operation above TA = 75°C, derate linearly at the rate of 2 mW/°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 recommended operating conditions MIN MAX UNIT Supply voltage, VDD 11.4 16.5 V Supply voltage, VSS −5.5 0 V High-level input voltage, VIH 2 V Low-level input voltage, VIL Reference voltage, Vref 0 Load resistance, RL 0.8 V VDD −4 V 2 kΩ Setup time, address valid before WR↓, tsu(AW) (see Figure 1) VDD = 11.4 V to 16.5 V *0 ns Setup time, data valid before WR↑, tsu(DW) (see Figure 1) VDD = 11.4 V to 16.5 V *45 ns Hold time, address valid after WR↑, th(AW) (see Figure 1) VDD = 11.4 V to 16.5 V *0 ns Hold time, data valid after WR↑, th(DW) (see Figure 1) VDD = 11.4 V to 16.5 V *10 ns Pulse duration, WR low, tw (see Figure 1) VDD = 11.4 V to 16.5 V C suffix *50 ns 0 70 Operating free-air temperature, TA I suffix −25 85 M suffix −55 125 °C C * This parameter is not tested for M suffix devices. electrical characteristics over recommended operating free-air temperature range dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V (unless otherwise noted) PARAMETER II TEST CONDITIONS Input current, digital I(DD) Supply current I(SS) ri(ref) Supply current VI = 0 V or VDD VI = 0.8 V or 2.4 V, VSS = − 5 V, VDD = 16.5 V, No load VI = 0.8 V or 2.4 V, No load Reference input resistance 2 ∆VDD = ± 5% Power supply sensitivity C and I suffix REF input Ci All 0s loaded M suffix All 1s loaded Input capacitance C and I suffix Digital inputs M suffix * This parameter is not tested for M suffix devices. 4 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX UNIT ±1 µA 6 16 mA 4 10 mA 0.01 %/% *300 pF 4 kΩ 65 *30 8 *12 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 operating characteristics over recommended operating free-air temperature range dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS Slew rate MIN TYP MAX *2.5 V•µs Positive full scale Settling time to 1/2 LSB Negative full scale *5 Vref = 10 V *7 Resolution 8 Total unadjusted error Linearity error Differential/integral Full-scale error VDD = 15 V ± 5%, Vref = 10 V VDD = 14 V to 16.5 V, Vref = 10 V Full scale Temperature coefficient of gain Zero-code error ±2 LSB ±1 LSB ±2 LSB Digital crosstalk glitch impulse area Vref = 0 LSB ± 20 ppm/°C ± 50 µV/°C ± 20 Zero-code error µss bits ± 0.25 Gain error UNIT ± 80 50 mV nV•s * This parameter is not tested for M suffix devices. single power supply, VDD = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, Vref = 10 V (unless otherwise noted) PARAMETER TEST CONDITIONS Supply current, IDD VI = 0.8 V or 2.4 V, Slew rate Settling time to 1/2 LSB MIN No load TYP MAX 5 13 *2 mA V•µs Positive full scale *5 Negative full scale *20 Resolution UNIT 8 µss bits Total unadjusted error ±2 LSB Full-scale error ±2 LSB Full scale Temperature coefficient of gain Linearity error VDD = 14 V to 16.5 V, Zero-code error Vref = 10 V ± 20 ppm/°C ± 50 µV/°C ±1 Differential Digital crosstalk-glitch impulse area 50 LSB nV•s * This parameter is not tested for M suffix devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 PARAMETER MEASUREMENT INFORMATION tsu(DW) VDD Data 0V th(DW) VDD Address 0V th(AW) tsu(AW) tw VDD WR 0V NOTES: A. tr = tf = 20 ns over VDD range. B. The timing measurement reference level is equal to VIH + VIL divided by 2. C. The selected input latch is transparent while WR is low. Invalid data during this time can cause erroneous outputs. Figure 1. Write-Cycle Voltage Waveforms TYPICAL CHARACTERISTICS OUTPUT CURRENT (SINK) vs OUTPUT VOLTAGE OUTPUT CURRENT vs OUTPUT VOLTAGE 700 200 VDD = 15 V 600 Source Current Short-Circuit Limiting 100 I O − Output Current (Sink) − µ A I O − Output Current − mA 150 50 0 −0.1 TA = 25°C VSS = − 5 V Digital In = 0 V −0.2 −0.3 Sinking Current Source −0.4 −2 −1 0 1 TA = 25°C VDD = 15 V 500 400 VSS = 0 300 200 100 0 2 VSS = − 5 V 0 1 Figure 2 6 2 3 4 5 Figure 3 POST OFFICE BOX 655303 6 7 VO − Output Voltage − V VO − Output Voltage − V • DALLAS, TEXAS 75265 8 9 10 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 PRINCIPLES OF OPERATION AGND bias for direct bipolar output operation The TLC7226 can be used in bipolar operation without adding more external operational amplifiers as shown in Figure 4 by biasing AGND to VSS. This configuration provides an excellent method for providing a direct bipolar output with no additional components. The transfer values are shown in Table 1. REF (Vref = 5 V) 4 18 VDD TLC7226‡ _ OUT 2 AGND + DAC A 5 3 Output range (5 V to − 5 V) 6 DGND VSS −5 V ‡ Digital inputs omitted for clarity. Figure 4. AGND Bias for Direct Bipolar Operation Table 1. Bipolar (Offset Binary) Code DAC LATCH CONTENTS MSB LSB ANALOG OUTPUT ǒ Ǔ 1111 1111 )V 127 ref 128 1000 0001 )V 1 ref 128 1000 0000 0111 1111 0000 0001 0000 0000 ǒ Ǔ 0V ǒ Ǔ * V ǒ127Ǔ ref 128 –V ǒ128Ǔ + * V ref ref 128 *V 1 ref 128 AGND bias for positive output offset The TLC7226 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an offset analog output voltage level. Figure 5 shows a circuit configuration to achieve this for channel A of the TLC7226. The output voltage, VO, at OUTA can be expressed as: V O +V BIAS )D A ǒVIǓ (1) where DA is a fractional representation of the digital input word (0 ≤ D ≤ 255/256). Increasing AGND above system GND reduces the output range. VDD − Vref must be at least 4 V to ensure specified operation. Since the AGND terminal is common to all four DACs, this method biases up the output voltages of all the DACs in the TLC7226. Supply voltages VDD and VSS for the TLC7226 should be referenced to DGND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 PRINCIPLES OF OPERATION AGND bias for positive output offset (continued) Vref 4 18 VDD TLC7226† VI _ 2 AGND OUTA + DAC A 5 3 Vbias 6 DGND VSS † Digital inputs omitted for clarity. Figure 5. AGND Bias Circuit interface logic information Address lines A0 and A1 select which DAC accepts data from the input port. Table 2 shows the operations of the four DACs. Figure 6 shows the input control logic. When the WR signal is low, the input latches of the selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value corresponding to the data held in their respective latches. Table 2. Function Table CONTROL INPUTS WR A1 A0 H X X L ↑ L ↑ L ↑ L ↑ L L L L H H H H L L H H L L H H L = low, 8 H = high, OPERATION No operation Device not selected DAC A transparent DAC A latched DAC B transparent DAC B latched DAC C transparent DAC C latched DAC D transparent DAC D latched X = irrelevant POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 PRINCIPLES OF OPERATION interface logic information (continued) A0 A1 17 To Latch A 16 To Latch B To Latch C WR To Latch D 15 Figure 6. Input Control Logic unipolar output operation The unipolar output operation is the basic mode of operation for each channel of the TLC7226, with the output voltages having the same positive polarity as Vref. The TLC7226 can be operated with a single power supply (VSS = AGND) or with positive/negative power supplies. The voltage at Vref must never be negative with respect to AGND to prevent parasitic transistor turnon. Connections for the unipolar output operation are shown in Figure 7. Transfer values are shown in Table 3. Table 3. Unipolar Code _ REF 4 DAC A 2 OUTA + _ 1 DAC B _ DAC C OUTB + 20 + OUTC _ 19 DAC D + OUTD DAC LATCH CONTENTS MSB LSB ANALOG OUTPUT ǒ Ǔ 255 ref 256 1111 1111 )V 1000 0001 )V 1000 0000 ǒ Ǔ V ) V ǒ128Ǔ + ) ref ref 256 2 0111 1111 )V 0000 0001 0000 0000 129 ref 256 ǒ Ǔ )V ǒ 1 Ǔ ref 256 127 ref 256 0V ǒ NOTE A. 1 LSB + V ref Ǔ 2– 8 + V ǒ Ǔ 1 ref 256 Figure 7. Unipolar Output Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 PRINCIPLES OF OPERATION linearity, offset, and gain error using single-ended power supplies When an amplifier is operated from a single power supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot be driven to a negative voltage. So when the output offset voltage is negative, the output voltage remains at zero volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in a transfer function shown in Figure 8. Output Voltage 0V DAC Code Negative Offset Figure 8. Effect of Negative Offset (Single Power Supply) This negative offset error, not the linearity error, produces the breakpoint. The transfer function would have followed the dotted line if the output buffer could be driven to a negative voltage. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single power supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full scale code and the lowest code which produces a positive output voltage. The code is calculated from the maximum specification for the negative offset. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 APPLICATION INFORMATION bipolar output operation using external amplifier Each of the DACs of the TLC7226 can also be individually configured to provide bipolar output operation, using an external amplifier and two resistors per channel. Figure 9 shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the TLC7226. In this case: V O with R1 + R2 V O ǒDA + 1 ) R2 R1 ǒ Ǔ + 2D * 1 A V V Ǔ * R2 ǒVrefǓ R1 (2) ref ref where D is a fractional representation of the digital word in latch A. A Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track over temperature. The TLC7226 can be operated with a single power supply or from positive and negative power supplies. REF R1† R2† 4 15 V TLC7226 _ _ DAC A 2 + VO + −15 V † R1 = R2 = 10 kΩ ±0.1% Figure 9. Bipolar Output Circuit staircase window comparator In many test systems, it is important to be able to determine whether some parameter lies within defined limits. The staircase window comparator shown in Figure 10 is a circuit that can be used to measure the VOH and VOL thresholds of a TTL device under test. Upper and lower limits on both VOH and VOL can be programmed using the TLC7226. Each adjacent pair of comparators forms a window of programmable size (see Figure 11). When the test voltage (Vtest) is within a window, then the output for that window is higher. With a reference of 2.56 V applied to the REF input, the minimum window size is 10 mV. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 APPLICATION INFORMATION staircase window comparator (continued) 5V Reference Voltage Vtest From DUT 10 kΩ + _ 4 Window 1 REF + _ 5V OUTA 2 VOH 10 kΩ + _ Window 2 + _ TLC7226 OUTB 1 VOH 5V 10 kΩ + _ Window 3 + _ 5V OUTC 20 VOL 10 kΩ + _ Window 4 + _ OUTD 19 VOL 10 kΩ + _ Window 5 AGND 5 + _ Figure 10. Logic Level Measurement 12 POST OFFICE BOX 655303 5V • DALLAS, TEXAS 75265 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 APPLICATION INFORMATION staircase window comparator (continued) REF Window 1 OUTA Window 2 OUTB Window 3 OUTC Window 4 OUTD Window 5 AGND Figure 11. Adjacent Window Structure The circuit can easily be adapted as shown in Figure 12 to allow for overlapping of windows. When the three outputs from this circuit are decoded, five different nonoverlapping programmable window possibilities can again be defined (see Figure 13). 5V Reference Voltage Vtest From DUT 10 kΩ + _ 4 Window 1 REF OUTA OUTB 2 5V 1 OUTD 10 kΩ + _ Window 2 TLC7226 OUTC + _ 20 19 AGND 5 + _ 5V 10 kΩ + _ Window 3 + _ Figure 12. Overlapping Window Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 APPLICATION INFORMATION staircase window comparator (continued) REF Window 1 OUTB Windows 1 and 2 OUTA Window 2 OUTD Windows 2 and 3 OUTC Window 3 AGND Figure 13. Overlapping Window Structure output buffer amplifier The unity-gain output amplifier is capable of sourcing 5 mA into a 2-kΩ load and can drive a 3300-pF capacitor. The output can be shorted to AGND indefinitely or it can be shorted to any voltage between VSS and VDD consistent with the maximum device power dissipation. multiplying DAC The TLC7226 can be used as a multiplying DAC when the reference signal is maintained between 2 V and VDD − 4 V. When this configuration is used, VDD should be 14.25 V to 15.75 V. A low output-impedance buffer should be used so that the input signal is not loaded by the resistor ladder. Figure 14 shows the general schematic. 15 V 1/4 TLC7226 R1 15 V _ 4 + AC Reference Input Signal _ Vref OP07 DAC AGND 5 R2 Figure 14. AC Signal Input Scheme 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VO + DGND 6 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN PINS ** 0.050 (1,27) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°−ā 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 03/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 MECHANICAL INFORMATION FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. 16 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23.37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21.59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0°−ā 15° 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-87802012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-87802012C ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type TLC7226CDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226CDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226CN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7226CNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7226IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7226IN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7226INE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7226MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2007 accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC7226CDWR DW 20 SITE 60 330 24 10.8 13.1 2.65 12 24 Q1 TLC7226IDWR DW 20 SITE 60 330 24 10.8 13.1 2.65 12 24 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TLC7226CDWR DW 20 SITE 60 346.0 346.0 41.0 TLC7226IDWR DW 20 SITE 60 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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